From: Frank Oltmanns <frank@oltmanns.dev>
To: jagan@amarulasolutions.com, michael@amarulasolutions.com,
Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Samuel Holland <samuel@sholland.org>,
dri-devel@lists.freedesktop.org (open list:DRM DRIVERS FOR
ALLWINNER A10),
linux-arm-kernel@lists.infradead.org (moderated
list:ARM/Allwinner sunXi SoC support),
linux-sunxi@lists.linux.dev (open list:ARM/Allwinner sunXi SoC
support), linux-kernel@vger.kernel.org (open list)
Cc: Frank Oltmanns <frank@oltmanns.dev>
Subject: [PATCH 0/1] Fixing the DSI dot clock on Allwinner
Date: Sun, 19 Mar 2023 17:07:03 +0100 [thread overview]
Message-ID: <20230319160704.9858-1-frank@oltmanns.dev> (raw)
According to the Allwinner A64's BSP code, the PLL rate needs to be set to the following frequency when using DSI:
PLL rate = DCLK * bpp / lanes
Source: [1]
The relevant lines for DSI (ommisions and comments mine):
dclk_rate = lcdp->panel_info.lcd_dclk_freq * 1000000;
lcd_rate = dclk_rate * clk_info.dsi_div; // dsi_div = bpp/lane
pll_rate = lcd_rate * clk_info.lcd_div; // lcd_div = 1 --> pll_rate = lcd_rate
dsi_rate = pll_rate / clk_info.dsi_div // --> dsi_rate = dclk_rate
clk_set_rate(lcdp->clk_parent, pll_rate);
This was already discussed by Maxime, Jagan and Michael in the past in the thread following this message: [2]. Unfortunately, there never was a conclusion in the form of code.
The attached patch is a slight variation of a patch that is part of megi's kernel branch that many PinePhone distributions (e.g. postmarketOS) use [3]. It calculates the TCON clock rate by using the formula above and dividing it by SUN6I_DSI_TCON_DIV, in order to force the parent clock to be set to the correct rate.
If I read the thread following this message [2] correctly, this was also what Maxime had in mind.
Please also note that, unfortunately, I only have a single board and panel (namely the PinePhone) to test this on.
Thanks,
Frank
[1] https://github.com/BPI-SINOVOIP/BPI-M64-bsp/blob/master/linux-sunxi/drivers/video/sunxi/disp2/disp/de/disp_lcd.c#L781
[2] https://lore.kernel.org/lkml/CAMty3ZAsH2iZ+JEqTE3D58aXfGuhMSg9YoO56ZhhOeE4c4yQHQ@mail.gmail.com/
[3] https://github.com/megous/linux/commit/eb5f28fb58727f4a6546f211486aad0d19cdea3f
Frank Oltmanns (1):
drm/sun4i: tcon: Fix setting PLL rate when using DSI
drivers/gpu/drm/sun4i/sun4i_tcon.c | 46 ++++++++++++++++++++----------
1 file changed, 31 insertions(+), 15 deletions(-)
--
2.39.2
next reply other threads:[~2023-03-19 16:08 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-19 16:07 Frank Oltmanns [this message]
2023-03-19 16:07 ` [PATCH 1/1] drm/sun4i: tcon: Fix setting PLL rate when using DSI Frank Oltmanns
2023-03-21 14:57 ` Maxime Ripard
2023-03-21 19:55 ` Frank Oltmanns
2023-03-22 3:25 ` Roman Beranek
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