From: Maxime Ripard <maxime@cerno.tech>
To: Frank Oltmanns <frank@oltmanns.dev>
Cc: jagan@amarulasolutions.com, michael@amarulasolutions.com,
Chen-Yu Tsai <wens@csie.org>, David Airlie <airlied@gmail.com>,
Daniel Vetter <daniel@ffwll.ch>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Samuel Holland <samuel@sholland.org>,
"open list:DRM DRIVERS FOR ALLWINNER A10"
<dri-devel@lists.freedesktop.org>,
"moderated list:ARM/Allwinner sunXi SoC support"
<linux-arm-kernel@lists.infradead.org>,
"open list:ARM/Allwinner sunXi SoC support"
<linux-sunxi@lists.linux.dev>,
open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 1/1] drm/sun4i: tcon: Fix setting PLL rate when using DSI
Date: Tue, 21 Mar 2023 15:57:39 +0100 [thread overview]
Message-ID: <20230321145739.jlpbzplsc27dlh7v@houat> (raw)
In-Reply-To: <20230319160704.9858-2-frank@oltmanns.dev>
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Hi,
On Sun, Mar 19, 2023 at 05:07:04PM +0100, Frank Oltmanns wrote:
> Set the required PLL rate by adjusting the dotclock rate when calling
> clk_set_rate() when using DSI.
>
> According to the Allwinners A64's BSP code, a TCON divider of 4 has to
> be used and the PLL rate needs to be set to the following frequency when
> using DSI:
> PLL rate = DCLK * bpp / lanes
>
> After this change the common mode set function would only contain
> setting the resolution. Therefore, dissolve the function and transfer
> the functionality to the individual mode set functions.
>
> Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
This is similar to:
https://lore.kernel.org/all/20230320161636.24411-1-romanberanek@icloud.com/
What's the story there?
Maxime
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next prev parent reply other threads:[~2023-03-21 14:57 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-19 16:07 [PATCH 0/1] Fixing the DSI dot clock on Allwinner Frank Oltmanns
2023-03-19 16:07 ` [PATCH 1/1] drm/sun4i: tcon: Fix setting PLL rate when using DSI Frank Oltmanns
2023-03-21 14:57 ` Maxime Ripard [this message]
2023-03-21 19:55 ` Frank Oltmanns
2023-03-22 3:25 ` Roman Beranek
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