From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
To: linux-clk@vger.kernel.org
Cc: linux-mips@vger.kernel.org, tsbogend@alpha.franken.de,
john@phrozen.org, linux-kernel@vger.kernel.org,
p.zabel@pengutronix.de, mturquette@baylibre.com,
sboyd@kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com,
devicetree@vger.kernel.org, arinc.unal@arinc9.com
Subject: [PATCH 01/10] dt: bindings: clock: add mtmips SoCs clock device tree binding documentation
Date: Mon, 20 Mar 2023 17:18:14 +0100 [thread overview]
Message-ID: <20230320161823.1424278-2-sergio.paracuellos@gmail.com> (raw)
In-Reply-To: <20230320161823.1424278-1-sergio.paracuellos@gmail.com>
Adds device tree binding documentation for clocks and resets in the
Mediatek MIPS and Ralink SOCs. This covers RT2880, RT3050, RT3052, RT3350,
RT3883, RT5350, MT7620, MT7628 and MT7688 SoCs.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
.../bindings/clock/mtmips-clock.yaml | 68 +++++++++++++++++++
1 file changed, 68 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/mtmips-clock.yaml
diff --git a/Documentation/devicetree/bindings/clock/mtmips-clock.yaml b/Documentation/devicetree/bindings/clock/mtmips-clock.yaml
new file mode 100644
index 000000000000..c92969ce231d
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/mtmips-clock.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/mtmips-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MTMIPS SoCs Clock
+
+maintainers:
+ - Sergio Paracuellos <sergio.paracuellos@gmail.com>
+
+description: |
+ MediaTek MIPS and Ralink SoCs have an XTAL from where the cpu clock is
+ provided as well as derived clocks for the bus and the peripherals.
+
+ Each clock is assigned an identifier and client nodes use this identifier
+ to specify the clock which they consume.
+
+ The clocks are provided inside a system controller node.
+
+ This node is also a reset provider for all the peripherals.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - ralink,rt2880-sysc
+ - ralink,rt3050-sysc
+ - ralink,rt3052-sysc
+ - ralink,rt3352-sysc
+ - ralink,rt3883-sysc
+ - ralink,rt5350-sysc
+ - ralink,mt7620-sysc
+ - ralink,mt7620a-sysc
+ - ralink,mt7628-sysc
+ - ralink,mt7688-sysc
+ - ralink,rt2880-reset
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ description:
+ The first cell indicates the clock number.
+ const: 1
+
+ '#reset-cells':
+ description:
+ The first cell indicates the reset bit within the register.
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ sysc: sysc@0 {
+ compatible = "ralink,rt5350-sysc", "syscon";
+ reg = <0x0 0x100>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
--
2.25.1
next prev parent reply other threads:[~2023-03-20 16:25 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-20 16:18 [PATCH 00/10] mips: ralink: add complete clock and reset driver for mtmips SoCs Sergio Paracuellos
2023-03-20 16:18 ` Sergio Paracuellos [this message]
2023-03-20 16:36 ` [PATCH 01/10] dt: bindings: clock: add mtmips SoCs clock device tree binding documentation Krzysztof Kozlowski
2023-03-20 16:43 ` Arınç ÜNAL
2023-03-20 16:50 ` Krzysztof Kozlowski
2023-03-20 17:24 ` Sergio Paracuellos
2023-03-20 17:36 ` Krzysztof Kozlowski
2023-03-20 17:57 ` Arınç ÜNAL
2023-03-20 18:02 ` Krzysztof Kozlowski
2023-03-20 18:09 ` Arınç ÜNAL
2023-03-20 18:15 ` Krzysztof Kozlowski
2023-03-21 4:34 ` Sergio Paracuellos
2023-03-21 6:32 ` Krzysztof Kozlowski
2023-03-21 6:38 ` Arınç ÜNAL
2023-03-21 6:43 ` Krzysztof Kozlowski
2023-03-21 6:56 ` Sergio Paracuellos
2023-03-21 7:19 ` Krzysztof Kozlowski
2023-03-21 7:27 ` Sergio Paracuellos
2023-03-21 7:39 ` Arınç ÜNAL
2023-03-21 8:04 ` Krzysztof Kozlowski
2023-03-21 8:24 ` Arınç ÜNAL
2023-03-21 8:27 ` Krzysztof Kozlowski
2023-03-21 8:33 ` Arınç ÜNAL
2023-03-21 8:39 ` Krzysztof Kozlowski
2023-03-21 8:53 ` Arınç ÜNAL
2023-03-21 9:01 ` Krzysztof Kozlowski
2023-03-21 9:02 ` Arınç ÜNAL
2023-03-24 22:10 ` Rob Herring
2023-03-24 23:15 ` Arınç ÜNAL
2023-03-24 22:13 ` Rob Herring
2023-03-21 4:29 ` Sergio Paracuellos
2023-03-20 18:01 ` Krzysztof Kozlowski
2023-03-20 18:07 ` Arınç ÜNAL
2023-03-20 18:11 ` Krzysztof Kozlowski
2023-03-20 18:23 ` Arınç ÜNAL
2023-03-21 6:34 ` Krzysztof Kozlowski
2023-03-20 16:18 ` [PATCH 02/10] clk: ralink: add clock and reset driver for MTMIPS SoCs Sergio Paracuellos
2023-03-20 16:18 ` [PATCH 03/10] mips: ralink: rt288x: remove clock related code Sergio Paracuellos
2023-03-20 16:18 ` [PATCH 04/10] mips: ralink: rt305x: " Sergio Paracuellos
2023-03-20 16:18 ` [PATCH 05/10] mips: ralink: rt3883: " Sergio Paracuellos
2023-03-20 16:18 ` [PATCH 06/10] mips: ralink: mt7620: " Sergio Paracuellos
2023-03-20 16:18 ` [PATCH 07/10] mips: ralink: remove clock related function prototypes Sergio Paracuellos
2023-03-20 19:38 ` Stephen Boyd
2023-03-20 20:17 ` Sergio Paracuellos
2023-03-20 21:21 ` Stephen Boyd
2023-03-21 4:23 ` Sergio Paracuellos
2023-03-20 16:18 ` [PATCH 08/10] mips: ralink: remove reset related code Sergio Paracuellos
2023-03-20 16:18 ` [PATCH 09/10] mips: ralink: get cpu rate from new driver code Sergio Paracuellos
2023-03-20 16:18 ` [PATCH 10/10] MAINTAINERS: add Mediatek MTMIPS Clock maintainer Sergio Paracuellos
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