* [PATCH net-next 1/3] net: ipa: add IPA v5.0 register definitions
2023-03-20 20:24 [PATCH net-next 0/3] net: ipa: fully support IPA v5.0 Alex Elder
@ 2023-03-20 20:24 ` Alex Elder
2023-03-21 12:41 ` Alex Elder
2023-03-20 20:24 ` [PATCH net-next 2/3] net: ipa: add IPA v5.0 GSI " Alex Elder
2023-03-20 20:24 ` [PATCH net-next 3/3] net: ipa: add IPA v5.0 configuration data Alex Elder
2 siblings, 1 reply; 5+ messages in thread
From: Alex Elder @ 2023-03-20 20:24 UTC (permalink / raw)
To: davem, edumazet, kuba, pabeni
Cc: caleb.connolly, mka, evgreen, andersson, quic_cpratapa,
quic_avuyyuru, quic_jponduru, quic_subashab, elder, netdev,
linux-arm-msm, linux-kernel
Add the definitions of IPA register offsets and fields for IPA v5.0.
These are used for the SDX65 SoC.
Signed-off-by: Alex Elder <elder@linaro.org>
---
drivers/net/ipa/Makefile | 2 +-
drivers/net/ipa/ipa_reg.c | 2 +
drivers/net/ipa/ipa_reg.h | 1 +
drivers/net/ipa/reg/ipa_reg-v5.0.c | 564 +++++++++++++++++++++++++++++
4 files changed, 568 insertions(+), 1 deletion(-)
create mode 100644 drivers/net/ipa/reg/ipa_reg-v5.0.c
diff --git a/drivers/net/ipa/Makefile b/drivers/net/ipa/Makefile
index cba199422f471..1458f9129e4b1 100644
--- a/drivers/net/ipa/Makefile
+++ b/drivers/net/ipa/Makefile
@@ -2,7 +2,7 @@
#
# Makefile for the Qualcomm IPA driver.
-IPA_VERSIONS := 3.1 3.5.1 4.2 4.5 4.7 4.9 4.11
+IPA_VERSIONS := 3.1 3.5.1 4.2 4.5 4.7 4.9 4.11 5.0
# Some IPA versions can reuse another set of GSI register definitions.
GSI_IPA_VERSIONS := 3.1 3.5.1 4.0 4.5 4.9 4.11
diff --git a/drivers/net/ipa/ipa_reg.c b/drivers/net/ipa/ipa_reg.c
index 3f475428ddddb..818a84f7c42d6 100644
--- a/drivers/net/ipa/ipa_reg.c
+++ b/drivers/net/ipa/ipa_reg.c
@@ -123,6 +123,8 @@ static const struct regs *ipa_regs(enum ipa_version version)
return &ipa_regs_v4_9;
case IPA_VERSION_4_11:
return &ipa_regs_v4_11;
+ case IPA_VERSION_5_0:
+ return &ipa_regs_v5_0;
default:
return NULL;
}
diff --git a/drivers/net/ipa/ipa_reg.h b/drivers/net/ipa/ipa_reg.h
index 7dd65d39333dd..3ac48dea865b2 100644
--- a/drivers/net/ipa/ipa_reg.h
+++ b/drivers/net/ipa/ipa_reg.h
@@ -636,6 +636,7 @@ extern const struct regs ipa_regs_v4_5;
extern const struct regs ipa_regs_v4_7;
extern const struct regs ipa_regs_v4_9;
extern const struct regs ipa_regs_v4_11;
+extern const struct regs ipa_regs_v5_0;
const struct reg *ipa_reg(struct ipa *ipa, enum ipa_reg_id reg_id);
diff --git a/drivers/net/ipa/reg/ipa_reg-v5.0.c b/drivers/net/ipa/reg/ipa_reg-v5.0.c
new file mode 100644
index 0000000000000..95e0edff41709
--- /dev/null
+++ b/drivers/net/ipa/reg/ipa_reg-v5.0.c
@@ -0,0 +1,564 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* Copyright (C) 2023 Linaro Ltd. */
+
+#include <linux/types.h>
+
+#include "../ipa.h"
+#include "../ipa_reg.h"
+
+static const u32 reg_flavor_0_fmask[] = {
+ [MAX_PIPES] = GENMASK(7, 0),
+ [MAX_CONS_PIPES] = GENMASK(15, 8),
+ [MAX_PROD_PIPES] = GENMASK(23, 16),
+ [PROD_LOWEST] = GENMASK(31, 24),
+};
+
+REG_FIELDS(FLAVOR_0, flavor_0, 0x00000000);
+
+static const u32 reg_comp_cfg_fmask[] = {
+ [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
+ [GSI_SNOC_BYPASS_DIS] = BIT(1),
+ [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
+ [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
+ /* Bit 4 reserved */
+ [IPA_QMB_SELECT_CONS_EN] = BIT(5),
+ [IPA_QMB_SELECT_PROD_EN] = BIT(6),
+ [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
+ [GSI_MULTI_INORDER_WR_DIS] = BIT(8),
+ [GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9),
+ [GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10),
+ [GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11),
+ [GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12),
+ [GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13),
+ [GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14),
+ [GSI_MULTI_AXI_MASTERS_DIS] = BIT(15),
+ [IPA_QMB_SELECT_GLOBAL_EN] = BIT(16),
+ [FULL_FLUSH_WAIT_RS_CLOSURE_EN] = BIT(17),
+ /* Bit 18 reserved */
+ [QMB_RAM_RD_CACHE_DISABLE] = BIT(19),
+ [GENQMB_AOOOWR] = BIT(20),
+ [IF_OUT_OF_BUF_STOP_RESET_MASK_EN] = BIT(21),
+ [ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(27, 22),
+ /* Bits 28-29 reserved */
+ [GEN_QMB_1_DYNAMIC_ASIZE] = BIT(30),
+ [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),
+};
+
+REG_FIELDS(COMP_CFG, comp_cfg, 0x0000002c);
+
+static const u32 reg_clkon_cfg_fmask[] = {
+ [CLKON_RX] = BIT(0),
+ [CLKON_PROC] = BIT(1),
+ [TX_WRAPPER] = BIT(2),
+ [CLKON_MISC] = BIT(3),
+ [RAM_ARB] = BIT(4),
+ [FTCH_HPS] = BIT(5),
+ [FTCH_DPS] = BIT(6),
+ [CLKON_HPS] = BIT(7),
+ [CLKON_DPS] = BIT(8),
+ [RX_HPS_CMDQS] = BIT(9),
+ [HPS_DPS_CMDQS] = BIT(10),
+ [DPS_TX_CMDQS] = BIT(11),
+ [RSRC_MNGR] = BIT(12),
+ [CTX_HANDLER] = BIT(13),
+ [ACK_MNGR] = BIT(14),
+ [D_DCPH] = BIT(15),
+ [H_DCPH] = BIT(16),
+ /* Bit 17 reserved */
+ [NTF_TX_CMDQS] = BIT(18),
+ [CLKON_TX_0] = BIT(19),
+ [CLKON_TX_1] = BIT(20),
+ [CLKON_FNR] = BIT(21),
+ [QSB2AXI_CMDQ_L] = BIT(22),
+ [AGGR_WRAPPER] = BIT(23),
+ [RAM_SLAVEWAY] = BIT(24),
+ [CLKON_QMB] = BIT(25),
+ [WEIGHT_ARB] = BIT(26),
+ [GSI_IF] = BIT(27),
+ [CLKON_GLOBAL] = BIT(28),
+ [GLOBAL_2X_CLK] = BIT(29),
+ [DPL_FIFO] = BIT(30),
+ [DRBIP] = BIT(31),
+};
+
+REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000034);
+
+static const u32 reg_route_fmask[] = {
+ [ROUTE_DEF_PIPE] = GENMASK(7, 0),
+ [ROUTE_FRAG_DEF_PIPE] = GENMASK(15, 8),
+ [ROUTE_DEF_HDR_OFST] = GENMASK(25, 16),
+ [ROUTE_DEF_HDR_TABLE] = BIT(26),
+ [ROUTE_DEF_RETAIN_HDR] = BIT(27),
+ [ROUTE_DIS] = BIT(28),
+ /* Bits 29-31 reserved */
+};
+
+REG_FIELDS(ROUTE, route, 0x00000038);
+
+static const u32 reg_shared_mem_size_fmask[] = {
+ [MEM_SIZE] = GENMASK(15, 0),
+ [MEM_BADDR] = GENMASK(31, 16),
+};
+
+REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000040);
+
+static const u32 reg_qsb_max_writes_fmask[] = {
+ [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
+ [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
+ /* Bits 8-31 reserved */
+};
+
+REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000054);
+
+static const u32 reg_qsb_max_reads_fmask[] = {
+ [GEN_QMB_0_MAX_READS] = GENMASK(3, 0),
+ [GEN_QMB_1_MAX_READS] = GENMASK(7, 4),
+ /* Bits 8-15 reserved */
+ [GEN_QMB_0_MAX_READS_BEATS] = GENMASK(23, 16),
+ [GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24),
+};
+
+REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000058);
+
+/* Valid bits defined by ipa->available */
+
+REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x00000100, 0x0004);
+
+static const u32 reg_filt_rout_cache_flush_fmask[] = {
+ [ROUTER_CACHE] = BIT(0),
+ /* Bits 1-3 reserved */
+ [FILTER_CACHE] = BIT(4),
+ /* Bits 5-31 reserved */
+};
+
+REG_FIELDS(FILT_ROUT_CACHE_FLUSH, filt_rout_cache_flush, 0x0000404);
+
+static const u32 reg_local_pkt_proc_cntxt_fmask[] = {
+ [IPA_BASE_ADDR] = GENMASK(17, 0),
+ /* Bits 18-31 reserved */
+};
+
+/* Offset must be a multiple of 8 */
+REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x00000478);
+
+static const u32 reg_ipa_tx_cfg_fmask[] = {
+ /* Bits 0-1 reserved */
+ [PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2),
+ [DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6),
+ [DMAW_SCND_OUTSD_PRED_EN] = BIT(10),
+ [DMAW_MAX_BEATS_256_DIS] = BIT(11),
+ [PA_MASK_EN] = BIT(12),
+ [PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13),
+ [DUAL_TX_ENABLE] = BIT(17),
+ [SSPND_PA_NO_START_STATE] = BIT(18),
+ /* Bit 19 reserved */
+ [HOLB_STICKY_DROP_EN] = BIT(20),
+ /* Bits 21-31 reserved */
+};
+
+REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x00000488);
+
+static const u32 reg_idle_indication_cfg_fmask[] = {
+ [ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0),
+ [CONST_NON_IDLE_ENABLE] = BIT(16),
+ /* Bits 17-31 reserved */
+};
+
+REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x000004a8);
+
+static const u32 reg_qtime_timestamp_cfg_fmask[] = {
+ [DPL_TIMESTAMP_LSB] = GENMASK(4, 0),
+ /* Bits 5-6 reserved */
+ [DPL_TIMESTAMP_SEL] = BIT(7),
+ [TAG_TIMESTAMP_LSB] = GENMASK(12, 8),
+ /* Bits 13-15 reserved */
+ [NAT_TIMESTAMP_LSB] = GENMASK(20, 16),
+ /* Bits 21-31 reserved */
+};
+
+REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x000004ac);
+
+static const u32 reg_timers_xo_clk_div_cfg_fmask[] = {
+ [DIV_VALUE] = GENMASK(8, 0),
+ /* Bits 9-30 reserved */
+ [DIV_ENABLE] = BIT(31),
+};
+
+REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x000004b0);
+
+static const u32 reg_timers_pulse_gran_cfg_fmask[] = {
+ [PULSE_GRAN_0] = GENMASK(2, 0),
+ [PULSE_GRAN_1] = GENMASK(5, 3),
+ [PULSE_GRAN_2] = GENMASK(8, 6),
+ [PULSE_GRAN_3] = GENMASK(11, 9),
+ /* Bits 12-31 reserved */
+};
+
+REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x000004b4);
+
+static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = {
+ [X_MIN_LIM] = GENMASK(5, 0),
+ /* Bits 6-7 reserved */
+ [X_MAX_LIM] = GENMASK(13, 8),
+ /* Bits 14-15 reserved */
+ [Y_MIN_LIM] = GENMASK(21, 16),
+ /* Bits 22-23 reserved */
+ [Y_MAX_LIM] = GENMASK(29, 24),
+ /* Bits 30-31 reserved */
+};
+
+REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,
+ 0x00000500, 0x0020);
+
+static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = {
+ [X_MIN_LIM] = GENMASK(5, 0),
+ /* Bits 6-7 reserved */
+ [X_MAX_LIM] = GENMASK(13, 8),
+ /* Bits 14-15 reserved */
+ [Y_MIN_LIM] = GENMASK(21, 16),
+ /* Bits 22-23 reserved */
+ [Y_MAX_LIM] = GENMASK(29, 24),
+ /* Bits 30-31 reserved */
+};
+
+REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type,
+ 0x00000504, 0x0020);
+
+static const u32 reg_src_rsrc_grp_45_rsrc_type_fmask[] = {
+ [X_MIN_LIM] = GENMASK(5, 0),
+ /* Bits 6-7 reserved */
+ [X_MAX_LIM] = GENMASK(13, 8),
+ /* Bits 14-15 reserved */
+ [Y_MIN_LIM] = GENMASK(21, 16),
+ /* Bits 22-23 reserved */
+ [Y_MAX_LIM] = GENMASK(29, 24),
+ /* Bits 30-31 reserved */
+};
+
+REG_STRIDE_FIELDS(SRC_RSRC_GRP_45_RSRC_TYPE, src_rsrc_grp_45_rsrc_type,
+ 0x00000508, 0x0020);
+
+static const u32 reg_src_rsrc_grp_67_rsrc_type_fmask[] = {
+ [X_MIN_LIM] = GENMASK(5, 0),
+ /* Bits 6-7 reserved */
+ [X_MAX_LIM] = GENMASK(13, 8),
+ /* Bits 14-15 reserved */
+ [Y_MIN_LIM] = GENMASK(21, 16),
+ /* Bits 22-23 reserved */
+ [Y_MAX_LIM] = GENMASK(29, 24),
+ /* Bits 30-31 reserved */
+};
+
+REG_STRIDE_FIELDS(SRC_RSRC_GRP_67_RSRC_TYPE, src_rsrc_grp_67_rsrc_type,
+ 0x0000050c, 0x0020);
+
+static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {
+ [X_MIN_LIM] = GENMASK(5, 0),
+ /* Bits 6-7 reserved */
+ [X_MAX_LIM] = GENMASK(13, 8),
+ /* Bits 14-15 reserved */
+ [Y_MIN_LIM] = GENMASK(21, 16),
+ /* Bits 22-23 reserved */
+ [Y_MAX_LIM] = GENMASK(29, 24),
+ /* Bits 30-31 reserved */
+};
+
+REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type,
+ 0x00000600, 0x0020);
+
+static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {
+ [X_MIN_LIM] = GENMASK(5, 0),
+ /* Bits 6-7 reserved */
+ [X_MAX_LIM] = GENMASK(13, 8),
+ /* Bits 14-15 reserved */
+ [Y_MIN_LIM] = GENMASK(21, 16),
+ /* Bits 22-23 reserved */
+ [Y_MAX_LIM] = GENMASK(29, 24),
+ /* Bits 30-31 reserved */
+};
+
+REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,
+ 0x00000604, 0x0020);
+
+static const u32 reg_dst_rsrc_grp_45_rsrc_type_fmask[] = {
+ [X_MIN_LIM] = GENMASK(5, 0),
+ /* Bits 6-7 reserved */
+ [X_MAX_LIM] = GENMASK(13, 8),
+ /* Bits 14-15 reserved */
+ [Y_MIN_LIM] = GENMASK(21, 16),
+ /* Bits 22-23 reserved */
+ [Y_MAX_LIM] = GENMASK(29, 24),
+ /* Bits 30-31 reserved */
+};
+
+REG_STRIDE_FIELDS(DST_RSRC_GRP_45_RSRC_TYPE, dst_rsrc_grp_45_rsrc_type,
+ 0x00000608, 0x0020);
+
+static const u32 reg_dst_rsrc_grp_67_rsrc_type_fmask[] = {
+ [X_MIN_LIM] = GENMASK(5, 0),
+ /* Bits 6-7 reserved */
+ [X_MAX_LIM] = GENMASK(13, 8),
+ /* Bits 14-15 reserved */
+ [Y_MIN_LIM] = GENMASK(21, 16),
+ /* Bits 22-23 reserved */
+ [Y_MAX_LIM] = GENMASK(29, 24),
+ /* Bits 30-31 reserved */
+};
+
+REG_STRIDE_FIELDS(DST_RSRC_GRP_67_RSRC_TYPE, dst_rsrc_grp_67_rsrc_type,
+ 0x0000060c, 0x0020);
+
+/* Valid bits defined by ipa->available */
+
+REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000006b0, 0x0004);
+
+static const u32 reg_endp_init_cfg_fmask[] = {
+ [FRAG_OFFLOAD_EN] = BIT(0),
+ [CS_OFFLOAD_EN] = GENMASK(2, 1),
+ [CS_METADATA_HDR_OFFSET] = GENMASK(6, 3),
+ /* Bit 7 reserved */
+ [CS_GEN_QMB_MASTER_SEL] = BIT(8),
+ /* Bits 9-31 reserved */
+};
+
+REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00001008, 0x0080);
+
+static const u32 reg_endp_init_nat_fmask[] = {
+ [NAT_EN] = GENMASK(1, 0),
+ /* Bits 2-31 reserved */
+};
+
+REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000100c, 0x0080);
+
+static const u32 reg_endp_init_hdr_fmask[] = {
+ [HDR_LEN] = GENMASK(5, 0),
+ [HDR_OFST_METADATA_VALID] = BIT(6),
+ [HDR_OFST_METADATA] = GENMASK(12, 7),
+ [HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13),
+ [HDR_OFST_PKT_SIZE_VALID] = BIT(19),
+ [HDR_OFST_PKT_SIZE] = GENMASK(25, 20),
+ /* Bit 26 reserved */
+ [HDR_LEN_INC_DEAGG_HDR] = BIT(27),
+ [HDR_LEN_MSB] = GENMASK(29, 28),
+ [HDR_OFST_METADATA_MSB] = GENMASK(31, 30),
+};
+
+REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00001010, 0x0080);
+
+static const u32 reg_endp_init_hdr_ext_fmask[] = {
+ [HDR_ENDIANNESS] = BIT(0),
+ [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1),
+ [HDR_TOTAL_LEN_OR_PAD] = BIT(2),
+ [HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3),
+ [HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4),
+ [HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10),
+ /* Bits 14-15 reserved */
+ [HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB] = GENMASK(17, 16),
+ [HDR_OFST_PKT_SIZE_MSB] = GENMASK(19, 18),
+ [HDR_ADDITIONAL_CONST_LEN_MSB] = GENMASK(21, 20),
+ [HDR_BYTES_TO_REMOVE_VALID] = BIT(22),
+ /* Bit 23 reserved */
+ [HDR_BYTES_TO_REMOVE] = GENMASK(31, 24),
+};
+
+REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00001014, 0x0080);
+
+REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,
+ 0x00001018, 0x0080);
+
+static const u32 reg_endp_init_mode_fmask[] = {
+ [ENDP_MODE] = GENMASK(2, 0),
+ [DCPH_ENABLE] = BIT(3),
+ [DEST_PIPE_INDEX] = GENMASK(11, 4),
+ [BYTE_THRESHOLD] = GENMASK(27, 12),
+ [PIPE_REPLICATION_EN] = BIT(28),
+ [PAD_EN] = BIT(29),
+ [DRBIP_ACL_ENABLE] = BIT(30),
+ /* Bit 31 reserved */
+};
+
+REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00001020, 0x0080);
+
+static const u32 reg_endp_init_aggr_fmask[] = {
+ [AGGR_EN] = GENMASK(1, 0),
+ [AGGR_TYPE] = GENMASK(4, 2),
+ [BYTE_LIMIT] = GENMASK(10, 5),
+ /* Bit 11 reserved */
+ [TIME_LIMIT] = GENMASK(16, 12),
+ [PKT_LIMIT] = GENMASK(22, 17),
+ [SW_EOF_ACTIVE] = BIT(23),
+ [FORCE_CLOSE] = BIT(24),
+ /* Bit 25 reserved */
+ [HARD_BYTE_LIMIT_EN] = BIT(26),
+ [AGGR_GRAN_SEL] = BIT(27),
+ /* Bits 28-31 reserved */
+};
+
+REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00001024, 0x0080);
+
+static const u32 reg_endp_init_hol_block_en_fmask[] = {
+ [HOL_BLOCK_EN] = BIT(0),
+ /* Bits 1-31 reserved */
+};
+
+REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en,
+ 0x0000102c, 0x0080);
+
+static const u32 reg_endp_init_hol_block_timer_fmask[] = {
+ [TIMER_LIMIT] = GENMASK(4, 0),
+ /* Bits 5-7 reserved */
+ [TIMER_GRAN_SEL] = GENMASK(9, 8),
+ /* Bits 10-31 reserved */
+};
+
+REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer,
+ 0x00001030, 0x0080);
+
+static const u32 reg_endp_init_deaggr_fmask[] = {
+ [DEAGGR_HDR_LEN] = GENMASK(5, 0),
+ [SYSPIPE_ERR_DETECTION] = BIT(6),
+ [PACKET_OFFSET_VALID] = BIT(7),
+ [PACKET_OFFSET_LOCATION] = GENMASK(13, 8),
+ [IGNORE_MIN_PKT_ERR] = BIT(14),
+ /* Bit 15 reserved */
+ [MAX_PACKET_LEN] = GENMASK(31, 16),
+};
+
+REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00001034, 0x0080);
+
+static const u32 reg_endp_init_rsrc_grp_fmask[] = {
+ [ENDP_RSRC_GRP] = GENMASK(2, 0),
+ /* Bits 3-31 reserved */
+};
+
+REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00001038, 0x0080);
+
+static const u32 reg_endp_init_seq_fmask[] = {
+ [SEQ_TYPE] = GENMASK(7, 0),
+ /* Bits 8-31 reserved */
+};
+
+REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000103c, 0x0080);
+
+static const u32 reg_endp_status_fmask[] = {
+ [STATUS_EN] = BIT(0),
+ [STATUS_ENDP] = GENMASK(8, 1),
+ [STATUS_PKT_SUPPRESS] = BIT(9),
+ /* Bits 10-31 reserved */
+};
+
+REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00001040, 0x0080);
+
+static const u32 reg_endp_filter_cache_cfg_fmask[] = {
+ [CACHE_MSK_SRC_ID] = BIT(0),
+ [CACHE_MSK_SRC_IP] = BIT(1),
+ [CACHE_MSK_DST_IP] = BIT(2),
+ [CACHE_MSK_SRC_PORT] = BIT(3),
+ [CACHE_MSK_DST_PORT] = BIT(4),
+ [CACHE_MSK_PROTOCOL] = BIT(5),
+ [CACHE_MSK_METADATA] = BIT(6),
+ /* Bits 7-31 reserved */
+};
+
+REG_STRIDE_FIELDS(ENDP_FILTER_CACHE_CFG, endp_filter_cache_cfg,
+ 0x0000105c, 0x0080);
+
+static const u32 reg_endp_router_cache_cfg_fmask[] = {
+ [CACHE_MSK_SRC_ID] = BIT(0),
+ [CACHE_MSK_SRC_IP] = BIT(1),
+ [CACHE_MSK_DST_IP] = BIT(2),
+ [CACHE_MSK_SRC_PORT] = BIT(3),
+ [CACHE_MSK_DST_PORT] = BIT(4),
+ [CACHE_MSK_PROTOCOL] = BIT(5),
+ [CACHE_MSK_METADATA] = BIT(6),
+ /* Bits 7-31 reserved */
+};
+
+REG_STRIDE_FIELDS(ENDP_ROUTER_CACHE_CFG, endp_router_cache_cfg,
+ 0x00001070, 0x0080);
+
+/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
+REG(IPA_IRQ_STTS, ipa_irq_stts, 0x0000c008 + 0x1000 * GSI_EE_AP);
+
+/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
+REG(IPA_IRQ_EN, ipa_irq_en, 0x0000c00c + 0x1000 * GSI_EE_AP);
+
+/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
+REG(IPA_IRQ_CLR, ipa_irq_clr, 0x0000c010 + 0x1000 * GSI_EE_AP);
+
+static const u32 reg_ipa_irq_uc_fmask[] = {
+ [UC_INTR] = BIT(0),
+ /* Bits 1-31 reserved */
+};
+
+REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000c01c + 0x1000 * GSI_EE_AP);
+
+/* Valid bits defined by ipa->available */
+
+REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info,
+ 0x0000c030 + 0x1000 * GSI_EE_AP, 0x0004);
+
+/* Valid bits defined by ipa->available */
+
+REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en,
+ 0x0000c050 + 0x1000 * GSI_EE_AP, 0x0004);
+
+/* Valid bits defined by ipa->available */
+
+REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr,
+ 0x0000c070 + 0x1000 * GSI_EE_AP, 0x0004);
+
+static const struct reg *reg_array[] = {
+ [COMP_CFG] = ®_comp_cfg,
+ [CLKON_CFG] = ®_clkon_cfg,
+ [ROUTE] = ®_route,
+ [SHARED_MEM_SIZE] = ®_shared_mem_size,
+ [QSB_MAX_WRITES] = ®_qsb_max_writes,
+ [QSB_MAX_READS] = ®_qsb_max_reads,
+ [FILT_ROUT_CACHE_FLUSH] = ®_filt_rout_cache_flush,
+ [STATE_AGGR_ACTIVE] = ®_state_aggr_active,
+ [LOCAL_PKT_PROC_CNTXT] = ®_local_pkt_proc_cntxt,
+ [AGGR_FORCE_CLOSE] = ®_aggr_force_close,
+ [IPA_TX_CFG] = ®_ipa_tx_cfg,
+ [FLAVOR_0] = ®_flavor_0,
+ [IDLE_INDICATION_CFG] = ®_idle_indication_cfg,
+ [QTIME_TIMESTAMP_CFG] = ®_qtime_timestamp_cfg,
+ [TIMERS_XO_CLK_DIV_CFG] = ®_timers_xo_clk_div_cfg,
+ [TIMERS_PULSE_GRAN_CFG] = ®_timers_pulse_gran_cfg,
+ [SRC_RSRC_GRP_01_RSRC_TYPE] = ®_src_rsrc_grp_01_rsrc_type,
+ [SRC_RSRC_GRP_23_RSRC_TYPE] = ®_src_rsrc_grp_23_rsrc_type,
+ [SRC_RSRC_GRP_45_RSRC_TYPE] = ®_src_rsrc_grp_45_rsrc_type,
+ [SRC_RSRC_GRP_67_RSRC_TYPE] = ®_src_rsrc_grp_67_rsrc_type,
+ [DST_RSRC_GRP_01_RSRC_TYPE] = ®_dst_rsrc_grp_01_rsrc_type,
+ [DST_RSRC_GRP_23_RSRC_TYPE] = ®_dst_rsrc_grp_23_rsrc_type,
+ [DST_RSRC_GRP_45_RSRC_TYPE] = ®_dst_rsrc_grp_45_rsrc_type,
+ [DST_RSRC_GRP_67_RSRC_TYPE] = ®_dst_rsrc_grp_67_rsrc_type,
+ [ENDP_INIT_CFG] = ®_endp_init_cfg,
+ [ENDP_INIT_NAT] = ®_endp_init_nat,
+ [ENDP_INIT_HDR] = ®_endp_init_hdr,
+ [ENDP_INIT_HDR_EXT] = ®_endp_init_hdr_ext,
+ [ENDP_INIT_HDR_METADATA_MASK] = ®_endp_init_hdr_metadata_mask,
+ [ENDP_INIT_MODE] = ®_endp_init_mode,
+ [ENDP_INIT_AGGR] = ®_endp_init_aggr,
+ [ENDP_INIT_HOL_BLOCK_EN] = ®_endp_init_hol_block_en,
+ [ENDP_INIT_HOL_BLOCK_TIMER] = ®_endp_init_hol_block_timer,
+ [ENDP_INIT_DEAGGR] = ®_endp_init_deaggr,
+ [ENDP_INIT_RSRC_GRP] = ®_endp_init_rsrc_grp,
+ [ENDP_INIT_SEQ] = ®_endp_init_seq,
+ [ENDP_STATUS] = ®_endp_status,
+ [ENDP_FILTER_CACHE_CFG] = ®_endp_filter_cache_cfg,
+ [ENDP_ROUTER_CACHE_CFG] = ®_endp_router_cache_cfg,
+ [IPA_IRQ_STTS] = ®_ipa_irq_stts,
+ [IPA_IRQ_EN] = ®_ipa_irq_en,
+ [IPA_IRQ_CLR] = ®_ipa_irq_clr,
+ [IPA_IRQ_UC] = ®_ipa_irq_uc,
+ [IRQ_SUSPEND_INFO] = ®_irq_suspend_info,
+ [IRQ_SUSPEND_EN] = ®_irq_suspend_en,
+ [IRQ_SUSPEND_CLR] = ®_irq_suspend_clr,
+};
+
+const struct regs ipa_regs_v5_0 = {
+ .reg_count = ARRAY_SIZE(reg_array),
+ .reg = reg_array,
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH net-next 1/3] net: ipa: add IPA v5.0 register definitions
2023-03-20 20:24 ` [PATCH net-next 1/3] net: ipa: add IPA v5.0 register definitions Alex Elder
@ 2023-03-21 12:41 ` Alex Elder
0 siblings, 0 replies; 5+ messages in thread
From: Alex Elder @ 2023-03-21 12:41 UTC (permalink / raw)
To: davem, edumazet, kuba, pabeni
Cc: caleb.connolly, mka, evgreen, andersson, quic_cpratapa,
quic_avuyyuru, quic_jponduru, quic_subashab, elder, netdev,
linux-arm-msm, linux-kernel
On 3/20/23 3:24 PM, Alex Elder wrote:
> Add the definitions of IPA register offsets and fields for IPA v5.0.
> These are used for the SDX65 SoC.
>
> Signed-off-by: Alex Elder <elder@linaro.org>
This causes build errors, because the Makefile states
that "ipa_data-v5.0.o" is needed even though it has
not yet been defined in this series. I didn't catch
it because I didn't clean my tree before test-building
the patches in the series.
I will re-send, and will move the hunk in the Makefile
that adds "5.0" to the IPA_VERSIONS variable into the
last patch in the series, when all needed source files
will be present.
-Alex
> ---
> drivers/net/ipa/Makefile | 2 +-
> drivers/net/ipa/ipa_reg.c | 2 +
> drivers/net/ipa/ipa_reg.h | 1 +
> drivers/net/ipa/reg/ipa_reg-v5.0.c | 564 +++++++++++++++++++++++++++++
> 4 files changed, 568 insertions(+), 1 deletion(-)
> create mode 100644 drivers/net/ipa/reg/ipa_reg-v5.0.c
>
> diff --git a/drivers/net/ipa/Makefile b/drivers/net/ipa/Makefile
> index cba199422f471..1458f9129e4b1 100644
> --- a/drivers/net/ipa/Makefile
> +++ b/drivers/net/ipa/Makefile
> @@ -2,7 +2,7 @@
> #
> # Makefile for the Qualcomm IPA driver.
>
> -IPA_VERSIONS := 3.1 3.5.1 4.2 4.5 4.7 4.9 4.11
> +IPA_VERSIONS := 3.1 3.5.1 4.2 4.5 4.7 4.9 4.11 5.0
>
> # Some IPA versions can reuse another set of GSI register definitions.
> GSI_IPA_VERSIONS := 3.1 3.5.1 4.0 4.5 4.9 4.11
> diff --git a/drivers/net/ipa/ipa_reg.c b/drivers/net/ipa/ipa_reg.c
> index 3f475428ddddb..818a84f7c42d6 100644
> --- a/drivers/net/ipa/ipa_reg.c
> +++ b/drivers/net/ipa/ipa_reg.c
> @@ -123,6 +123,8 @@ static const struct regs *ipa_regs(enum ipa_version version)
> return &ipa_regs_v4_9;
> case IPA_VERSION_4_11:
> return &ipa_regs_v4_11;
> + case IPA_VERSION_5_0:
> + return &ipa_regs_v5_0;
> default:
> return NULL;
> }
> diff --git a/drivers/net/ipa/ipa_reg.h b/drivers/net/ipa/ipa_reg.h
> index 7dd65d39333dd..3ac48dea865b2 100644
> --- a/drivers/net/ipa/ipa_reg.h
> +++ b/drivers/net/ipa/ipa_reg.h
> @@ -636,6 +636,7 @@ extern const struct regs ipa_regs_v4_5;
> extern const struct regs ipa_regs_v4_7;
> extern const struct regs ipa_regs_v4_9;
> extern const struct regs ipa_regs_v4_11;
> +extern const struct regs ipa_regs_v5_0;
>
> const struct reg *ipa_reg(struct ipa *ipa, enum ipa_reg_id reg_id);
>
> diff --git a/drivers/net/ipa/reg/ipa_reg-v5.0.c b/drivers/net/ipa/reg/ipa_reg-v5.0.c
> new file mode 100644
> index 0000000000000..95e0edff41709
> --- /dev/null
> +++ b/drivers/net/ipa/reg/ipa_reg-v5.0.c
> @@ -0,0 +1,564 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +/* Copyright (C) 2023 Linaro Ltd. */
> +
> +#include <linux/types.h>
> +
> +#include "../ipa.h"
> +#include "../ipa_reg.h"
> +
> +static const u32 reg_flavor_0_fmask[] = {
> + [MAX_PIPES] = GENMASK(7, 0),
> + [MAX_CONS_PIPES] = GENMASK(15, 8),
> + [MAX_PROD_PIPES] = GENMASK(23, 16),
> + [PROD_LOWEST] = GENMASK(31, 24),
> +};
> +
> +REG_FIELDS(FLAVOR_0, flavor_0, 0x00000000);
> +
> +static const u32 reg_comp_cfg_fmask[] = {
> + [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
> + [GSI_SNOC_BYPASS_DIS] = BIT(1),
> + [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
> + [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
> + /* Bit 4 reserved */
> + [IPA_QMB_SELECT_CONS_EN] = BIT(5),
> + [IPA_QMB_SELECT_PROD_EN] = BIT(6),
> + [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
> + [GSI_MULTI_INORDER_WR_DIS] = BIT(8),
> + [GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9),
> + [GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10),
> + [GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11),
> + [GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12),
> + [GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13),
> + [GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14),
> + [GSI_MULTI_AXI_MASTERS_DIS] = BIT(15),
> + [IPA_QMB_SELECT_GLOBAL_EN] = BIT(16),
> + [FULL_FLUSH_WAIT_RS_CLOSURE_EN] = BIT(17),
> + /* Bit 18 reserved */
> + [QMB_RAM_RD_CACHE_DISABLE] = BIT(19),
> + [GENQMB_AOOOWR] = BIT(20),
> + [IF_OUT_OF_BUF_STOP_RESET_MASK_EN] = BIT(21),
> + [ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(27, 22),
> + /* Bits 28-29 reserved */
> + [GEN_QMB_1_DYNAMIC_ASIZE] = BIT(30),
> + [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),
> +};
> +
> +REG_FIELDS(COMP_CFG, comp_cfg, 0x0000002c);
> +
> +static const u32 reg_clkon_cfg_fmask[] = {
> + [CLKON_RX] = BIT(0),
> + [CLKON_PROC] = BIT(1),
> + [TX_WRAPPER] = BIT(2),
> + [CLKON_MISC] = BIT(3),
> + [RAM_ARB] = BIT(4),
> + [FTCH_HPS] = BIT(5),
> + [FTCH_DPS] = BIT(6),
> + [CLKON_HPS] = BIT(7),
> + [CLKON_DPS] = BIT(8),
> + [RX_HPS_CMDQS] = BIT(9),
> + [HPS_DPS_CMDQS] = BIT(10),
> + [DPS_TX_CMDQS] = BIT(11),
> + [RSRC_MNGR] = BIT(12),
> + [CTX_HANDLER] = BIT(13),
> + [ACK_MNGR] = BIT(14),
> + [D_DCPH] = BIT(15),
> + [H_DCPH] = BIT(16),
> + /* Bit 17 reserved */
> + [NTF_TX_CMDQS] = BIT(18),
> + [CLKON_TX_0] = BIT(19),
> + [CLKON_TX_1] = BIT(20),
> + [CLKON_FNR] = BIT(21),
> + [QSB2AXI_CMDQ_L] = BIT(22),
> + [AGGR_WRAPPER] = BIT(23),
> + [RAM_SLAVEWAY] = BIT(24),
> + [CLKON_QMB] = BIT(25),
> + [WEIGHT_ARB] = BIT(26),
> + [GSI_IF] = BIT(27),
> + [CLKON_GLOBAL] = BIT(28),
> + [GLOBAL_2X_CLK] = BIT(29),
> + [DPL_FIFO] = BIT(30),
> + [DRBIP] = BIT(31),
> +};
> +
> +REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000034);
> +
> +static const u32 reg_route_fmask[] = {
> + [ROUTE_DEF_PIPE] = GENMASK(7, 0),
> + [ROUTE_FRAG_DEF_PIPE] = GENMASK(15, 8),
> + [ROUTE_DEF_HDR_OFST] = GENMASK(25, 16),
> + [ROUTE_DEF_HDR_TABLE] = BIT(26),
> + [ROUTE_DEF_RETAIN_HDR] = BIT(27),
> + [ROUTE_DIS] = BIT(28),
> + /* Bits 29-31 reserved */
> +};
> +
> +REG_FIELDS(ROUTE, route, 0x00000038);
> +
> +static const u32 reg_shared_mem_size_fmask[] = {
> + [MEM_SIZE] = GENMASK(15, 0),
> + [MEM_BADDR] = GENMASK(31, 16),
> +};
> +
> +REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000040);
> +
> +static const u32 reg_qsb_max_writes_fmask[] = {
> + [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
> + [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
> + /* Bits 8-31 reserved */
> +};
> +
> +REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000054);
> +
> +static const u32 reg_qsb_max_reads_fmask[] = {
> + [GEN_QMB_0_MAX_READS] = GENMASK(3, 0),
> + [GEN_QMB_1_MAX_READS] = GENMASK(7, 4),
> + /* Bits 8-15 reserved */
> + [GEN_QMB_0_MAX_READS_BEATS] = GENMASK(23, 16),
> + [GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24),
> +};
> +
> +REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000058);
> +
> +/* Valid bits defined by ipa->available */
> +
> +REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x00000100, 0x0004);
> +
> +static const u32 reg_filt_rout_cache_flush_fmask[] = {
> + [ROUTER_CACHE] = BIT(0),
> + /* Bits 1-3 reserved */
> + [FILTER_CACHE] = BIT(4),
> + /* Bits 5-31 reserved */
> +};
> +
> +REG_FIELDS(FILT_ROUT_CACHE_FLUSH, filt_rout_cache_flush, 0x0000404);
> +
> +static const u32 reg_local_pkt_proc_cntxt_fmask[] = {
> + [IPA_BASE_ADDR] = GENMASK(17, 0),
> + /* Bits 18-31 reserved */
> +};
> +
> +/* Offset must be a multiple of 8 */
> +REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x00000478);
> +
> +static const u32 reg_ipa_tx_cfg_fmask[] = {
> + /* Bits 0-1 reserved */
> + [PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2),
> + [DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6),
> + [DMAW_SCND_OUTSD_PRED_EN] = BIT(10),
> + [DMAW_MAX_BEATS_256_DIS] = BIT(11),
> + [PA_MASK_EN] = BIT(12),
> + [PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13),
> + [DUAL_TX_ENABLE] = BIT(17),
> + [SSPND_PA_NO_START_STATE] = BIT(18),
> + /* Bit 19 reserved */
> + [HOLB_STICKY_DROP_EN] = BIT(20),
> + /* Bits 21-31 reserved */
> +};
> +
> +REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x00000488);
> +
> +static const u32 reg_idle_indication_cfg_fmask[] = {
> + [ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0),
> + [CONST_NON_IDLE_ENABLE] = BIT(16),
> + /* Bits 17-31 reserved */
> +};
> +
> +REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x000004a8);
> +
> +static const u32 reg_qtime_timestamp_cfg_fmask[] = {
> + [DPL_TIMESTAMP_LSB] = GENMASK(4, 0),
> + /* Bits 5-6 reserved */
> + [DPL_TIMESTAMP_SEL] = BIT(7),
> + [TAG_TIMESTAMP_LSB] = GENMASK(12, 8),
> + /* Bits 13-15 reserved */
> + [NAT_TIMESTAMP_LSB] = GENMASK(20, 16),
> + /* Bits 21-31 reserved */
> +};
> +
> +REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x000004ac);
> +
> +static const u32 reg_timers_xo_clk_div_cfg_fmask[] = {
> + [DIV_VALUE] = GENMASK(8, 0),
> + /* Bits 9-30 reserved */
> + [DIV_ENABLE] = BIT(31),
> +};
> +
> +REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x000004b0);
> +
> +static const u32 reg_timers_pulse_gran_cfg_fmask[] = {
> + [PULSE_GRAN_0] = GENMASK(2, 0),
> + [PULSE_GRAN_1] = GENMASK(5, 3),
> + [PULSE_GRAN_2] = GENMASK(8, 6),
> + [PULSE_GRAN_3] = GENMASK(11, 9),
> + /* Bits 12-31 reserved */
> +};
> +
> +REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x000004b4);
> +
> +static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = {
> + [X_MIN_LIM] = GENMASK(5, 0),
> + /* Bits 6-7 reserved */
> + [X_MAX_LIM] = GENMASK(13, 8),
> + /* Bits 14-15 reserved */
> + [Y_MIN_LIM] = GENMASK(21, 16),
> + /* Bits 22-23 reserved */
> + [Y_MAX_LIM] = GENMASK(29, 24),
> + /* Bits 30-31 reserved */
> +};
> +
> +REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,
> + 0x00000500, 0x0020);
> +
> +static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = {
> + [X_MIN_LIM] = GENMASK(5, 0),
> + /* Bits 6-7 reserved */
> + [X_MAX_LIM] = GENMASK(13, 8),
> + /* Bits 14-15 reserved */
> + [Y_MIN_LIM] = GENMASK(21, 16),
> + /* Bits 22-23 reserved */
> + [Y_MAX_LIM] = GENMASK(29, 24),
> + /* Bits 30-31 reserved */
> +};
> +
> +REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type,
> + 0x00000504, 0x0020);
> +
> +static const u32 reg_src_rsrc_grp_45_rsrc_type_fmask[] = {
> + [X_MIN_LIM] = GENMASK(5, 0),
> + /* Bits 6-7 reserved */
> + [X_MAX_LIM] = GENMASK(13, 8),
> + /* Bits 14-15 reserved */
> + [Y_MIN_LIM] = GENMASK(21, 16),
> + /* Bits 22-23 reserved */
> + [Y_MAX_LIM] = GENMASK(29, 24),
> + /* Bits 30-31 reserved */
> +};
> +
> +REG_STRIDE_FIELDS(SRC_RSRC_GRP_45_RSRC_TYPE, src_rsrc_grp_45_rsrc_type,
> + 0x00000508, 0x0020);
> +
> +static const u32 reg_src_rsrc_grp_67_rsrc_type_fmask[] = {
> + [X_MIN_LIM] = GENMASK(5, 0),
> + /* Bits 6-7 reserved */
> + [X_MAX_LIM] = GENMASK(13, 8),
> + /* Bits 14-15 reserved */
> + [Y_MIN_LIM] = GENMASK(21, 16),
> + /* Bits 22-23 reserved */
> + [Y_MAX_LIM] = GENMASK(29, 24),
> + /* Bits 30-31 reserved */
> +};
> +
> +REG_STRIDE_FIELDS(SRC_RSRC_GRP_67_RSRC_TYPE, src_rsrc_grp_67_rsrc_type,
> + 0x0000050c, 0x0020);
> +
> +static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {
> + [X_MIN_LIM] = GENMASK(5, 0),
> + /* Bits 6-7 reserved */
> + [X_MAX_LIM] = GENMASK(13, 8),
> + /* Bits 14-15 reserved */
> + [Y_MIN_LIM] = GENMASK(21, 16),
> + /* Bits 22-23 reserved */
> + [Y_MAX_LIM] = GENMASK(29, 24),
> + /* Bits 30-31 reserved */
> +};
> +
> +REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type,
> + 0x00000600, 0x0020);
> +
> +static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {
> + [X_MIN_LIM] = GENMASK(5, 0),
> + /* Bits 6-7 reserved */
> + [X_MAX_LIM] = GENMASK(13, 8),
> + /* Bits 14-15 reserved */
> + [Y_MIN_LIM] = GENMASK(21, 16),
> + /* Bits 22-23 reserved */
> + [Y_MAX_LIM] = GENMASK(29, 24),
> + /* Bits 30-31 reserved */
> +};
> +
> +REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,
> + 0x00000604, 0x0020);
> +
> +static const u32 reg_dst_rsrc_grp_45_rsrc_type_fmask[] = {
> + [X_MIN_LIM] = GENMASK(5, 0),
> + /* Bits 6-7 reserved */
> + [X_MAX_LIM] = GENMASK(13, 8),
> + /* Bits 14-15 reserved */
> + [Y_MIN_LIM] = GENMASK(21, 16),
> + /* Bits 22-23 reserved */
> + [Y_MAX_LIM] = GENMASK(29, 24),
> + /* Bits 30-31 reserved */
> +};
> +
> +REG_STRIDE_FIELDS(DST_RSRC_GRP_45_RSRC_TYPE, dst_rsrc_grp_45_rsrc_type,
> + 0x00000608, 0x0020);
> +
> +static const u32 reg_dst_rsrc_grp_67_rsrc_type_fmask[] = {
> + [X_MIN_LIM] = GENMASK(5, 0),
> + /* Bits 6-7 reserved */
> + [X_MAX_LIM] = GENMASK(13, 8),
> + /* Bits 14-15 reserved */
> + [Y_MIN_LIM] = GENMASK(21, 16),
> + /* Bits 22-23 reserved */
> + [Y_MAX_LIM] = GENMASK(29, 24),
> + /* Bits 30-31 reserved */
> +};
> +
> +REG_STRIDE_FIELDS(DST_RSRC_GRP_67_RSRC_TYPE, dst_rsrc_grp_67_rsrc_type,
> + 0x0000060c, 0x0020);
> +
> +/* Valid bits defined by ipa->available */
> +
> +REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000006b0, 0x0004);
> +
> +static const u32 reg_endp_init_cfg_fmask[] = {
> + [FRAG_OFFLOAD_EN] = BIT(0),
> + [CS_OFFLOAD_EN] = GENMASK(2, 1),
> + [CS_METADATA_HDR_OFFSET] = GENMASK(6, 3),
> + /* Bit 7 reserved */
> + [CS_GEN_QMB_MASTER_SEL] = BIT(8),
> + /* Bits 9-31 reserved */
> +};
> +
> +REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00001008, 0x0080);
> +
> +static const u32 reg_endp_init_nat_fmask[] = {
> + [NAT_EN] = GENMASK(1, 0),
> + /* Bits 2-31 reserved */
> +};
> +
> +REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000100c, 0x0080);
> +
> +static const u32 reg_endp_init_hdr_fmask[] = {
> + [HDR_LEN] = GENMASK(5, 0),
> + [HDR_OFST_METADATA_VALID] = BIT(6),
> + [HDR_OFST_METADATA] = GENMASK(12, 7),
> + [HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13),
> + [HDR_OFST_PKT_SIZE_VALID] = BIT(19),
> + [HDR_OFST_PKT_SIZE] = GENMASK(25, 20),
> + /* Bit 26 reserved */
> + [HDR_LEN_INC_DEAGG_HDR] = BIT(27),
> + [HDR_LEN_MSB] = GENMASK(29, 28),
> + [HDR_OFST_METADATA_MSB] = GENMASK(31, 30),
> +};
> +
> +REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00001010, 0x0080);
> +
> +static const u32 reg_endp_init_hdr_ext_fmask[] = {
> + [HDR_ENDIANNESS] = BIT(0),
> + [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1),
> + [HDR_TOTAL_LEN_OR_PAD] = BIT(2),
> + [HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3),
> + [HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4),
> + [HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10),
> + /* Bits 14-15 reserved */
> + [HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB] = GENMASK(17, 16),
> + [HDR_OFST_PKT_SIZE_MSB] = GENMASK(19, 18),
> + [HDR_ADDITIONAL_CONST_LEN_MSB] = GENMASK(21, 20),
> + [HDR_BYTES_TO_REMOVE_VALID] = BIT(22),
> + /* Bit 23 reserved */
> + [HDR_BYTES_TO_REMOVE] = GENMASK(31, 24),
> +};
> +
> +REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00001014, 0x0080);
> +
> +REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,
> + 0x00001018, 0x0080);
> +
> +static const u32 reg_endp_init_mode_fmask[] = {
> + [ENDP_MODE] = GENMASK(2, 0),
> + [DCPH_ENABLE] = BIT(3),
> + [DEST_PIPE_INDEX] = GENMASK(11, 4),
> + [BYTE_THRESHOLD] = GENMASK(27, 12),
> + [PIPE_REPLICATION_EN] = BIT(28),
> + [PAD_EN] = BIT(29),
> + [DRBIP_ACL_ENABLE] = BIT(30),
> + /* Bit 31 reserved */
> +};
> +
> +REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00001020, 0x0080);
> +
> +static const u32 reg_endp_init_aggr_fmask[] = {
> + [AGGR_EN] = GENMASK(1, 0),
> + [AGGR_TYPE] = GENMASK(4, 2),
> + [BYTE_LIMIT] = GENMASK(10, 5),
> + /* Bit 11 reserved */
> + [TIME_LIMIT] = GENMASK(16, 12),
> + [PKT_LIMIT] = GENMASK(22, 17),
> + [SW_EOF_ACTIVE] = BIT(23),
> + [FORCE_CLOSE] = BIT(24),
> + /* Bit 25 reserved */
> + [HARD_BYTE_LIMIT_EN] = BIT(26),
> + [AGGR_GRAN_SEL] = BIT(27),
> + /* Bits 28-31 reserved */
> +};
> +
> +REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00001024, 0x0080);
> +
> +static const u32 reg_endp_init_hol_block_en_fmask[] = {
> + [HOL_BLOCK_EN] = BIT(0),
> + /* Bits 1-31 reserved */
> +};
> +
> +REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en,
> + 0x0000102c, 0x0080);
> +
> +static const u32 reg_endp_init_hol_block_timer_fmask[] = {
> + [TIMER_LIMIT] = GENMASK(4, 0),
> + /* Bits 5-7 reserved */
> + [TIMER_GRAN_SEL] = GENMASK(9, 8),
> + /* Bits 10-31 reserved */
> +};
> +
> +REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer,
> + 0x00001030, 0x0080);
> +
> +static const u32 reg_endp_init_deaggr_fmask[] = {
> + [DEAGGR_HDR_LEN] = GENMASK(5, 0),
> + [SYSPIPE_ERR_DETECTION] = BIT(6),
> + [PACKET_OFFSET_VALID] = BIT(7),
> + [PACKET_OFFSET_LOCATION] = GENMASK(13, 8),
> + [IGNORE_MIN_PKT_ERR] = BIT(14),
> + /* Bit 15 reserved */
> + [MAX_PACKET_LEN] = GENMASK(31, 16),
> +};
> +
> +REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00001034, 0x0080);
> +
> +static const u32 reg_endp_init_rsrc_grp_fmask[] = {
> + [ENDP_RSRC_GRP] = GENMASK(2, 0),
> + /* Bits 3-31 reserved */
> +};
> +
> +REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00001038, 0x0080);
> +
> +static const u32 reg_endp_init_seq_fmask[] = {
> + [SEQ_TYPE] = GENMASK(7, 0),
> + /* Bits 8-31 reserved */
> +};
> +
> +REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000103c, 0x0080);
> +
> +static const u32 reg_endp_status_fmask[] = {
> + [STATUS_EN] = BIT(0),
> + [STATUS_ENDP] = GENMASK(8, 1),
> + [STATUS_PKT_SUPPRESS] = BIT(9),
> + /* Bits 10-31 reserved */
> +};
> +
> +REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00001040, 0x0080);
> +
> +static const u32 reg_endp_filter_cache_cfg_fmask[] = {
> + [CACHE_MSK_SRC_ID] = BIT(0),
> + [CACHE_MSK_SRC_IP] = BIT(1),
> + [CACHE_MSK_DST_IP] = BIT(2),
> + [CACHE_MSK_SRC_PORT] = BIT(3),
> + [CACHE_MSK_DST_PORT] = BIT(4),
> + [CACHE_MSK_PROTOCOL] = BIT(5),
> + [CACHE_MSK_METADATA] = BIT(6),
> + /* Bits 7-31 reserved */
> +};
> +
> +REG_STRIDE_FIELDS(ENDP_FILTER_CACHE_CFG, endp_filter_cache_cfg,
> + 0x0000105c, 0x0080);
> +
> +static const u32 reg_endp_router_cache_cfg_fmask[] = {
> + [CACHE_MSK_SRC_ID] = BIT(0),
> + [CACHE_MSK_SRC_IP] = BIT(1),
> + [CACHE_MSK_DST_IP] = BIT(2),
> + [CACHE_MSK_SRC_PORT] = BIT(3),
> + [CACHE_MSK_DST_PORT] = BIT(4),
> + [CACHE_MSK_PROTOCOL] = BIT(5),
> + [CACHE_MSK_METADATA] = BIT(6),
> + /* Bits 7-31 reserved */
> +};
> +
> +REG_STRIDE_FIELDS(ENDP_ROUTER_CACHE_CFG, endp_router_cache_cfg,
> + 0x00001070, 0x0080);
> +
> +/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
> +REG(IPA_IRQ_STTS, ipa_irq_stts, 0x0000c008 + 0x1000 * GSI_EE_AP);
> +
> +/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
> +REG(IPA_IRQ_EN, ipa_irq_en, 0x0000c00c + 0x1000 * GSI_EE_AP);
> +
> +/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
> +REG(IPA_IRQ_CLR, ipa_irq_clr, 0x0000c010 + 0x1000 * GSI_EE_AP);
> +
> +static const u32 reg_ipa_irq_uc_fmask[] = {
> + [UC_INTR] = BIT(0),
> + /* Bits 1-31 reserved */
> +};
> +
> +REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000c01c + 0x1000 * GSI_EE_AP);
> +
> +/* Valid bits defined by ipa->available */
> +
> +REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info,
> + 0x0000c030 + 0x1000 * GSI_EE_AP, 0x0004);
> +
> +/* Valid bits defined by ipa->available */
> +
> +REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en,
> + 0x0000c050 + 0x1000 * GSI_EE_AP, 0x0004);
> +
> +/* Valid bits defined by ipa->available */
> +
> +REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr,
> + 0x0000c070 + 0x1000 * GSI_EE_AP, 0x0004);
> +
> +static const struct reg *reg_array[] = {
> + [COMP_CFG] = ®_comp_cfg,
> + [CLKON_CFG] = ®_clkon_cfg,
> + [ROUTE] = ®_route,
> + [SHARED_MEM_SIZE] = ®_shared_mem_size,
> + [QSB_MAX_WRITES] = ®_qsb_max_writes,
> + [QSB_MAX_READS] = ®_qsb_max_reads,
> + [FILT_ROUT_CACHE_FLUSH] = ®_filt_rout_cache_flush,
> + [STATE_AGGR_ACTIVE] = ®_state_aggr_active,
> + [LOCAL_PKT_PROC_CNTXT] = ®_local_pkt_proc_cntxt,
> + [AGGR_FORCE_CLOSE] = ®_aggr_force_close,
> + [IPA_TX_CFG] = ®_ipa_tx_cfg,
> + [FLAVOR_0] = ®_flavor_0,
> + [IDLE_INDICATION_CFG] = ®_idle_indication_cfg,
> + [QTIME_TIMESTAMP_CFG] = ®_qtime_timestamp_cfg,
> + [TIMERS_XO_CLK_DIV_CFG] = ®_timers_xo_clk_div_cfg,
> + [TIMERS_PULSE_GRAN_CFG] = ®_timers_pulse_gran_cfg,
> + [SRC_RSRC_GRP_01_RSRC_TYPE] = ®_src_rsrc_grp_01_rsrc_type,
> + [SRC_RSRC_GRP_23_RSRC_TYPE] = ®_src_rsrc_grp_23_rsrc_type,
> + [SRC_RSRC_GRP_45_RSRC_TYPE] = ®_src_rsrc_grp_45_rsrc_type,
> + [SRC_RSRC_GRP_67_RSRC_TYPE] = ®_src_rsrc_grp_67_rsrc_type,
> + [DST_RSRC_GRP_01_RSRC_TYPE] = ®_dst_rsrc_grp_01_rsrc_type,
> + [DST_RSRC_GRP_23_RSRC_TYPE] = ®_dst_rsrc_grp_23_rsrc_type,
> + [DST_RSRC_GRP_45_RSRC_TYPE] = ®_dst_rsrc_grp_45_rsrc_type,
> + [DST_RSRC_GRP_67_RSRC_TYPE] = ®_dst_rsrc_grp_67_rsrc_type,
> + [ENDP_INIT_CFG] = ®_endp_init_cfg,
> + [ENDP_INIT_NAT] = ®_endp_init_nat,
> + [ENDP_INIT_HDR] = ®_endp_init_hdr,
> + [ENDP_INIT_HDR_EXT] = ®_endp_init_hdr_ext,
> + [ENDP_INIT_HDR_METADATA_MASK] = ®_endp_init_hdr_metadata_mask,
> + [ENDP_INIT_MODE] = ®_endp_init_mode,
> + [ENDP_INIT_AGGR] = ®_endp_init_aggr,
> + [ENDP_INIT_HOL_BLOCK_EN] = ®_endp_init_hol_block_en,
> + [ENDP_INIT_HOL_BLOCK_TIMER] = ®_endp_init_hol_block_timer,
> + [ENDP_INIT_DEAGGR] = ®_endp_init_deaggr,
> + [ENDP_INIT_RSRC_GRP] = ®_endp_init_rsrc_grp,
> + [ENDP_INIT_SEQ] = ®_endp_init_seq,
> + [ENDP_STATUS] = ®_endp_status,
> + [ENDP_FILTER_CACHE_CFG] = ®_endp_filter_cache_cfg,
> + [ENDP_ROUTER_CACHE_CFG] = ®_endp_router_cache_cfg,
> + [IPA_IRQ_STTS] = ®_ipa_irq_stts,
> + [IPA_IRQ_EN] = ®_ipa_irq_en,
> + [IPA_IRQ_CLR] = ®_ipa_irq_clr,
> + [IPA_IRQ_UC] = ®_ipa_irq_uc,
> + [IRQ_SUSPEND_INFO] = ®_irq_suspend_info,
> + [IRQ_SUSPEND_EN] = ®_irq_suspend_en,
> + [IRQ_SUSPEND_CLR] = ®_irq_suspend_clr,
> +};
> +
> +const struct regs ipa_regs_v5_0 = {
> + .reg_count = ARRAY_SIZE(reg_array),
> + .reg = reg_array,
> +};
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH net-next 2/3] net: ipa: add IPA v5.0 GSI register definitions
2023-03-20 20:24 [PATCH net-next 0/3] net: ipa: fully support IPA v5.0 Alex Elder
2023-03-20 20:24 ` [PATCH net-next 1/3] net: ipa: add IPA v5.0 register definitions Alex Elder
@ 2023-03-20 20:24 ` Alex Elder
2023-03-20 20:24 ` [PATCH net-next 3/3] net: ipa: add IPA v5.0 configuration data Alex Elder
2 siblings, 0 replies; 5+ messages in thread
From: Alex Elder @ 2023-03-20 20:24 UTC (permalink / raw)
To: davem, edumazet, kuba, pabeni
Cc: caleb.connolly, mka, evgreen, andersson, quic_cpratapa,
quic_avuyyuru, quic_jponduru, quic_subashab, elder, netdev,
linux-arm-msm, linux-kernel
Add the definitions of GSI register offsets and fields for IPA v5.0.
These are used for the SDX65 SoC. Increase the maximum channel and
event ring counts supported by the driver, so those implemented by
the SDX65 are supported.
Signed-off-by: Alex Elder <elder@linaro.org>
---
drivers/net/ipa/Makefile | 2 +-
drivers/net/ipa/gsi.h | 4 +-
drivers/net/ipa/gsi_reg.c | 3 +
drivers/net/ipa/gsi_reg.h | 1 +
drivers/net/ipa/reg/gsi_reg-v5.0.c | 317 +++++++++++++++++++++++++++++
5 files changed, 324 insertions(+), 3 deletions(-)
create mode 100644 drivers/net/ipa/reg/gsi_reg-v5.0.c
diff --git a/drivers/net/ipa/Makefile b/drivers/net/ipa/Makefile
index 1458f9129e4b1..a878096ed1252 100644
--- a/drivers/net/ipa/Makefile
+++ b/drivers/net/ipa/Makefile
@@ -5,7 +5,7 @@
IPA_VERSIONS := 3.1 3.5.1 4.2 4.5 4.7 4.9 4.11 5.0
# Some IPA versions can reuse another set of GSI register definitions.
-GSI_IPA_VERSIONS := 3.1 3.5.1 4.0 4.5 4.9 4.11
+GSI_IPA_VERSIONS := 3.1 3.5.1 4.0 4.5 4.9 4.11 5.0
obj-$(CONFIG_QCOM_IPA) += ipa.o
diff --git a/drivers/net/ipa/gsi.h b/drivers/net/ipa/gsi.h
index 50bc80cb167c3..42063b227c185 100644
--- a/drivers/net/ipa/gsi.h
+++ b/drivers/net/ipa/gsi.h
@@ -16,8 +16,8 @@
#include "ipa_version.h"
/* Maximum number of channels and event rings supported by the driver */
-#define GSI_CHANNEL_COUNT_MAX 23
-#define GSI_EVT_RING_COUNT_MAX 24
+#define GSI_CHANNEL_COUNT_MAX 28
+#define GSI_EVT_RING_COUNT_MAX 28
/* Maximum TLV FIFO size for a channel; 64 here is arbitrary (and high) */
#define GSI_TLV_MAX 64
diff --git a/drivers/net/ipa/gsi_reg.c b/drivers/net/ipa/gsi_reg.c
index 1651fbad4bd54..c5458e28b12f2 100644
--- a/drivers/net/ipa/gsi_reg.c
+++ b/drivers/net/ipa/gsi_reg.c
@@ -109,6 +109,9 @@ static const struct regs *gsi_regs(struct gsi *gsi)
case IPA_VERSION_4_11:
return &gsi_regs_v4_11;
+ case IPA_VERSION_5_0:
+ return &gsi_regs_v5_0;
+
default:
return NULL;
}
diff --git a/drivers/net/ipa/gsi_reg.h b/drivers/net/ipa/gsi_reg.h
index 48fde65fa2e8a..cf046567f3fe6 100644
--- a/drivers/net/ipa/gsi_reg.h
+++ b/drivers/net/ipa/gsi_reg.h
@@ -355,6 +355,7 @@ extern const struct regs gsi_regs_v4_0;
extern const struct regs gsi_regs_v4_5;
extern const struct regs gsi_regs_v4_9;
extern const struct regs gsi_regs_v4_11;
+extern const struct regs gsi_regs_v5_0;
/**
* gsi_reg() - Return the structure describing a GSI register
diff --git a/drivers/net/ipa/reg/gsi_reg-v5.0.c b/drivers/net/ipa/reg/gsi_reg-v5.0.c
new file mode 100644
index 0000000000000..d7b81a36d673b
--- /dev/null
+++ b/drivers/net/ipa/reg/gsi_reg-v5.0.c
@@ -0,0 +1,317 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* Copyright (C) 2023 Linaro Ltd. */
+
+#include <linux/types.h>
+
+#include "../gsi.h"
+#include "../reg.h"
+#include "../gsi_reg.h"
+
+REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
+ 0x0000c01c + 0x1000 * GSI_EE_AP);
+
+REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
+ 0x0000c028 + 0x1000 * GSI_EE_AP);
+
+static const u32 reg_ch_c_cntxt_0_fmask[] = {
+ [CHTYPE_PROTOCOL] = GENMASK(6, 0),
+ [CHTYPE_DIR] = BIT(7),
+ [CH_EE] = GENMASK(11, 8),
+ [CHID] = GENMASK(19, 12),
+ [CHSTATE] = GENMASK(23, 20),
+ [ELEMENT_SIZE] = GENMASK(31, 24),
+};
+
+REG_STRIDE_FIELDS(CH_C_CNTXT_0, ch_c_cntxt_0,
+ 0x00014000 + 0x12000 * GSI_EE_AP, 0x80);
+
+static const u32 reg_ch_c_cntxt_1_fmask[] = {
+ [CH_R_LENGTH] = GENMASK(23, 0),
+ [ERINDEX] = GENMASK(31, 24),
+};
+
+REG_STRIDE_FIELDS(CH_C_CNTXT_1, ch_c_cntxt_1,
+ 0x00014004 + 0x12000 * GSI_EE_AP, 0x80);
+
+REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x00014008 + 0x12000 * GSI_EE_AP, 0x80);
+
+REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0001400c + 0x12000 * GSI_EE_AP, 0x80);
+
+static const u32 reg_ch_c_qos_fmask[] = {
+ [WRR_WEIGHT] = GENMASK(3, 0),
+ /* Bits 4-7 reserved */
+ [MAX_PREFETCH] = BIT(8),
+ [USE_DB_ENG] = BIT(9),
+ [PREFETCH_MODE] = GENMASK(13, 10),
+ /* Bits 14-15 reserved */
+ [EMPTY_LVL_THRSHOLD] = GENMASK(23, 16),
+ [DB_IN_BYTES] = BIT(24),
+ [LOW_LATENCY_EN] = BIT(25),
+ /* Bits 26-31 reserved */
+};
+
+REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x00014048 + 0x12000 * GSI_EE_AP, 0x80);
+
+REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0,
+ 0x0001404c + 0x12000 * GSI_EE_AP, 0x80);
+
+REG_STRIDE(CH_C_SCRATCH_1, ch_c_scratch_1,
+ 0x00014050 + 0x12000 * GSI_EE_AP, 0x80);
+
+REG_STRIDE(CH_C_SCRATCH_2, ch_c_scratch_2,
+ 0x00014054 + 0x12000 * GSI_EE_AP, 0x80);
+
+REG_STRIDE(CH_C_SCRATCH_3, ch_c_scratch_3,
+ 0x00014058 + 0x12000 * GSI_EE_AP, 0x80);
+
+static const u32 reg_ev_ch_e_cntxt_0_fmask[] = {
+ [EV_CHTYPE] = GENMASK(6, 0),
+ [EV_INTYPE] = BIT(7),
+ [EV_EVCHID] = GENMASK(15, 8),
+ [EV_EE] = GENMASK(19, 16),
+ [EV_CHSTATE] = GENMASK(23, 20),
+ [EV_ELEMENT_SIZE] = GENMASK(31, 24),
+};
+
+REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0,
+ 0x0001c000 + 0x12000 * GSI_EE_AP, 0x80);
+
+static const u32 reg_ev_ch_e_cntxt_1_fmask[] = {
+ [R_LENGTH] = GENMASK(19, 0),
+};
+
+REG_STRIDE_FIELDS(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1,
+ 0x0001c004 + 0x12000 * GSI_EE_AP, 0x80);
+
+REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2,
+ 0x0001c008 + 0x12000 * GSI_EE_AP, 0x80);
+
+REG_STRIDE(EV_CH_E_CNTXT_3, ev_ch_e_cntxt_3,
+ 0x0001c00c + 0x12000 * GSI_EE_AP, 0x80);
+
+REG_STRIDE(EV_CH_E_CNTXT_4, ev_ch_e_cntxt_4,
+ 0x0001c010 + 0x12000 * GSI_EE_AP, 0x80);
+
+static const u32 reg_ev_ch_e_cntxt_8_fmask[] = {
+ [EV_MODT] = GENMASK(15, 0),
+ [EV_MODC] = GENMASK(23, 16),
+ [EV_MOD_CNT] = GENMASK(31, 24),
+};
+
+REG_STRIDE_FIELDS(EV_CH_E_CNTXT_8, ev_ch_e_cntxt_8,
+ 0x0001c020 + 0x12000 * GSI_EE_AP, 0x80);
+
+REG_STRIDE(EV_CH_E_CNTXT_9, ev_ch_e_cntxt_9,
+ 0x0001c024 + 0x12000 * GSI_EE_AP, 0x80);
+
+REG_STRIDE(EV_CH_E_CNTXT_10, ev_ch_e_cntxt_10,
+ 0x0001c028 + 0x12000 * GSI_EE_AP, 0x80);
+
+REG_STRIDE(EV_CH_E_CNTXT_11, ev_ch_e_cntxt_11,
+ 0x0001c02c + 0x12000 * GSI_EE_AP, 0x80);
+
+REG_STRIDE(EV_CH_E_CNTXT_12, ev_ch_e_cntxt_12,
+ 0x0001c030 + 0x12000 * GSI_EE_AP, 0x80);
+
+REG_STRIDE(EV_CH_E_CNTXT_13, ev_ch_e_cntxt_13,
+ 0x0001c034 + 0x12000 * GSI_EE_AP, 0x80);
+
+REG_STRIDE(EV_CH_E_SCRATCH_0, ev_ch_e_scratch_0,
+ 0x0001c048 + 0x12000 * GSI_EE_AP, 0x80);
+
+REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1,
+ 0x0001c04c + 0x12000 * GSI_EE_AP, 0x80);
+
+REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0,
+ 0x00024000 + 0x12000 * GSI_EE_AP, 0x08);
+
+REG_STRIDE(EV_CH_E_DOORBELL_0, ev_ch_e_doorbell_0,
+ 0x00024800 + 0x12000 * GSI_EE_AP, 0x08);
+
+static const u32 reg_gsi_status_fmask[] = {
+ [ENABLED] = BIT(0),
+ /* Bits 1-31 reserved */
+};
+
+REG_FIELDS(GSI_STATUS, gsi_status, 0x00025000 + 0x12000 * GSI_EE_AP);
+
+static const u32 reg_ch_cmd_fmask[] = {
+ [CH_CHID] = GENMASK(7, 0),
+ /* Bits 8-23 reserved */
+ [CH_OPCODE] = GENMASK(31, 24),
+};
+
+REG_FIELDS(CH_CMD, ch_cmd, 0x00025008 + 0x12000 * GSI_EE_AP);
+
+static const u32 reg_ev_ch_cmd_fmask[] = {
+ [EV_CHID] = GENMASK(7, 0),
+ /* Bits 8-23 reserved */
+ [EV_OPCODE] = GENMASK(31, 24),
+};
+
+REG_FIELDS(EV_CH_CMD, ev_ch_cmd, 0x00025010 + 0x12000 * GSI_EE_AP);
+
+static const u32 reg_generic_cmd_fmask[] = {
+ [GENERIC_OPCODE] = GENMASK(4, 0),
+ [GENERIC_CHID] = GENMASK(9, 5),
+ [GENERIC_EE] = GENMASK(13, 10),
+ /* Bits 14-31 reserved */
+};
+
+REG_FIELDS(GENERIC_CMD, generic_cmd, 0x00025018 + 0x12000 * GSI_EE_AP);
+
+static const u32 reg_hw_param_2_fmask[] = {
+ [NUM_CH_PER_EE] = GENMASK(7, 0),
+ [IRAM_SIZE] = GENMASK(12, 8),
+ [GSI_CH_PEND_TRANSLATE] = BIT(13),
+ [GSI_CH_FULL_LOGIC] = BIT(14),
+ [GSI_USE_SDMA] = BIT(15),
+ [GSI_SDMA_N_INT] = GENMASK(18, 16),
+ [GSI_SDMA_MAX_BURST] = GENMASK(26, 19),
+ [GSI_SDMA_N_IOVEC] = GENMASK(29, 27),
+ [GSI_USE_RD_WR_ENG] = BIT(30),
+ [GSI_USE_INTER_EE] = BIT(31),
+};
+
+REG_FIELDS(HW_PARAM_2, hw_param_2, 0x00025040 + 0x12000 * GSI_EE_AP);
+
+static const u32 reg_hw_param_4_fmask[] = {
+ [EV_PER_EE] = GENMASK(7, 0),
+ [IRAM_PROTOCOL_COUNT] = GENMASK(15, 8),
+ /* Bits 16-31 reserved */
+};
+
+REG_FIELDS(HW_PARAM_4, hw_param_4, 0x00025050 + 0x12000 * GSI_EE_AP);
+
+REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x00025080 + 0x12000 * GSI_EE_AP);
+
+REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x00025088 + 0x12000 * GSI_EE_AP);
+
+REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x00025090 + 0x12000 * GSI_EE_AP);
+
+REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
+ 0x00025094 + 0x12000 * GSI_EE_AP);
+
+REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
+ 0x00025098 + 0x12000 * GSI_EE_AP);
+
+REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x0002509c + 0x12000 * GSI_EE_AP);
+
+REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
+ 0x000250a0 + 0x12000 * GSI_EE_AP);
+
+REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
+ 0x000250a4 + 0x12000 * GSI_EE_AP);
+
+REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x000250a8 + 0x12000 * GSI_EE_AP);
+
+REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk,
+ 0x000250ac + 0x12000 * GSI_EE_AP);
+
+REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr,
+ 0x000250b0 + 0x12000 * GSI_EE_AP);
+
+REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x00025200 + 0x12000 * GSI_EE_AP);
+
+REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x00025204 + 0x12000 * GSI_EE_AP);
+
+REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x00025208 + 0x12000 * GSI_EE_AP);
+
+REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x0002520c + 0x12000 * GSI_EE_AP);
+
+REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x00025210 + 0x12000 * GSI_EE_AP);
+
+REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x00025214 + 0x12000 * GSI_EE_AP);
+
+static const u32 reg_cntxt_intset_fmask[] = {
+ [INTYPE] = BIT(0)
+ /* Bits 1-31 reserved */
+};
+
+REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x00025220 + 0x12000 * GSI_EE_AP);
+
+static const u32 reg_error_log_fmask[] = {
+ [ERR_ARG3] = GENMASK(3, 0),
+ [ERR_ARG2] = GENMASK(7, 4),
+ [ERR_ARG1] = GENMASK(11, 8),
+ [ERR_CODE] = GENMASK(15, 12),
+ /* Bits 16-18 reserved */
+ [ERR_VIRT_IDX] = GENMASK(23, 19),
+ [ERR_TYPE] = GENMASK(27, 24),
+ [ERR_EE] = GENMASK(31, 28),
+};
+
+REG_FIELDS(ERROR_LOG, error_log, 0x00025240 + 0x12000 * GSI_EE_AP);
+
+REG(ERROR_LOG_CLR, error_log_clr, 0x00025244 + 0x12000 * GSI_EE_AP);
+
+static const u32 reg_cntxt_scratch_0_fmask[] = {
+ [INTER_EE_RESULT] = GENMASK(2, 0),
+ /* Bits 3-4 reserved */
+ [GENERIC_EE_RESULT] = GENMASK(7, 5),
+ /* Bits 8-31 reserved */
+};
+
+REG_FIELDS(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x00025400 + 0x12000 * GSI_EE_AP);
+
+static const struct reg *reg_array[] = {
+ [INTER_EE_SRC_CH_IRQ_MSK] = ®_inter_ee_src_ch_irq_msk,
+ [INTER_EE_SRC_EV_CH_IRQ_MSK] = ®_inter_ee_src_ev_ch_irq_msk,
+ [CH_C_CNTXT_0] = ®_ch_c_cntxt_0,
+ [CH_C_CNTXT_1] = ®_ch_c_cntxt_1,
+ [CH_C_CNTXT_2] = ®_ch_c_cntxt_2,
+ [CH_C_CNTXT_3] = ®_ch_c_cntxt_3,
+ [CH_C_QOS] = ®_ch_c_qos,
+ [CH_C_SCRATCH_0] = ®_ch_c_scratch_0,
+ [CH_C_SCRATCH_1] = ®_ch_c_scratch_1,
+ [CH_C_SCRATCH_2] = ®_ch_c_scratch_2,
+ [CH_C_SCRATCH_3] = ®_ch_c_scratch_3,
+ [EV_CH_E_CNTXT_0] = ®_ev_ch_e_cntxt_0,
+ [EV_CH_E_CNTXT_1] = ®_ev_ch_e_cntxt_1,
+ [EV_CH_E_CNTXT_2] = ®_ev_ch_e_cntxt_2,
+ [EV_CH_E_CNTXT_3] = ®_ev_ch_e_cntxt_3,
+ [EV_CH_E_CNTXT_4] = ®_ev_ch_e_cntxt_4,
+ [EV_CH_E_CNTXT_8] = ®_ev_ch_e_cntxt_8,
+ [EV_CH_E_CNTXT_9] = ®_ev_ch_e_cntxt_9,
+ [EV_CH_E_CNTXT_10] = ®_ev_ch_e_cntxt_10,
+ [EV_CH_E_CNTXT_11] = ®_ev_ch_e_cntxt_11,
+ [EV_CH_E_CNTXT_12] = ®_ev_ch_e_cntxt_12,
+ [EV_CH_E_CNTXT_13] = ®_ev_ch_e_cntxt_13,
+ [EV_CH_E_SCRATCH_0] = ®_ev_ch_e_scratch_0,
+ [EV_CH_E_SCRATCH_1] = ®_ev_ch_e_scratch_1,
+ [CH_C_DOORBELL_0] = ®_ch_c_doorbell_0,
+ [EV_CH_E_DOORBELL_0] = ®_ev_ch_e_doorbell_0,
+ [GSI_STATUS] = ®_gsi_status,
+ [CH_CMD] = ®_ch_cmd,
+ [EV_CH_CMD] = ®_ev_ch_cmd,
+ [GENERIC_CMD] = ®_generic_cmd,
+ [HW_PARAM_2] = ®_hw_param_2,
+ [HW_PARAM_4] = ®_hw_param_4,
+ [CNTXT_TYPE_IRQ] = ®_cntxt_type_irq,
+ [CNTXT_TYPE_IRQ_MSK] = ®_cntxt_type_irq_msk,
+ [CNTXT_SRC_CH_IRQ] = ®_cntxt_src_ch_irq,
+ [CNTXT_SRC_CH_IRQ_MSK] = ®_cntxt_src_ch_irq_msk,
+ [CNTXT_SRC_CH_IRQ_CLR] = ®_cntxt_src_ch_irq_clr,
+ [CNTXT_SRC_EV_CH_IRQ] = ®_cntxt_src_ev_ch_irq,
+ [CNTXT_SRC_EV_CH_IRQ_MSK] = ®_cntxt_src_ev_ch_irq_msk,
+ [CNTXT_SRC_EV_CH_IRQ_CLR] = ®_cntxt_src_ev_ch_irq_clr,
+ [CNTXT_SRC_IEOB_IRQ] = ®_cntxt_src_ieob_irq,
+ [CNTXT_SRC_IEOB_IRQ_MSK] = ®_cntxt_src_ieob_irq_msk,
+ [CNTXT_SRC_IEOB_IRQ_CLR] = ®_cntxt_src_ieob_irq_clr,
+ [CNTXT_GLOB_IRQ_STTS] = ®_cntxt_glob_irq_stts,
+ [CNTXT_GLOB_IRQ_EN] = ®_cntxt_glob_irq_en,
+ [CNTXT_GLOB_IRQ_CLR] = ®_cntxt_glob_irq_clr,
+ [CNTXT_GSI_IRQ_STTS] = ®_cntxt_gsi_irq_stts,
+ [CNTXT_GSI_IRQ_EN] = ®_cntxt_gsi_irq_en,
+ [CNTXT_GSI_IRQ_CLR] = ®_cntxt_gsi_irq_clr,
+ [CNTXT_INTSET] = ®_cntxt_intset,
+ [ERROR_LOG] = ®_error_log,
+ [ERROR_LOG_CLR] = ®_error_log_clr,
+ [CNTXT_SCRATCH_0] = ®_cntxt_scratch_0,
+};
+
+const struct regs gsi_regs_v5_0 = {
+ .reg_count = ARRAY_SIZE(reg_array),
+ .reg = reg_array,
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH net-next 3/3] net: ipa: add IPA v5.0 configuration data
2023-03-20 20:24 [PATCH net-next 0/3] net: ipa: fully support IPA v5.0 Alex Elder
2023-03-20 20:24 ` [PATCH net-next 1/3] net: ipa: add IPA v5.0 register definitions Alex Elder
2023-03-20 20:24 ` [PATCH net-next 2/3] net: ipa: add IPA v5.0 GSI " Alex Elder
@ 2023-03-20 20:24 ` Alex Elder
2 siblings, 0 replies; 5+ messages in thread
From: Alex Elder @ 2023-03-20 20:24 UTC (permalink / raw)
To: davem, edumazet, kuba, pabeni
Cc: caleb.connolly, mka, evgreen, andersson, quic_cpratapa,
quic_avuyyuru, quic_jponduru, quic_subashab, elder, netdev,
linux-arm-msm, linux-kernel
Add the configuration data required for IPA v5.0, which is used in
the SDX65 SoC.
Signed-off-by: Alex Elder <elder@linaro.org>
---
drivers/net/ipa/data/ipa_data-v5.0.c | 481 +++++++++++++++++++++++++++
drivers/net/ipa/ipa_data.h | 3 +-
drivers/net/ipa/ipa_main.c | 6 +-
3 files changed, 488 insertions(+), 2 deletions(-)
create mode 100644 drivers/net/ipa/data/ipa_data-v5.0.c
diff --git a/drivers/net/ipa/data/ipa_data-v5.0.c b/drivers/net/ipa/data/ipa_data-v5.0.c
new file mode 100644
index 0000000000000..4d8171dae4cd7
--- /dev/null
+++ b/drivers/net/ipa/data/ipa_data-v5.0.c
@@ -0,0 +1,481 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* Copyright (C) 2023 Linaro Ltd. */
+
+#include <linux/log2.h>
+
+#include "../gsi.h"
+#include "../ipa_data.h"
+#include "../ipa_endpoint.h"
+#include "../ipa_mem.h"
+
+/** enum ipa_resource_type - IPA resource types for an SoC having IPA v5.0 */
+enum ipa_resource_type {
+ /* Source resource types; first must have value 0 */
+ IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0,
+ IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS,
+ IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF,
+ IPA_RESOURCE_TYPE_SRC_HPS_DMARS,
+ IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES,
+
+ /* Destination resource types; first must have value 0 */
+ IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0,
+ IPA_RESOURCE_TYPE_DST_DPS_DMARS,
+ IPA_RESOURCE_TYPE_DST_ULSO_SEGMENTS,
+};
+
+/* Resource groups used for an SoC having IPA v5.0 */
+enum ipa_rsrc_group_id {
+ /* Source resource group identifiers */
+ IPA_RSRC_GROUP_SRC_UL = 0,
+ IPA_RSRC_GROUP_SRC_DL,
+ IPA_RSRC_GROUP_SRC_UNUSED_2,
+ IPA_RSRC_GROUP_SRC_UNUSED_3,
+ IPA_RSRC_GROUP_SRC_URLLC,
+ IPA_RSRC_GROUP_SRC_U_RX_QC,
+ IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */
+
+ /* Destination resource group identifiers */
+ IPA_RSRC_GROUP_DST_UL = 0,
+ IPA_RSRC_GROUP_DST_DL,
+ IPA_RSRC_GROUP_DST_DMA,
+ IPA_RSRC_GROUP_DST_QDSS,
+ IPA_RSRC_GROUP_DST_CV2X,
+ IPA_RSRC_GROUP_DST_UC,
+ IPA_RSRC_GROUP_DST_DRB_IP,
+ IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */
+};
+
+/* QSB configuration data for an SoC having IPA v5.0 */
+static const struct ipa_qsb_data ipa_qsb_data[] = {
+ [IPA_QSB_MASTER_DDR] = {
+ .max_writes = 0,
+ .max_reads = 0, /* no limit (hardware max) */
+ .max_reads_beats = 0,
+ },
+ [IPA_QSB_MASTER_PCIE] = {
+ .max_writes = 0,
+ .max_reads = 0, /* no limit (hardware max) */
+ .max_reads_beats = 0,
+ },
+};
+
+/* Endpoint configuration data for an SoC having IPA v5.0 */
+static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
+ [IPA_ENDPOINT_AP_COMMAND_TX] = {
+ .ee_id = GSI_EE_AP,
+ .channel_id = 12,
+ .endpoint_id = 14,
+ .toward_ipa = true,
+ .channel = {
+ .tre_count = 256,
+ .event_count = 256,
+ .tlv_count = 20,
+ },
+ .endpoint = {
+ .config = {
+ .resource_group = IPA_RSRC_GROUP_SRC_UL,
+ .dma_mode = true,
+ .dma_endpoint = IPA_ENDPOINT_AP_LAN_RX,
+ .tx = {
+ .seq_type = IPA_SEQ_DMA,
+ },
+ },
+ },
+ },
+ [IPA_ENDPOINT_AP_LAN_RX] = {
+ .ee_id = GSI_EE_AP,
+ .channel_id = 13,
+ .endpoint_id = 16,
+ .toward_ipa = false,
+ .channel = {
+ .tre_count = 256,
+ .event_count = 256,
+ .tlv_count = 9,
+ },
+ .endpoint = {
+ .config = {
+ .resource_group = IPA_RSRC_GROUP_DST_UL,
+ .aggregation = true,
+ .status_enable = true,
+ .rx = {
+ .buffer_size = 8192,
+ .pad_align = ilog2(sizeof(u32)),
+ .aggr_time_limit = 500,
+ },
+ },
+ },
+ },
+ [IPA_ENDPOINT_AP_MODEM_TX] = {
+ .ee_id = GSI_EE_AP,
+ .channel_id = 11,
+ .endpoint_id = 2,
+ .toward_ipa = true,
+ .channel = {
+ .tre_count = 512,
+ .event_count = 512,
+ .tlv_count = 25,
+ },
+ .endpoint = {
+ .filter_support = true,
+ .config = {
+ .resource_group = IPA_RSRC_GROUP_SRC_UL,
+ .checksum = true,
+ .qmap = true,
+ .status_enable = true,
+ .tx = {
+ .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC,
+ .status_endpoint =
+ IPA_ENDPOINT_MODEM_AP_RX,
+ },
+ },
+ },
+ },
+ [IPA_ENDPOINT_AP_MODEM_RX] = {
+ .ee_id = GSI_EE_AP,
+ .channel_id = 1,
+ .endpoint_id = 23,
+ .toward_ipa = false,
+ .channel = {
+ .tre_count = 256,
+ .event_count = 256,
+ .tlv_count = 9,
+ },
+ .endpoint = {
+ .config = {
+ .resource_group = IPA_RSRC_GROUP_DST_DL,
+ .checksum = true,
+ .qmap = true,
+ .aggregation = true,
+ .rx = {
+ .buffer_size = 8192,
+ .aggr_time_limit = 500,
+ .aggr_close_eof = true,
+ },
+ },
+ },
+ },
+ [IPA_ENDPOINT_MODEM_AP_TX] = {
+ .ee_id = GSI_EE_MODEM,
+ .channel_id = 0,
+ .endpoint_id = 12,
+ .toward_ipa = true,
+ .endpoint = {
+ .filter_support = true,
+ },
+ },
+ [IPA_ENDPOINT_MODEM_AP_RX] = {
+ .ee_id = GSI_EE_MODEM,
+ .channel_id = 7,
+ .endpoint_id = 21,
+ .toward_ipa = false,
+ },
+ [IPA_ENDPOINT_MODEM_DL_NLO_TX] = {
+ .ee_id = GSI_EE_MODEM,
+ .channel_id = 2,
+ .endpoint_id = 15,
+ .toward_ipa = true,
+ .endpoint = {
+ .filter_support = true,
+ },
+ },
+};
+
+/* Source resource configuration data for an SoC having IPA v5.0 */
+static const struct ipa_resource ipa_resource_src[] = {
+ [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = {
+ .limits[IPA_RSRC_GROUP_SRC_UL] = {
+ .min = 3, .max = 9,
+ },
+ .limits[IPA_RSRC_GROUP_SRC_DL] = {
+ .min = 4, .max = 10,
+ },
+ .limits[IPA_RSRC_GROUP_SRC_URLLC] = {
+ .min = 1, .max = 63,
+ },
+ .limits[IPA_RSRC_GROUP_SRC_U_RX_QC] = {
+ .min = 0, .max = 63,
+ },
+ },
+ [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = {
+ .limits[IPA_RSRC_GROUP_SRC_UL] = {
+ .min = 9, .max = 9,
+ },
+ .limits[IPA_RSRC_GROUP_SRC_DL] = {
+ .min = 12, .max = 12,
+ },
+ .limits[IPA_RSRC_GROUP_SRC_URLLC] = {
+ .min = 10, .max = 10,
+ },
+ },
+ [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = {
+ .limits[IPA_RSRC_GROUP_SRC_UL] = {
+ .min = 9, .max = 9,
+ },
+ .limits[IPA_RSRC_GROUP_SRC_DL] = {
+ .min = 24, .max = 24,
+ },
+ .limits[IPA_RSRC_GROUP_SRC_URLLC] = {
+ .min = 20, .max = 20,
+ },
+ },
+ [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = {
+ .limits[IPA_RSRC_GROUP_SRC_UL] = {
+ .min = 0, .max = 63,
+ },
+ .limits[IPA_RSRC_GROUP_SRC_DL] = {
+ .min = 0, .max = 63,
+ },
+ .limits[IPA_RSRC_GROUP_SRC_URLLC] = {
+ .min = 1, .max = 63,
+ },
+ .limits[IPA_RSRC_GROUP_SRC_U_RX_QC] = {
+ .min = 0, .max = 63,
+ },
+ },
+ [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = {
+ .limits[IPA_RSRC_GROUP_SRC_UL] = {
+ .min = 22, .max = 22,
+ },
+ .limits[IPA_RSRC_GROUP_SRC_DL] = {
+ .min = 16, .max = 16,
+ },
+ .limits[IPA_RSRC_GROUP_SRC_URLLC] = {
+ .min = 16, .max = 16,
+ },
+ },
+};
+
+/* Destination resource configuration data for an SoC having IPA v5.0 */
+static const struct ipa_resource ipa_resource_dst[] = {
+ [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = {
+ .limits[IPA_RSRC_GROUP_DST_UL] = {
+ .min = 6, .max = 6,
+ },
+ .limits[IPA_RSRC_GROUP_DST_DL] = {
+ .min = 5, .max = 5,
+ },
+ .limits[IPA_RSRC_GROUP_DST_DRB_IP] = {
+ .min = 39, .max = 39,
+ },
+ },
+ [IPA_RESOURCE_TYPE_DST_DPS_DMARS] = {
+ .limits[IPA_RSRC_GROUP_DST_UL] = {
+ .min = 0, .max = 3,
+ },
+ .limits[IPA_RSRC_GROUP_DST_DL] = {
+ .min = 0, .max = 3,
+ },
+ },
+ [IPA_RESOURCE_TYPE_DST_ULSO_SEGMENTS] = {
+ .limits[IPA_RSRC_GROUP_DST_UL] = {
+ .min = 0, .max = 63,
+ },
+ .limits[IPA_RSRC_GROUP_DST_DL] = {
+ .min = 0, .max = 63,
+ },
+ },
+};
+
+/* Resource configuration data for an SoC having IPA v5.0 */
+static const struct ipa_resource_data ipa_resource_data = {
+ .rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT,
+ .rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT,
+ .resource_src_count = ARRAY_SIZE(ipa_resource_src),
+ .resource_src = ipa_resource_src,
+ .resource_dst_count = ARRAY_SIZE(ipa_resource_dst),
+ .resource_dst = ipa_resource_dst,
+};
+
+/* IPA-resident memory region data for an SoC having IPA v5.0 */
+static const struct ipa_mem ipa_mem_local_data[] = {
+ {
+ .id = IPA_MEM_UC_EVENT_RING,
+ .offset = 0x0000,
+ .size = 0x1000,
+ .canary_count = 0,
+ },
+ {
+ .id = IPA_MEM_UC_SHARED,
+ .offset = 0x1000,
+ .size = 0x0080,
+ .canary_count = 0,
+ },
+ {
+ .id = IPA_MEM_UC_INFO,
+ .offset = 0x1080,
+ .size = 0x0200,
+ .canary_count = 0,
+ },
+ {
+ .id = IPA_MEM_V4_FILTER_HASHED,
+ .offset = 0x1288,
+ .size = 0x0078,
+ .canary_count = 2,
+ },
+ {
+ .id = IPA_MEM_V4_FILTER,
+ .offset = 0x1308,
+ .size = 0x0078,
+ .canary_count = 2,
+ },
+ {
+ .id = IPA_MEM_V6_FILTER_HASHED,
+ .offset = 0x1388,
+ .size = 0x0078,
+ .canary_count = 2,
+ },
+ {
+ .id = IPA_MEM_V6_FILTER,
+ .offset = 0x1408,
+ .size = 0x0078,
+ .canary_count = 2,
+ },
+ {
+ .id = IPA_MEM_V4_ROUTE_HASHED,
+ .offset = 0x1488,
+ .size = 0x0098,
+ .canary_count = 2,
+ },
+ {
+ .id = IPA_MEM_V4_ROUTE,
+ .offset = 0x1528,
+ .size = 0x0098,
+ .canary_count = 2,
+ },
+ {
+ .id = IPA_MEM_V6_ROUTE_HASHED,
+ .offset = 0x15c8,
+ .size = 0x0098,
+ .canary_count = 2,
+ },
+ {
+ .id = IPA_MEM_V6_ROUTE,
+ .offset = 0x1668,
+ .size = 0x0098,
+ .canary_count = 2,
+ },
+ {
+ .id = IPA_MEM_MODEM_HEADER,
+ .offset = 0x1708,
+ .size = 0x0240,
+ .canary_count = 2,
+ },
+ {
+ .id = IPA_MEM_AP_HEADER,
+ .offset = 0x1948,
+ .size = 0x01e0,
+ .canary_count = 0,
+ },
+ {
+ .id = IPA_MEM_MODEM_PROC_CTX,
+ .offset = 0x1b40,
+ .size = 0x0b20,
+ .canary_count = 2,
+ },
+ {
+ .id = IPA_MEM_AP_PROC_CTX,
+ .offset = 0x2660,
+ .size = 0x0200,
+ .canary_count = 0,
+ },
+ {
+ .id = IPA_MEM_STATS_QUOTA_MODEM,
+ .offset = 0x2868,
+ .size = 0x0060,
+ .canary_count = 2,
+ },
+ {
+ .id = IPA_MEM_STATS_QUOTA_AP,
+ .offset = 0x28c8,
+ .size = 0x0048,
+ .canary_count = 0,
+ },
+ {
+ .id = IPA_MEM_AP_V4_FILTER,
+ .offset = 0x2918,
+ .size = 0x0118,
+ .canary_count = 2,
+ },
+ {
+ .id = IPA_MEM_AP_V6_FILTER,
+ .offset = 0x2aa0,
+ .size = 0x0228,
+ .canary_count = 0,
+ },
+ {
+ .id = IPA_MEM_STATS_FILTER_ROUTE,
+ .offset = 0x2cd0,
+ .size = 0x0ba0,
+ .canary_count = 2,
+ },
+ {
+ .id = IPA_MEM_STATS_DROP,
+ .offset = 0x3870,
+ .size = 0x0020,
+ .canary_count = 0,
+ },
+ {
+ .id = IPA_MEM_MODEM,
+ .offset = 0x3898,
+ .size = 0x0d48,
+ .canary_count = 2,
+ },
+ {
+ .id = IPA_MEM_NAT_TABLE,
+ .offset = 0x45e0,
+ .size = 0x0900,
+ .canary_count = 0,
+ },
+ {
+ .id = IPA_MEM_PDN_CONFIG,
+ .offset = 0x4ee8,
+ .size = 0x0100,
+ .canary_count = 2,
+ },
+};
+
+/* Memory configuration data for an SoC having IPA v5.0 */
+static const struct ipa_mem_data ipa_mem_data = {
+ .local_count = ARRAY_SIZE(ipa_mem_local_data),
+ .local = ipa_mem_local_data,
+ .imem_addr = 0x14688000,
+ .imem_size = 0x00003000,
+ .smem_id = 497,
+ .smem_size = 0x00009000,
+};
+
+/* Interconnect rates are in 1000 byte/second units */
+static const struct ipa_interconnect_data ipa_interconnect_data[] = {
+ {
+ .name = "memory",
+ .peak_bandwidth = 1900000, /* 1.9 GBps */
+ .average_bandwidth = 600000, /* 600 MBps */
+ },
+ /* Average rate is unused for the next interconnect */
+ {
+ .name = "config",
+ .peak_bandwidth = 76800, /* 76.8 MBps */
+ .average_bandwidth = 0, /* unused */
+ },
+};
+
+/* Clock and interconnect configuration data for an SoC having IPA v5.0 */
+static const struct ipa_power_data ipa_power_data = {
+ .core_clock_rate = 120 * 1000 * 1000, /* Hz */
+ .interconnect_count = ARRAY_SIZE(ipa_interconnect_data),
+ .interconnect_data = ipa_interconnect_data,
+};
+
+/* Configuration data for an SoC having IPA v5.0. */
+const struct ipa_data ipa_data_v5_0 = {
+ .version = IPA_VERSION_5_0,
+ .qsb_count = ARRAY_SIZE(ipa_qsb_data),
+ .qsb_data = ipa_qsb_data,
+ .modem_route_count = 11,
+ .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data),
+ .endpoint_data = ipa_gsi_endpoint_data,
+ .resource_data = &ipa_resource_data,
+ .mem_data = &ipa_mem_data,
+ .power_data = &ipa_power_data,
+};
diff --git a/drivers/net/ipa/ipa_data.h b/drivers/net/ipa/ipa_data.h
index 818e64114ed50..ce82b00fdc498 100644
--- a/drivers/net/ipa/ipa_data.h
+++ b/drivers/net/ipa/ipa_data.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
- * Copyright (C) 2019-2022 Linaro Ltd.
+ * Copyright (C) 2019-2023 Linaro Ltd.
*/
#ifndef _IPA_DATA_H_
#define _IPA_DATA_H_
@@ -249,5 +249,6 @@ extern const struct ipa_data ipa_data_v4_5;
extern const struct ipa_data ipa_data_v4_7;
extern const struct ipa_data ipa_data_v4_9;
extern const struct ipa_data ipa_data_v4_11;
+extern const struct ipa_data ipa_data_v5_0;
#endif /* _IPA_DATA_H_ */
diff --git a/drivers/net/ipa/ipa_main.c b/drivers/net/ipa/ipa_main.c
index 4cc8d8d6bc9b7..6a2f2fc2f501e 100644
--- a/drivers/net/ipa/ipa_main.c
+++ b/drivers/net/ipa/ipa_main.c
@@ -285,7 +285,7 @@ static void ipa_hardware_config_comp(struct ipa *ipa)
} else if (ipa->version < IPA_VERSION_4_5) {
val |= reg_bit(reg, GSI_MULTI_AXI_MASTERS_DIS);
} else {
- /* For IPA v4.5 FULL_FLUSH_WAIT_RS_CLOSURE_EN is 0 */
+ /* For IPA v4.5+ FULL_FLUSH_WAIT_RS_CLOSURE_EN is 0 */
}
val |= reg_bit(reg, GSI_MULTI_INORDER_RD_DIS);
@@ -684,6 +684,10 @@ static const struct of_device_id ipa_match[] = {
.compatible = "qcom,sc7280-ipa",
.data = &ipa_data_v4_11,
},
+ {
+ .compatible = "qcom,sdx65-ipa",
+ .data = &ipa_data_v5_0,
+ },
{ },
};
MODULE_DEVICE_TABLE(of, ipa_match);
--
2.34.1
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