[PATCH v2 0/4] Fix some issues of xHCI for zhaoxin

[PATCH v2 0/4] Fix some issues of xHCI for zhaoxin

[Weitao Wang]

Fix some issues of xHCI for zhaoxin.

Weitao Wang (4):
  xhci: Add some quirks for zhaoxin xhci to fix issues
  xhci: fix issue of cross page boundary in TRB prefetch
  xhci: Show zhaoxin xHCI root hub speed correctly
  xhci: Add zhaoxin xHCI U1/U2 feature support

 drivers/usb/host/xhci-mem.c |  8 +++--
 drivers/usb/host/xhci-pci.c | 11 +++++++
 drivers/usb/host/xhci.c     | 65 +++++++++++++++++++++++--------------
 drivers/usb/host/xhci.h     |  2 ++
 4 files changed, 59 insertions(+), 27 deletions(-)

-- 
2.32.0

[PATCH v2 1/4] xhci: Add some quirks for zhaoxin xhci to fix issues

[Weitao Wang]

Add a quirk XHCI_ZHAOXIN_HOST for zhaoxin xhci to fix issues,
there are two cases will be used.
- add u1/u2 support.
- fix xHCI root hub speed show issue in zhaoxin platform.

Add a quirk XHCI_ZHAOXIN_TRB_FETCH to fix TRB prefetch issue.

On Zhaoxin ZX-100 project, xHCI can't work normally after resume
from system Sx state. To fix this issue, when resume from system
sx state, reinitialize xHCI instead of restore.
So, Add XHCI_RESET_ON_RESUME quirk for zx-100 to fix issue of
resuming from system sx state.

Cc: stable@vger.kernel.org
Signed-off-by: Weitao Wang <WeitaoWang-oc@zhaoxin.com>
---
v1->v2
 - Add more quirks of xhci for zhaoxin.

 drivers/usb/host/xhci-pci.c | 11 +++++++++++
 drivers/usb/host/xhci.h     |  2 ++
 2 files changed, 13 insertions(+)

diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c
index 6db07ca419c3..53b7d8a1ed0a 100644
--- a/drivers/usb/host/xhci-pci.c
+++ b/drivers/usb/host/xhci-pci.c
@@ -334,6 +334,17 @@ static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
 	     pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4))
 		xhci->quirks |= XHCI_NO_SOFT_RETRY;
 
+	if (pdev->vendor == PCI_VENDOR_ID_ZHAOXIN) {
+		xhci->quirks |= XHCI_LPM_SUPPORT;
+		xhci->quirks |= XHCI_ZHAOXIN_HOST;
+		if (pdev->device == 0x9202) {
+			xhci->quirks |= XHCI_RESET_ON_RESUME;
+			xhci->quirks |= XHCI_ZHAOXIN_TRB_FETCH;
+		}
+		if (pdev->device == 0x9203)
+			xhci->quirks |= XHCI_ZHAOXIN_TRB_FETCH;
+	}
+
 	/* xHC spec requires PCI devices to support D3hot and D3cold */
 	if (xhci->hci_version >= 0x120)
 		xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
index 786002bb35db..8f8f0e91b0dc 100644
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -1905,6 +1905,8 @@ struct xhci_hcd {
 #define XHCI_EP_CTX_BROKEN_DCS	BIT_ULL(42)
 #define XHCI_SUSPEND_RESUME_CLKS	BIT_ULL(43)
 #define XHCI_RESET_TO_DEFAULT	BIT_ULL(44)
+#define XHCI_ZHAOXIN_HOST	BIT_ULL(45)
+#define XHCI_ZHAOXIN_TRB_FETCH	BIT_ULL(46)
 
 	unsigned int		num_active_eps;
 	unsigned int		limit_active_eps;
-- 
2.32.0

[PATCH v2 2/4] xhci: fix issue of cross page boundary in TRB prefetch

[Weitao Wang]

On some Zhaoxin platforms, xHCI will prefetch TRB for performance
improvement. However this TRB prefetch mechanism may cross page boundary,
which may access memory not allocated by xHCI driver. In order to fix
this issue, two pages was allocated for TRB and only the first
page will be used.

Cc: stable@vger.kernel.org
Signed-off-by: Weitao Wang <WeitaoWang-oc@zhaoxin.com>
---
 drivers/usb/host/xhci-mem.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
index d0a9467aa5fc..d5517400d874 100644
--- a/drivers/usb/host/xhci-mem.c
+++ b/drivers/usb/host/xhci-mem.c
@@ -2369,8 +2369,12 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
 	 * and our use of dma addresses in the trb_address_map radix tree needs
 	 * TRB_SEGMENT_SIZE alignment, so we pick the greater alignment need.
 	 */
-	xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
-			TRB_SEGMENT_SIZE, TRB_SEGMENT_SIZE, xhci->page_size);
+	if (xhci->quirks & XHCI_ZHAOXIN_TRB_FETCH)
+		xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
+				TRB_SEGMENT_SIZE * 2, TRB_SEGMENT_SIZE * 2, xhci->page_size * 2);
+	else
+		xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
+				TRB_SEGMENT_SIZE, TRB_SEGMENT_SIZE, xhci->page_size);
 
 	/* See Table 46 and Note on Figure 55 */
 	xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev,
-- 
2.32.0

[PATCH v2 3/4] xhci: Show zhaoxin xHCI root hub speed correctly

[Weitao Wang]

Some zhaoxin xHCI controllers follow usb3.1 spec,
but only support gen1 speed 5G. While in Linux kernel,
if xHCI suspport usb3.1,root hub speed will show on 10G.
To fix this issue of zhaoxin xHCI platforms, read usb speed ID
supported by xHCI to determine root hub speed.

Signed-off-by: Weitao Wang <WeitaoWang-oc@zhaoxin.com>
---
 drivers/usb/host/xhci.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index 6307bae9cddf..31d6ace9cace 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -5294,6 +5294,7 @@ static void xhci_hcd_init_usb2_data(struct xhci_hcd *xhci, struct usb_hcd *hcd)
 static void xhci_hcd_init_usb3_data(struct xhci_hcd *xhci, struct usb_hcd *hcd)
 {
 	unsigned int minor_rev;
+	unsigned int i, j;
 
 	/*
 	 * Early xHCI 1.1 spec did not mention USB 3.1 capable hosts
@@ -5323,6 +5324,27 @@ static void xhci_hcd_init_usb3_data(struct xhci_hcd *xhci, struct usb_hcd *hcd)
 		hcd->self.root_hub->ssp_rate = USB_SSP_GEN_2x1;
 		break;
 	}
+
+	/* Usb3.1 has gen1 and gen2, Some zhaoxin's xHCI controller
+	 * that follow usb3.1 spec but only support gen1.
+	 */
+	if (xhci->quirks & XHCI_ZHAOXIN_HOST) {
+		minor_rev = 0;
+		for (j = 0; j < xhci->num_port_caps; j++) {
+			for (i = 0; i < xhci->port_caps[j].psi_count; i++) {
+				if (XHCI_EXT_PORT_PSIV(xhci->port_caps[j].psi[i]) >= 5) {
+					minor_rev = 1;
+					break;
+				}
+			}
+			if (minor_rev)
+				break;
+		}
+		if (minor_rev != 1) {
+			hcd->speed = HCD_USB3;
+			hcd->self.root_hub->speed = USB_SPEED_SUPER;
+		}
+	}
 	xhci_info(xhci, "Host supports USB 3.%x %sSuperSpeed\n",
 		  minor_rev, minor_rev ? "Enhanced " : "");
 
-- 
2.32.0

[PATCH v2 4/4] xhci: Add zhaoxin xHCI U1/U2 feature support

[Weitao Wang]

Add U1/U2 feature support of xHCI for zhaoxin.
Since both Intel and Zhaoxin need to check the tier where the device is
located to determine whether to enabled U1/U2, remove the previous Intel
U1/U2 tier policy and add common policy in xhci_check_tier_policy.
If vendor has specific U1/U2 enable policy,quirks can be add to declare.

Suggested-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Weitao Wang <WeitaoWang-oc@zhaoxin.com>
---
 v1->v2
 - Modify the description.
 - Adjust U1/U2 tier enable policy.

 drivers/usb/host/xhci.c | 43 +++++++++++++++++------------------------
 1 file changed, 18 insertions(+), 25 deletions(-)

diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index 31d6ace9cace..b81a69126188 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -4802,7 +4802,7 @@ static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
 		}
 	}
 
-	if (xhci->quirks & XHCI_INTEL_HOST)
+	if (xhci->quirks & (XHCI_INTEL_HOST | XHCI_ZHAOXIN_HOST))
 		timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
 	else
 		timeout_ns = udev->u1_params.sel;
@@ -4866,7 +4866,7 @@ static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
 		}
 	}
 
-	if (xhci->quirks & XHCI_INTEL_HOST)
+	if (xhci->quirks & (XHCI_INTEL_HOST | XHCI_ZHAOXIN_HOST))
 		timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
 	else
 		timeout_ns = udev->u2_params.sel;
@@ -4938,37 +4938,30 @@ static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
 	return 0;
 }
 
-static int xhci_check_intel_tier_policy(struct usb_device *udev,
+static int xhci_check_tier_policy(struct xhci_hcd *xhci,
+		struct usb_device *udev,
 		enum usb3_link_state state)
 {
-	struct usb_device *parent;
-	unsigned int num_hubs;
+	struct usb_device *parent = udev->parent;
+	int tier = 1; /* roothub is tier1 */
 
-	/* Don't enable U1 if the device is on a 2nd tier hub or lower. */
-	for (parent = udev->parent, num_hubs = 0; parent->parent;
-			parent = parent->parent)
-		num_hubs++;
+	while (parent) {
+		parent = parent->parent;
+		tier++;
+	}
 
-	if (num_hubs < 2)
-		return 0;
+	if (xhci->quirks & XHCI_INTEL_HOST && tier > 3)
+		goto fail;
+	if (xhci->quirks & XHCI_ZHAOXIN_HOST && tier > 2)
+		goto fail;
 
-	dev_dbg(&udev->dev, "Disabling U1/U2 link state for device"
-			" below second-tier hub.\n");
-	dev_dbg(&udev->dev, "Plug device into first-tier hub "
-			"to decrease power consumption.\n");
+	return 0;
+fail:
+	dev_dbg(&udev->dev, "Tier policy prevents U1/U2 LPM states for devices at tier %d\n",
+			tier);
 	return -E2BIG;
 }
 
-static int xhci_check_tier_policy(struct xhci_hcd *xhci,
-		struct usb_device *udev,
-		enum usb3_link_state state)
-{
-	if (xhci->quirks & XHCI_INTEL_HOST)
-		return xhci_check_intel_tier_policy(udev, state);
-	else
-		return 0;
-}
-
 /* Returns the U1 or U2 timeout that should be enabled.
  * If the tier check or timeout setting functions return with a non-zero exit
  * code, that means the timeout value has been finalized and we shouldn't look
-- 
2.32.0

Re: [PATCH v2 3/4] xhci: Show zhaoxin xHCI root hub speed correctly

[Mathias Nyman]

On 21.4.2023 23.38, Weitao Wang wrote:
> Some zhaoxin xHCI controllers follow usb3.1 spec,
> but only support gen1 speed 5G. While in Linux kernel,
> if xHCI suspport usb3.1,root hub speed will show on 10G.
> To fix this issue of zhaoxin xHCI platforms, read usb speed ID
> supported by xHCI to determine root hub speed.
> 
> Signed-off-by: Weitao Wang <WeitaoWang-oc@zhaoxin.com>
> ---
>   drivers/usb/host/xhci.c | 22 ++++++++++++++++++++++
>   1 file changed, 22 insertions(+)
> 
> diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
> index 6307bae9cddf..31d6ace9cace 100644
> --- a/drivers/usb/host/xhci.c
> +++ b/drivers/usb/host/xhci.c
> @@ -5294,6 +5294,7 @@ static void xhci_hcd_init_usb2_data(struct xhci_hcd *xhci, struct usb_hcd *hcd)
>   static void xhci_hcd_init_usb3_data(struct xhci_hcd *xhci, struct usb_hcd *hcd)
>   {
>   	unsigned int minor_rev;
> +	unsigned int i, j;
>   
>   	/*
>   	 * Early xHCI 1.1 spec did not mention USB 3.1 capable hosts
> @@ -5323,6 +5324,27 @@ static void xhci_hcd_init_usb3_data(struct xhci_hcd *xhci, struct usb_hcd *hcd)
>   		hcd->self.root_hub->ssp_rate = USB_SSP_GEN_2x1;
>   		break;
>   	}
> +
> +	/* Usb3.1 has gen1 and gen2, Some zhaoxin's xHCI controller
> +	 * that follow usb3.1 spec but only support gen1.
> +	 */
> +	if (xhci->quirks & XHCI_ZHAOXIN_HOST) {
> +		minor_rev = 0;
> +		for (j = 0; j < xhci->num_port_caps; j++) {
> +			for (i = 0; i < xhci->port_caps[j].psi_count; i++) {
> +				if (XHCI_EXT_PORT_PSIV(xhci->port_caps[j].psi[i]) >= 5) {
> +					minor_rev = 1;
> +					break;
> +				}
> +			}
> +			if (minor_rev)
> +				break;
> +		}
> +		if (minor_rev != 1) {
> +			hcd->speed = HCD_USB3;
> +			hcd->self.root_hub->speed = USB_SPEED_SUPER;
> +		}
> +	}
>   	xhci_info(xhci, "Host supports USB 3.%x %sSuperSpeed\n",
>   		  minor_rev, minor_rev ? "Enhanced " : "");
>   

How about checking if port support over 5Gbps (psiv >= 5) when we parse the protocol speed ID
entries the first time? This way we could avoid looping through all the port_cap psiv values.

Something like:

diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
index c4170421bc9c..2e4c80eb4972 100644
--- a/drivers/usb/host/xhci-mem.c
+++ b/drivers/usb/host/xhci-mem.c
@@ -1961,7 +1961,7 @@ static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
  {
         u32 temp, port_offset, port_count;
         int i;
-       u8 major_revision, minor_revision;
+       u8 major_revision, minor_revision, tmp_minor_revision;
         struct xhci_hub *rhub;
         struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
         struct xhci_port_cap *port_cap;
@@ -1981,6 +1981,11 @@ static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
                  */
                 if (minor_revision > 0x00 && minor_revision < 0x10)
                         minor_revision <<= 4;
+               if (xhci->quirks & XHCI_ZHAOXIN_HOST) {
+                       tmp_minor_revision = minor_revision;
+                       minor_revision = 0;
+               }
+
         } else if (major_revision <= 0x02) {
                 rhub = &xhci->usb2_rhub;
         } else {
@@ -1989,10 +1994,6 @@ static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
                 /* Ignoring port protocol we can't understand. FIXME */
                 return;
         }
-       rhub->maj_rev = XHCI_EXT_PORT_MAJOR(temp);
-
-       if (rhub->min_rev < minor_revision)
-               rhub->min_rev = minor_revision;
  
         /* Port offset and count in the third dword, see section 7.2 */
         temp = readl(addr + 2);
@@ -2010,8 +2011,6 @@ static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
         if (xhci->num_port_caps > max_caps)
                 return;
  
-       port_cap->maj_rev = major_revision;
-       port_cap->min_rev = minor_revision;
         port_cap->psi_count = XHCI_EXT_PORT_PSIC(temp);
  
         if (port_cap->psi_count) {
@@ -2032,6 +2031,10 @@ static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
                                   XHCI_EXT_PORT_PSIV(port_cap->psi[i - 1])))
                                 port_cap->psi_uid_count++;
  
+                       if (xhci->quirks & XHCI_ZHAOXIN_HOST &&
+                           XHCI_EXT_PORT_PSIV(port_cap->psi[i]) >= 5)
+                               minor_revision = tmp_minor_revision;
+
                         xhci_dbg(xhci, "PSIV:%d PSIE:%d PLT:%d PFD:%d LP:%d PSIM:%d\n",
                                   XHCI_EXT_PORT_PSIV(port_cap->psi[i]),
                                   XHCI_EXT_PORT_PSIE(port_cap->psi[i]),
@@ -2041,6 +2044,15 @@ static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
                                   XHCI_EXT_PORT_PSIM(port_cap->psi[i]));
                 }
         }
+
+       rhub->maj_rev = major_revision;
+
+       if (rhub->min_rev < minor_revision)
+               rhub->min_rev = minor_revision;
+
+       port_cap->maj_rev = major_revision;
+       port_cap->min_rev = minor_revision;
+
         /* cache usb2 port capabilities */
         if (major_revision < 0x03 && xhci->num_ext_caps < max_caps)
                 xhci->ext_caps[xhci->num_ext_caps++] = temp;

Thanks
Mathias

Re: [PATCH v2 3/4] xhci: Show zhaoxin xHCI root hub speed correctly

[WeitaoWang-oc]

On 2023/5/5 18:52, Mathias Nyman wrote:
> On 21.4.2023 23.38, Weitao Wang wrote:
>> Some zhaoxin xHCI controllers follow usb3.1 spec,
>> but only support gen1 speed 5G. While in Linux kernel,
>> if xHCI suspport usb3.1,root hub speed will show on 10G.
>> To fix this issue of zhaoxin xHCI platforms, read usb speed ID
>> supported by xHCI to determine root hub speed.
>>
>> Signed-off-by: Weitao Wang <WeitaoWang-oc@zhaoxin.com>
>> ---
>>   drivers/usb/host/xhci.c | 22 ++++++++++++++++++++++
>>   1 file changed, 22 insertions(+)
>>
>> diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
>> index 6307bae9cddf..31d6ace9cace 100644
>> --- a/drivers/usb/host/xhci.c
>> +++ b/drivers/usb/host/xhci.c
>> @@ -5294,6 +5294,7 @@ static void xhci_hcd_init_usb2_data(struct xhci_hcd *xhci, struct 
>> usb_hcd *hcd)
>>   static void xhci_hcd_init_usb3_data(struct xhci_hcd *xhci, struct usb_hcd *hcd)
>>   {
>>       unsigned int minor_rev;
>> +    unsigned int i, j;
>>       /*
>>        * Early xHCI 1.1 spec did not mention USB 3.1 capable hosts
>> @@ -5323,6 +5324,27 @@ static void xhci_hcd_init_usb3_data(struct xhci_hcd *xhci, struct 
>> usb_hcd *hcd)
>>           hcd->self.root_hub->ssp_rate = USB_SSP_GEN_2x1;
>>           break;
>>       }
>> +
>> +    /* Usb3.1 has gen1 and gen2, Some zhaoxin's xHCI controller
>> +     * that follow usb3.1 spec but only support gen1.
>> +     */
>> +    if (xhci->quirks & XHCI_ZHAOXIN_HOST) {
>> +        minor_rev = 0;
>> +        for (j = 0; j < xhci->num_port_caps; j++) {
>> +            for (i = 0; i < xhci->port_caps[j].psi_count; i++) {
>> +                if (XHCI_EXT_PORT_PSIV(xhci->port_caps[j].psi[i]) >= 5) {
>> +                    minor_rev = 1;
>> +                    break;
>> +                }
>> +            }
>> +            if (minor_rev)
>> +                break;
>> +        }
>> +        if (minor_rev != 1) {
>> +            hcd->speed = HCD_USB3;
>> +            hcd->self.root_hub->speed = USB_SPEED_SUPER;
>> +        }
>> +    }
>>       xhci_info(xhci, "Host supports USB 3.%x %sSuperSpeed\n",
>>             minor_rev, minor_rev ? "Enhanced " : "");
> 
> How about checking if port support over 5Gbps (psiv >= 5) when we parse the protocol speed ID
> entries the first time? This way we could avoid looping through all the port_cap psiv values.
> 
> Something like:
> 
> diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
> index c4170421bc9c..2e4c80eb4972 100644
> --- a/drivers/usb/host/xhci-mem.c
> +++ b/drivers/usb/host/xhci-mem.c
> @@ -1961,7 +1961,7 @@ static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int 
> num_ports,
>   {
>          u32 temp, port_offset, port_count;
>          int i;
> -       u8 major_revision, minor_revision;
> +       u8 major_revision, minor_revision, tmp_minor_revision;
>          struct xhci_hub *rhub;
>          struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
>          struct xhci_port_cap *port_cap;
> @@ -1981,6 +1981,11 @@ static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int 
> num_ports,
>                   */
>                  if (minor_revision > 0x00 && minor_revision < 0x10)
>                          minor_revision <<= 4;
> +               if (xhci->quirks & XHCI_ZHAOXIN_HOST) {
> +                       tmp_minor_revision = minor_revision;
> +                       minor_revision = 0;
> +               }
> +
>          } else if (major_revision <= 0x02) {
>                  rhub = &xhci->usb2_rhub;
>          } else {
> @@ -1989,10 +1994,6 @@ static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int 
> num_ports,
>                  /* Ignoring port protocol we can't understand. FIXME */
>                  return;
>          }
> -       rhub->maj_rev = XHCI_EXT_PORT_MAJOR(temp);
> -
> -       if (rhub->min_rev < minor_revision)
> -               rhub->min_rev = minor_revision;
> 
>          /* Port offset and count in the third dword, see section 7.2 */
>          temp = readl(addr + 2);
> @@ -2010,8 +2011,6 @@ static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int 
> num_ports,
>          if (xhci->num_port_caps > max_caps)
>                  return;
> 
> -       port_cap->maj_rev = major_revision;
> -       port_cap->min_rev = minor_revision;
>          port_cap->psi_count = XHCI_EXT_PORT_PSIC(temp);
> 
>          if (port_cap->psi_count) {
> @@ -2032,6 +2031,10 @@ static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int 
> num_ports,
>                                    XHCI_EXT_PORT_PSIV(port_cap->psi[i - 1])))
>                                  port_cap->psi_uid_count++;
> 
> +                       if (xhci->quirks & XHCI_ZHAOXIN_HOST &&
> +                           XHCI_EXT_PORT_PSIV(port_cap->psi[i]) >= 5)
> +                               minor_revision = tmp_minor_revision;
> +
>                          xhci_dbg(xhci, "PSIV:%d PSIE:%d PLT:%d PFD:%d LP:%d PSIM:%d\n",
>                                    XHCI_EXT_PORT_PSIV(port_cap->psi[i]),
>                                    XHCI_EXT_PORT_PSIE(port_cap->psi[i]),
> @@ -2041,6 +2044,15 @@ static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int 
> num_ports,
>                                    XHCI_EXT_PORT_PSIM(port_cap->psi[i]));
>                  }
>          }
> +
> +       rhub->maj_rev = major_revision;
> +
> +       if (rhub->min_rev < minor_revision)
> +               rhub->min_rev = minor_revision;
> +
> +       port_cap->maj_rev = major_revision;
> +       port_cap->min_rev = minor_revision;
> +

This patch solution is effective and concise. Thanks for your suggestion.
I'll adopt it in next patch version after other patches of this patch set
are reviewed or suggested.

Best Regards,
Weitao
>          /* cache usb2 port capabilities */
>          if (major_revision < 0x03 && xhci->num_ext_caps < max_caps)
>                  xhci->ext_caps[xhci->num_ext_caps++] = temp;
> 
> Thanks
> Mathias
> .

Re: [PATCH v2 1/4] xhci: Add some quirks for zhaoxin xhci to fix issues

[Mathias Nyman]

On 21.4.2023 23.38, Weitao Wang wrote:
> Add a quirk XHCI_ZHAOXIN_HOST for zhaoxin xhci to fix issues,
> there are two cases will be used.
> - add u1/u2 support.
> - fix xHCI root hub speed show issue in zhaoxin platform.
> 
> Add a quirk XHCI_ZHAOXIN_TRB_FETCH to fix TRB prefetch issue.
> 
> On Zhaoxin ZX-100 project, xHCI can't work normally after resume
> from system Sx state. To fix this issue, when resume from system
> sx state, reinitialize xHCI instead of restore.
> So, Add XHCI_RESET_ON_RESUME quirk for zx-100 to fix issue of
> resuming from system sx state.
> 
> Cc: stable@vger.kernel.org
> Signed-off-by: Weitao Wang <WeitaoWang-oc@zhaoxin.com>
> ---

I'd split this series into different logical parts:

patch 1/4
   Set XHCI_RESET_ON_RESUME quirk to ZHAOXIN host to fix resume issue.
   cc: stable

patch 2/4
   Add XHCI_ZHAOXIN_TRB_FETCH quirk flag together with code that allocates double pages
   cc: stable

patch 3/4
   Add XHCI_ZHAOXIN_HOST quirk flag together with code that corrects USB3 roothub minor version
   cc: stable

patch 4/4
   Set XHCI_LPM_SUPPORT quirk together with code that sets tier policy and u1/u2 timeouts,
   Don't add stable as this is about adding feature support.

Thanks
-Mathias