From: Sunil V L <sunilvl@ventanamicro.com>
To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org,
linux-crypto@vger.kernel.org,
platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev
Cc: Jonathan Corbet <corbet@lwn.net>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
"Rafael J . Wysocki" <rafael@kernel.org>,
Len Brown <lenb@kernel.org>, Sunil V L <sunilvl@ventanamicro.com>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Weili Qian <qianweili@huawei.com>,
Zhou Wang <wangzhou1@hisilicon.com>,
Herbert Xu <herbert@gondor.apana.org.au>,
"David S . Miller" <davem@davemloft.net>,
Marc Zyngier <maz@kernel.org>,
Maximilian Luz <luzmaximilian@gmail.com>,
Hans de Goede <hdegoede@redhat.com>,
Mark Gross <markgross@kernel.org>,
Nathan Chancellor <nathan@kernel.org>,
Nick Desaulniers <ndesaulniers@google.com>,
Tom Rix <trix@redhat.com>,
"Rafael J . Wysocki" <rafael.j.wysocki@intel.com>,
Andrew Jones <ajones@ventanamicro.com>,
Palmer Dabbelt <palmer@rivosinc.com>
Subject: [PATCH V6 10/21] drivers/acpi: RISC-V: Add RHCT related code
Date: Mon, 15 May 2023 11:19:17 +0530 [thread overview]
Message-ID: <20230515054928.2079268-11-sunilvl@ventanamicro.com> (raw)
In-Reply-To: <20230515054928.2079268-1-sunilvl@ventanamicro.com>
RHCT is a new table defined for RISC-V to communicate the
features of the CPU to the OS. Create a new architecture folder
in drivers/acpi and add RHCT parsing code.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
---
arch/riscv/include/asm/acpi.h | 8 ++++
drivers/acpi/Makefile | 2 +
drivers/acpi/riscv/Makefile | 2 +
drivers/acpi/riscv/rhct.c | 83 +++++++++++++++++++++++++++++++++++
4 files changed, 95 insertions(+)
create mode 100644 drivers/acpi/riscv/Makefile
create mode 100644 drivers/acpi/riscv/rhct.c
diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h
index 6519529c8bdf..39471759bec1 100644
--- a/arch/riscv/include/asm/acpi.h
+++ b/arch/riscv/include/asm/acpi.h
@@ -62,6 +62,8 @@ static inline void arch_fix_phys_package_id(int num, u32 slot) { }
void acpi_init_rintc_map(void);
struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu);
u32 get_acpi_id_for_cpu(int cpu);
+int acpi_get_riscv_isa(struct acpi_table_header *table,
+ unsigned int cpu, const char **isa);
#else
static inline void acpi_init_rintc_map(void) { }
static inline struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu)
@@ -69,6 +71,12 @@ static inline struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu)
return NULL;
}
+static inline int acpi_get_riscv_isa(struct acpi_table_header *table,
+ unsigned int cpu, const char **isa)
+{
+ return -EINVAL;
+}
+
#endif /* CONFIG_ACPI */
#endif /*_ASM_ACPI_H*/
diff --git a/drivers/acpi/Makefile b/drivers/acpi/Makefile
index feb36c0b9446..3fc5a0d54f6e 100644
--- a/drivers/acpi/Makefile
+++ b/drivers/acpi/Makefile
@@ -131,3 +131,5 @@ obj-y += dptf/
obj-$(CONFIG_ARM64) += arm64/
obj-$(CONFIG_ACPI_VIOT) += viot.o
+
+obj-$(CONFIG_RISCV) += riscv/
diff --git a/drivers/acpi/riscv/Makefile b/drivers/acpi/riscv/Makefile
new file mode 100644
index 000000000000..8b3b126e0b94
--- /dev/null
+++ b/drivers/acpi/riscv/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-y += rhct.o
diff --git a/drivers/acpi/riscv/rhct.c b/drivers/acpi/riscv/rhct.c
new file mode 100644
index 000000000000..b280b3e9c7d9
--- /dev/null
+++ b/drivers/acpi/riscv/rhct.c
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2022-2023, Ventana Micro Systems Inc
+ * Author: Sunil V L <sunilvl@ventanamicro.com>
+ *
+ */
+
+#define pr_fmt(fmt) "ACPI: RHCT: " fmt
+
+#include <linux/acpi.h>
+
+static struct acpi_table_header *acpi_get_rhct(void)
+{
+ static struct acpi_table_header *rhct;
+ acpi_status status;
+
+ /*
+ * RHCT will be used at runtime on every CPU, so we
+ * don't need to call acpi_put_table() to release the table mapping.
+ */
+ if (!rhct) {
+ status = acpi_get_table(ACPI_SIG_RHCT, 0, &rhct);
+ if (ACPI_FAILURE(status)) {
+ pr_warn_once("No RHCT table found\n");
+ return NULL;
+ }
+ }
+
+ return rhct;
+}
+
+/*
+ * During early boot, the caller should call acpi_get_table() and pass its pointer to
+ * these functions(and free up later). At run time, since this table can be used
+ * multiple times, NULL may be passed in order to use the cached table.
+ */
+int acpi_get_riscv_isa(struct acpi_table_header *table, unsigned int cpu, const char **isa)
+{
+ struct acpi_rhct_node_header *node, *ref_node, *end;
+ u32 size_hdr = sizeof(struct acpi_rhct_node_header);
+ u32 size_hartinfo = sizeof(struct acpi_rhct_hart_info);
+ struct acpi_rhct_hart_info *hart_info;
+ struct acpi_rhct_isa_string *isa_node;
+ struct acpi_table_rhct *rhct;
+ u32 *hart_info_node_offset;
+ u32 acpi_cpu_id = get_acpi_id_for_cpu(cpu);
+
+ BUG_ON(acpi_disabled);
+
+ if (!table) {
+ rhct = (struct acpi_table_rhct *)acpi_get_rhct();
+ if (!rhct)
+ return -ENOENT;
+ } else {
+ rhct = (struct acpi_table_rhct *)table;
+ }
+
+ end = ACPI_ADD_PTR(struct acpi_rhct_node_header, rhct, rhct->header.length);
+
+ for (node = ACPI_ADD_PTR(struct acpi_rhct_node_header, rhct, rhct->node_offset);
+ node < end;
+ node = ACPI_ADD_PTR(struct acpi_rhct_node_header, node, node->length)) {
+ if (node->type == ACPI_RHCT_NODE_TYPE_HART_INFO) {
+ hart_info = ACPI_ADD_PTR(struct acpi_rhct_hart_info, node, size_hdr);
+ hart_info_node_offset = ACPI_ADD_PTR(u32, hart_info, size_hartinfo);
+ if (acpi_cpu_id != hart_info->uid)
+ continue;
+
+ for (int i = 0; i < hart_info->num_offsets; i++) {
+ ref_node = ACPI_ADD_PTR(struct acpi_rhct_node_header,
+ rhct, hart_info_node_offset[i]);
+ if (ref_node->type == ACPI_RHCT_NODE_TYPE_ISA_STRING) {
+ isa_node = ACPI_ADD_PTR(struct acpi_rhct_isa_string,
+ ref_node, size_hdr);
+ *isa = isa_node->isa;
+ return 0;
+ }
+ }
+ }
+ }
+
+ return -1;
+}
--
2.34.1
next prev parent reply other threads:[~2023-05-15 5:53 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-15 5:49 [PATCH V6 00/21] Add basic ACPI support for RISC-V Sunil V L
2023-05-15 5:49 ` [PATCH V6 01/21] riscv: move sbi_init() earlier before jump_label_init() Sunil V L
2023-05-15 5:49 ` [PATCH V6 02/21] platform/surface: Disable for RISC-V Sunil V L
2023-05-15 5:49 ` [PATCH V6 03/21] crypto: hisilicon/qm: Fix to enable build with RISC-V clang Sunil V L
2023-05-15 5:54 ` Herbert Xu
2023-05-15 5:49 ` [PATCH V6 04/21] ACPI: tables: Print RINTC information when MADT is parsed Sunil V L
2023-05-15 5:49 ` [PATCH V6 05/21] ACPI: OSL: Make should_use_kmap() 0 for RISC-V Sunil V L
2023-05-15 5:49 ` [PATCH V6 06/21] RISC-V: Add support to build the ACPI core Sunil V L
2023-05-15 5:49 ` [PATCH V6 07/21] ACPI: processor_core: RISC-V: Enable mapping processor to the hartid Sunil V L
2023-05-15 5:49 ` [PATCH V6 08/21] RISC-V: Add ACPI initialization in setup_arch() Sunil V L
2023-05-15 5:49 ` [PATCH V6 09/21] RISC-V: ACPI: Cache and retrieve the RINTC structure Sunil V L
2023-05-23 12:01 ` Andrew Jones
2023-05-15 5:49 ` Sunil V L [this message]
2023-05-15 5:49 ` [PATCH V6 11/21] RISC-V: smpboot: Create wrapper setup_smp() Sunil V L
2023-05-15 5:49 ` [PATCH V6 12/21] RISC-V: smpboot: Add ACPI support in setup_smp() Sunil V L
2023-05-15 5:49 ` [PATCH V6 13/21] RISC-V: only iterate over possible CPUs in ISA string parser Sunil V L
2023-05-15 5:49 ` [PATCH V6 14/21] RISC-V: cpufeature: Add ACPI support in riscv_fill_hwcap() Sunil V L
2023-05-15 5:49 ` [PATCH V6 15/21] RISC-V: cpu: Enable cpuinfo for ACPI systems Sunil V L
2023-05-15 5:49 ` [PATCH V6 16/21] irqchip/riscv-intc: Add ACPI support Sunil V L
2023-05-15 5:49 ` [PATCH V6 17/21] clocksource/timer-riscv: Refactor riscv_timer_init_dt() Sunil V L
2023-05-15 5:49 ` [PATCH V6 18/21] clocksource/timer-riscv: Add ACPI support Sunil V L
2023-05-15 5:49 ` [PATCH V6 19/21] RISC-V: time.c: Add ACPI support for time_init() Sunil V L
2023-05-15 5:49 ` [PATCH V6 20/21] RISC-V: Enable ACPI in defconfig Sunil V L
2023-05-15 5:49 ` [PATCH V6 21/21] MAINTAINERS: Add entry for drivers/acpi/riscv Sunil V L
2023-06-02 14:57 ` (subset) [PATCH V6 00/21] Add basic ACPI support for RISC-V Palmer Dabbelt
2023-06-02 15:11 ` Palmer Dabbelt
2023-06-02 15:50 ` Conor Dooley
2023-06-02 15:54 ` Conor Dooley
2023-06-02 15:00 ` patchwork-bot+linux-riscv
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