From: Sunil V L <sunilvl@ventanamicro.com>
To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org,
linux-crypto@vger.kernel.org,
platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev
Cc: Jonathan Corbet <corbet@lwn.net>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
"Rafael J . Wysocki" <rafael@kernel.org>,
Len Brown <lenb@kernel.org>, Sunil V L <sunilvl@ventanamicro.com>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Weili Qian <qianweili@huawei.com>,
Zhou Wang <wangzhou1@hisilicon.com>,
Herbert Xu <herbert@gondor.apana.org.au>,
"David S . Miller" <davem@davemloft.net>,
Marc Zyngier <maz@kernel.org>,
Maximilian Luz <luzmaximilian@gmail.com>,
Hans de Goede <hdegoede@redhat.com>,
Mark Gross <markgross@kernel.org>,
Nathan Chancellor <nathan@kernel.org>,
Nick Desaulniers <ndesaulniers@google.com>,
Tom Rix <trix@redhat.com>,
"Rafael J . Wysocki" <rafael.j.wysocki@intel.com>,
Conor Dooley <conor.dooley@microchip.com>,
Andrew Jones <ajones@ventanamicro.com>
Subject: [PATCH V6 12/21] RISC-V: smpboot: Add ACPI support in setup_smp()
Date: Mon, 15 May 2023 11:19:19 +0530 [thread overview]
Message-ID: <20230515054928.2079268-13-sunilvl@ventanamicro.com> (raw)
In-Reply-To: <20230515054928.2079268-1-sunilvl@ventanamicro.com>
Enable SMP boot on ACPI based platforms by using the RINTC
structures in the MADT table.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
arch/riscv/include/asm/acpi.h | 2 +
arch/riscv/kernel/smpboot.c | 72 ++++++++++++++++++++++++++++++++++-
2 files changed, 73 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h
index 39471759bec1..f71ce21ff684 100644
--- a/arch/riscv/include/asm/acpi.h
+++ b/arch/riscv/include/asm/acpi.h
@@ -64,6 +64,8 @@ struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu);
u32 get_acpi_id_for_cpu(int cpu);
int acpi_get_riscv_isa(struct acpi_table_header *table,
unsigned int cpu, const char **isa);
+
+static inline int acpi_numa_get_nid(unsigned int cpu) { return NUMA_NO_NODE; }
#else
static inline void acpi_init_rintc_map(void) { }
static inline struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu)
diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
index a2e66126b733..67bc5ef3e8b2 100644
--- a/arch/riscv/kernel/smpboot.c
+++ b/arch/riscv/kernel/smpboot.c
@@ -8,6 +8,7 @@
* Copyright (C) 2017 SiFive
*/
+#include <linux/acpi.h>
#include <linux/arch_topology.h>
#include <linux/module.h>
#include <linux/init.h>
@@ -70,6 +71,72 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
}
}
+#ifdef CONFIG_ACPI
+static unsigned int cpu_count = 1;
+
+static int __init acpi_parse_rintc(union acpi_subtable_headers *header, const unsigned long end)
+{
+ unsigned long hart;
+ static bool found_boot_cpu;
+ struct acpi_madt_rintc *processor = (struct acpi_madt_rintc *)header;
+
+ /*
+ * Each RINTC structure in MADT will have a flag. If ACPI_MADT_ENABLED
+ * bit in the flag is not enabled, it means OS should not try to enable
+ * the cpu to which RINTC belongs.
+ */
+ if (!(processor->flags & ACPI_MADT_ENABLED))
+ return 0;
+
+ if (BAD_MADT_ENTRY(processor, end))
+ return -EINVAL;
+
+ acpi_table_print_madt_entry(&header->common);
+
+ hart = processor->hart_id;
+ if (hart == INVALID_HARTID) {
+ pr_warn("Invalid hartid\n");
+ return 0;
+ }
+
+ if (hart == cpuid_to_hartid_map(0)) {
+ BUG_ON(found_boot_cpu);
+ found_boot_cpu = true;
+ early_map_cpu_to_node(0, acpi_numa_get_nid(cpu_count));
+ return 0;
+ }
+
+ if (cpu_count >= NR_CPUS) {
+ pr_warn("NR_CPUS is too small for the number of ACPI tables.\n");
+ return 0;
+ }
+
+ cpuid_to_hartid_map(cpu_count) = hart;
+ early_map_cpu_to_node(cpu_count, acpi_numa_get_nid(cpu_count));
+ cpu_count++;
+
+ return 0;
+}
+
+static void __init acpi_parse_and_init_cpus(void)
+{
+ int cpuid;
+
+ cpu_set_ops(0);
+
+ acpi_table_parse_madt(ACPI_MADT_TYPE_RINTC, acpi_parse_rintc, 0);
+
+ for (cpuid = 1; cpuid < nr_cpu_ids; cpuid++) {
+ if (cpuid_to_hartid_map(cpuid) != INVALID_HARTID) {
+ cpu_set_ops(cpuid);
+ set_cpu_possible(cpuid, true);
+ }
+ }
+}
+#else
+#define acpi_parse_and_init_cpus(...) do { } while (0)
+#endif
+
static void __init of_parse_and_init_cpus(void)
{
struct device_node *dn;
@@ -118,7 +185,10 @@ static void __init of_parse_and_init_cpus(void)
void __init setup_smp(void)
{
- of_parse_and_init_cpus();
+ if (acpi_disabled)
+ of_parse_and_init_cpus();
+ else
+ acpi_parse_and_init_cpus();
}
static int start_secondary_cpu(int cpu, struct task_struct *tidle)
--
2.34.1
next prev parent reply other threads:[~2023-05-15 5:54 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-15 5:49 [PATCH V6 00/21] Add basic ACPI support for RISC-V Sunil V L
2023-05-15 5:49 ` [PATCH V6 01/21] riscv: move sbi_init() earlier before jump_label_init() Sunil V L
2023-05-15 5:49 ` [PATCH V6 02/21] platform/surface: Disable for RISC-V Sunil V L
2023-05-15 5:49 ` [PATCH V6 03/21] crypto: hisilicon/qm: Fix to enable build with RISC-V clang Sunil V L
2023-05-15 5:54 ` Herbert Xu
2023-05-15 5:49 ` [PATCH V6 04/21] ACPI: tables: Print RINTC information when MADT is parsed Sunil V L
2023-05-15 5:49 ` [PATCH V6 05/21] ACPI: OSL: Make should_use_kmap() 0 for RISC-V Sunil V L
2023-05-15 5:49 ` [PATCH V6 06/21] RISC-V: Add support to build the ACPI core Sunil V L
2023-05-15 5:49 ` [PATCH V6 07/21] ACPI: processor_core: RISC-V: Enable mapping processor to the hartid Sunil V L
2023-05-15 5:49 ` [PATCH V6 08/21] RISC-V: Add ACPI initialization in setup_arch() Sunil V L
2023-05-15 5:49 ` [PATCH V6 09/21] RISC-V: ACPI: Cache and retrieve the RINTC structure Sunil V L
2023-05-23 12:01 ` Andrew Jones
2023-05-15 5:49 ` [PATCH V6 10/21] drivers/acpi: RISC-V: Add RHCT related code Sunil V L
2023-05-15 5:49 ` [PATCH V6 11/21] RISC-V: smpboot: Create wrapper setup_smp() Sunil V L
2023-05-15 5:49 ` Sunil V L [this message]
2023-05-15 5:49 ` [PATCH V6 13/21] RISC-V: only iterate over possible CPUs in ISA string parser Sunil V L
2023-05-15 5:49 ` [PATCH V6 14/21] RISC-V: cpufeature: Add ACPI support in riscv_fill_hwcap() Sunil V L
2023-05-15 5:49 ` [PATCH V6 15/21] RISC-V: cpu: Enable cpuinfo for ACPI systems Sunil V L
2023-05-15 5:49 ` [PATCH V6 16/21] irqchip/riscv-intc: Add ACPI support Sunil V L
2023-05-15 5:49 ` [PATCH V6 17/21] clocksource/timer-riscv: Refactor riscv_timer_init_dt() Sunil V L
2023-05-15 5:49 ` [PATCH V6 18/21] clocksource/timer-riscv: Add ACPI support Sunil V L
2023-05-15 5:49 ` [PATCH V6 19/21] RISC-V: time.c: Add ACPI support for time_init() Sunil V L
2023-05-15 5:49 ` [PATCH V6 20/21] RISC-V: Enable ACPI in defconfig Sunil V L
2023-05-15 5:49 ` [PATCH V6 21/21] MAINTAINERS: Add entry for drivers/acpi/riscv Sunil V L
2023-06-02 14:57 ` (subset) [PATCH V6 00/21] Add basic ACPI support for RISC-V Palmer Dabbelt
2023-06-02 15:11 ` Palmer Dabbelt
2023-06-02 15:50 ` Conor Dooley
2023-06-02 15:54 ` Conor Dooley
2023-06-02 15:00 ` patchwork-bot+linux-riscv
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230515054928.2079268-13-sunilvl@ventanamicro.com \
--to=sunilvl@ventanamicro.com \
--cc=ajones@ventanamicro.com \
--cc=aou@eecs.berkeley.edu \
--cc=conor.dooley@microchip.com \
--cc=corbet@lwn.net \
--cc=daniel.lezcano@linaro.org \
--cc=davem@davemloft.net \
--cc=hdegoede@redhat.com \
--cc=herbert@gondor.apana.org.au \
--cc=lenb@kernel.org \
--cc=linux-acpi@vger.kernel.org \
--cc=linux-crypto@vger.kernel.org \
--cc=linux-doc@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=llvm@lists.linux.dev \
--cc=luzmaximilian@gmail.com \
--cc=markgross@kernel.org \
--cc=maz@kernel.org \
--cc=nathan@kernel.org \
--cc=ndesaulniers@google.com \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=platform-driver-x86@vger.kernel.org \
--cc=qianweili@huawei.com \
--cc=rafael.j.wysocki@intel.com \
--cc=rafael@kernel.org \
--cc=tglx@linutronix.de \
--cc=trix@redhat.com \
--cc=wangzhou1@hisilicon.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).