* [PATCH V5 0/3] PCI: designware-ep: Fix DBI access before core init
@ 2022-10-13 17:57 Vidya Sagar
2022-10-13 17:57 ` [PATCH V5 1/3] " Vidya Sagar
` (4 more replies)
0 siblings, 5 replies; 13+ messages in thread
From: Vidya Sagar @ 2022-10-13 17:57 UTC (permalink / raw)
To: jingoohan1, gustavo.pimentel, lpieralisi, robh, kw, bhelgaas,
mani, Sergey.Semin, dmitry.baryshkov, linmq006, ffclaire1224
Cc: thierry.reding, jonathanh, linux-pci, linux-arm-msm,
linux-kernel, kthota, mmaddireddy, vidyas, sagar.tv
This series attempts to fix the issue with core register (Ex:- DBI) accesses
causing system hang issues in platforms where there is a dependency on the
availability of PCIe Reference clock from the host for their core
initialization.
This series is verified on Tegra194 & Tegra234 platforms.
Manivannan, could you please verify on qcom platforms?
V5:
* Addressed review comments from Bjorn
* Changed dw_pcie_ep_init_complete() to dw_pcie_ep_init_late()
* Skipped memory allocation if done already. This is to avoid freeing and then
allocating again during PERST# toggles from the host.
V4:
* Addressed review comments from Bjorn and Manivannan
* Added .ep_init_late() ops
* Added patches to refactor code in qcom and tegra platforms
Vidya Sagar (3):
PCI: designware-ep: Fix DBI access before core init
PCI: qcom-ep: Refactor EP initialization completion
PCI: tegra194: Refactor EP initialization completion
.../pci/controller/dwc/pcie-designware-ep.c | 125 +++++++++++-------
drivers/pci/controller/dwc/pcie-designware.h | 10 +-
drivers/pci/controller/dwc/pcie-qcom-ep.c | 27 ++--
drivers/pci/controller/dwc/pcie-tegra194.c | 4 +-
4 files changed, 97 insertions(+), 69 deletions(-)
--
2.17.1
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH V5 1/3] PCI: designware-ep: Fix DBI access before core init
2022-10-13 17:57 [PATCH V5 0/3] PCI: designware-ep: Fix DBI access before core init Vidya Sagar
@ 2022-10-13 17:57 ` Vidya Sagar
2022-10-15 22:00 ` Han Jingoo
2022-10-26 5:10 ` Manivannan Sadhasivam
2022-10-13 17:57 ` [PATCH V5 2/3] PCI: qcom-ep: Refactor EP initialization completion Vidya Sagar
` (3 subsequent siblings)
4 siblings, 2 replies; 13+ messages in thread
From: Vidya Sagar @ 2022-10-13 17:57 UTC (permalink / raw)
To: jingoohan1, gustavo.pimentel, lpieralisi, robh, kw, bhelgaas,
mani, Sergey.Semin, dmitry.baryshkov, linmq006, ffclaire1224
Cc: thierry.reding, jonathanh, linux-pci, linux-arm-msm,
linux-kernel, kthota, mmaddireddy, vidyas, sagar.tv
Platforms that cannot support their core initialization without the
reference clock from the host, implement the feature 'core_init_notifier'
to indicate the DesignWare sub-system about when their core is getting
initialized. Any accesses to the core (Ex:- DBI) would the core being
ready result in system hang in such systems (Ex:- tegra194).
This patch moves any access to the core to dw_pcie_ep_init_complete() API
which is effectively called only after the core initialization.
It also introduces .ep_init_late() ops hook to be used for any post init
work that platform drivers may have to do.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
V5:
* Changed dw_pcie_ep_init_complete() to dw_pcie_ep_init_late()
* Skipped memory allocation if done already. This is to avoid freeing and then
allocating again during PERST# toggles from the host.
V4:
* Addressed review comments from Bjorn and Manivannan
* Moved dw_pcie_ep_init_complete() inside dw_pcie_ep_init_notify()
* Added .ep_init_late() ops to perform late init tasks
.../pci/controller/dwc/pcie-designware-ep.c | 125 +++++++++++-------
drivers/pci/controller/dwc/pcie-designware.h | 10 +-
2 files changed, 80 insertions(+), 55 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 83ddb190292e..f300ea2f7bf7 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -23,14 +23,6 @@ void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
}
EXPORT_SYMBOL_GPL(dw_pcie_ep_linkup);
-void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep)
-{
- struct pci_epc *epc = ep->epc;
-
- pci_epc_init_notify(epc);
-}
-EXPORT_SYMBOL_GPL(dw_pcie_ep_init_notify);
-
struct dw_pcie_ep_func *
dw_pcie_ep_get_func_from_ep(struct dw_pcie_ep *ep, u8 func_no)
{
@@ -640,12 +632,17 @@ static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap)
return 0;
}
-int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
+static int dw_pcie_ep_init_late(struct dw_pcie_ep *ep)
{
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ struct dw_pcie_ep_func *ep_func;
+ struct device *dev = pci->dev;
+ struct pci_epc *epc = ep->epc;
unsigned int offset;
unsigned int nbars;
u8 hdr_type;
+ u8 func_no;
+ void *addr;
u32 reg;
int i;
@@ -658,6 +655,51 @@ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
return -EIO;
}
+ dw_pcie_version_detect(pci);
+
+ dw_pcie_iatu_detect(pci);
+
+ if (!ep->ib_window_map) {
+ ep->ib_window_map = devm_bitmap_zalloc(dev, pci->num_ib_windows,
+ GFP_KERNEL);
+ if (!ep->ib_window_map)
+ return -ENOMEM;
+ }
+
+ if (!ep->ob_window_map) {
+ ep->ob_window_map = devm_bitmap_zalloc(dev, pci->num_ob_windows,
+ GFP_KERNEL);
+ if (!ep->ob_window_map)
+ return -ENOMEM;
+ }
+
+ if (!ep->outbound_addr) {
+ addr = devm_kcalloc(dev, pci->num_ob_windows, sizeof(phys_addr_t),
+ GFP_KERNEL);
+ if (!addr)
+ return -ENOMEM;
+ ep->outbound_addr = addr;
+ }
+
+ for (func_no = 0; func_no < epc->max_functions; func_no++) {
+
+ ep_func = dw_pcie_ep_get_func_from_ep(ep, func_no);
+ if (ep_func)
+ continue;
+
+ ep_func = devm_kzalloc(dev, sizeof(*ep_func), GFP_KERNEL);
+ if (!ep_func)
+ return -ENOMEM;
+
+ ep_func->func_no = func_no;
+ ep_func->msi_cap = dw_pcie_ep_find_capability(ep, func_no,
+ PCI_CAP_ID_MSI);
+ ep_func->msix_cap = dw_pcie_ep_find_capability(ep, func_no,
+ PCI_CAP_ID_MSIX);
+
+ list_add_tail(&ep_func->list, &ep->func_list);
+ }
+
offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR);
dw_pcie_dbi_ro_wr_en(pci);
@@ -676,13 +718,28 @@ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
return 0;
}
-EXPORT_SYMBOL_GPL(dw_pcie_ep_init_complete);
+
+int dw_pcie_ep_init_notify(struct dw_pcie_ep *ep)
+{
+ struct pci_epc *epc = ep->epc;
+ int ret;
+
+ ret = dw_pcie_ep_init_late(ep);
+ if (ret)
+ return ret;
+
+ if (ep->ops->ep_init_late)
+ ep->ops->ep_init_late(ep);
+
+ pci_epc_init_notify(epc);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(dw_pcie_ep_init_notify);
int dw_pcie_ep_init(struct dw_pcie_ep *ep)
{
int ret;
- void *addr;
- u8 func_no;
struct resource *res;
struct pci_epc *epc;
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
@@ -690,7 +747,6 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
struct platform_device *pdev = to_platform_device(dev);
struct device_node *np = dev->of_node;
const struct pci_epc_features *epc_features;
- struct dw_pcie_ep_func *ep_func;
INIT_LIST_HEAD(&ep->func_list);
@@ -719,26 +775,6 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
ep->phys_base = res->start;
ep->addr_size = resource_size(res);
- dw_pcie_version_detect(pci);
-
- dw_pcie_iatu_detect(pci);
-
- ep->ib_window_map = devm_bitmap_zalloc(dev, pci->num_ib_windows,
- GFP_KERNEL);
- if (!ep->ib_window_map)
- return -ENOMEM;
-
- ep->ob_window_map = devm_bitmap_zalloc(dev, pci->num_ob_windows,
- GFP_KERNEL);
- if (!ep->ob_window_map)
- return -ENOMEM;
-
- addr = devm_kcalloc(dev, pci->num_ob_windows, sizeof(phys_addr_t),
- GFP_KERNEL);
- if (!addr)
- return -ENOMEM;
- ep->outbound_addr = addr;
-
if (pci->link_gen < 1)
pci->link_gen = of_pci_get_max_link_speed(np);
@@ -755,20 +791,6 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
if (ret < 0)
epc->max_functions = 1;
- for (func_no = 0; func_no < epc->max_functions; func_no++) {
- ep_func = devm_kzalloc(dev, sizeof(*ep_func), GFP_KERNEL);
- if (!ep_func)
- return -ENOMEM;
-
- ep_func->func_no = func_no;
- ep_func->msi_cap = dw_pcie_ep_find_capability(ep, func_no,
- PCI_CAP_ID_MSI);
- ep_func->msix_cap = dw_pcie_ep_find_capability(ep, func_no,
- PCI_CAP_ID_MSIX);
-
- list_add_tail(&ep_func->list, &ep->func_list);
- }
-
if (ep->ops->ep_init)
ep->ops->ep_init(ep);
@@ -793,7 +815,14 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
return 0;
}
- ret = dw_pcie_ep_init_complete(ep);
+ /*
+ * NOTE:- Avoid accessing the hardware (Ex:- DBI space) before this
+ * step as platforms that implement 'core_init_notifier' feature may
+ * not have the hardware ready (i.e. core initialized) for access
+ * (Ex: tegra194). Any hardware access on such platforms result
+ * in system hard hang.
+ */
+ ret = dw_pcie_ep_init_late(ep);
if (ret)
goto err_free_epc_mem;
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 45fcdfc8c035..7252513956b7 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -253,6 +253,7 @@ struct dw_pcie_rp {
struct dw_pcie_ep_ops {
void (*ep_init)(struct dw_pcie_ep *ep);
+ void (*ep_init_late)(struct dw_pcie_ep *ep);
int (*raise_irq)(struct dw_pcie_ep *ep, u8 func_no,
enum pci_epc_irq_type type, u16 interrupt_num);
const struct pci_epc_features* (*get_features)(struct dw_pcie_ep *ep);
@@ -467,8 +468,7 @@ static inline void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus,
#ifdef CONFIG_PCIE_DW_EP
void dw_pcie_ep_linkup(struct dw_pcie_ep *ep);
int dw_pcie_ep_init(struct dw_pcie_ep *ep);
-int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep);
-void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep);
+int dw_pcie_ep_init_notify(struct dw_pcie_ep *ep);
void dw_pcie_ep_exit(struct dw_pcie_ep *ep);
int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no);
int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
@@ -490,15 +490,11 @@ static inline int dw_pcie_ep_init(struct dw_pcie_ep *ep)
return 0;
}
-static inline int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
+static inline int dw_pcie_ep_init_notify(struct dw_pcie_ep *ep)
{
return 0;
}
-static inline void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep)
-{
-}
-
static inline void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
{
}
--
2.17.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH V5 2/3] PCI: qcom-ep: Refactor EP initialization completion
2022-10-13 17:57 [PATCH V5 0/3] PCI: designware-ep: Fix DBI access before core init Vidya Sagar
2022-10-13 17:57 ` [PATCH V5 1/3] " Vidya Sagar
@ 2022-10-13 17:57 ` Vidya Sagar
2022-10-26 5:30 ` Manivannan Sadhasivam
2022-10-13 17:57 ` [PATCH V5 3/3] PCI: tegra194: " Vidya Sagar
` (2 subsequent siblings)
4 siblings, 1 reply; 13+ messages in thread
From: Vidya Sagar @ 2022-10-13 17:57 UTC (permalink / raw)
To: jingoohan1, gustavo.pimentel, lpieralisi, robh, kw, bhelgaas,
mani, Sergey.Semin, dmitry.baryshkov, linmq006, ffclaire1224
Cc: thierry.reding, jonathanh, linux-pci, linux-arm-msm,
linux-kernel, kthota, mmaddireddy, vidyas, sagar.tv
Move the post initialization code to .ep_init_late() call back and call
only dw_pcie_ep_init_notify() which internally takes care of calling
dw_pcie_ep_init_complete().
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
V5:
* None
V4:
* New patch in this series
drivers/pci/controller/dwc/pcie-qcom-ep.c | 27 ++++++++++++++---------
1 file changed, 16 insertions(+), 11 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
index e33eb3871309..c418b20042aa 100644
--- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
+++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
@@ -361,22 +361,12 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci)
PARF_INT_ALL_LINK_UP;
writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_MASK);
- ret = dw_pcie_ep_init_complete(&pcie_ep->pci.ep);
+ ret = dw_pcie_ep_init_notify(&pcie_ep->pci.ep);
if (ret) {
dev_err(dev, "Failed to complete initialization: %d\n", ret);
goto err_disable_resources;
}
- /*
- * The physical address of the MMIO region which is exposed as the BAR
- * should be written to MHI BASE registers.
- */
- writel_relaxed(pcie_ep->mmio_res->start,
- pcie_ep->parf + PARF_MHI_BASE_ADDR_LOWER);
- writel_relaxed(0, pcie_ep->parf + PARF_MHI_BASE_ADDR_UPPER);
-
- dw_pcie_ep_init_notify(&pcie_ep->pci.ep);
-
/* Enable LTSSM */
val = readl_relaxed(pcie_ep->parf + PARF_LTSSM);
val |= BIT(8);
@@ -643,8 +633,23 @@ static void qcom_pcie_ep_init(struct dw_pcie_ep *ep)
dw_pcie_ep_reset_bar(pci, bar);
}
+static void qcom_pcie_ep_init_late(struct dw_pcie_ep *ep)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
+
+ /*
+ * The physical address of the MMIO region which is exposed as the BAR
+ * should be written to MHI BASE registers.
+ */
+ writel_relaxed(pcie_ep->mmio_res->start,
+ pcie_ep->parf + PARF_MHI_BASE_ADDR_LOWER);
+ writel_relaxed(0, pcie_ep->parf + PARF_MHI_BASE_ADDR_UPPER);
+}
+
static const struct dw_pcie_ep_ops pci_ep_ops = {
.ep_init = qcom_pcie_ep_init,
+ .ep_init_late = qcom_pcie_ep_init_late,
.raise_irq = qcom_pcie_ep_raise_irq,
.get_features = qcom_pcie_epc_get_features,
};
--
2.17.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH V5 3/3] PCI: tegra194: Refactor EP initialization completion
2022-10-13 17:57 [PATCH V5 0/3] PCI: designware-ep: Fix DBI access before core init Vidya Sagar
2022-10-13 17:57 ` [PATCH V5 1/3] " Vidya Sagar
2022-10-13 17:57 ` [PATCH V5 2/3] PCI: qcom-ep: Refactor EP initialization completion Vidya Sagar
@ 2022-10-13 17:57 ` Vidya Sagar
2022-10-14 6:10 ` [PATCH V5 0/3] PCI: designware-ep: Fix DBI access before core init Manivannan Sadhasivam
2023-02-14 13:03 ` Manivannan Sadhasivam
4 siblings, 0 replies; 13+ messages in thread
From: Vidya Sagar @ 2022-10-13 17:57 UTC (permalink / raw)
To: jingoohan1, gustavo.pimentel, lpieralisi, robh, kw, bhelgaas,
mani, Sergey.Semin, dmitry.baryshkov, linmq006, ffclaire1224
Cc: thierry.reding, jonathanh, linux-pci, linux-arm-msm,
linux-kernel, kthota, mmaddireddy, vidyas, sagar.tv
Call only dw_pcie_ep_init_notify() which internally takes care of calling
dw_pcie_ep_init_complete() to notify about the EP initialization
completion to the DWC EP framework.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
V5:
* None
V4:
* New patch in this series
drivers/pci/controller/dwc/pcie-tegra194.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 1b6b437823d2..2600304522eb 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1885,14 +1885,12 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
val = (upper_32_bits(ep->msi_mem_phys) & MSIX_ADDR_MATCH_HIGH_OFF_MASK);
dw_pcie_writel_dbi(pci, MSIX_ADDR_MATCH_HIGH_OFF, val);
- ret = dw_pcie_ep_init_complete(ep);
+ ret = dw_pcie_ep_init_notify(ep);
if (ret) {
dev_err(dev, "Failed to complete initialization: %d\n", ret);
goto fail_init_complete;
}
- dw_pcie_ep_init_notify(ep);
-
/* Program the private control to allow sending LTR upstream */
if (pcie->of_data->has_ltr_req_fix) {
val = appl_readl(pcie, APPL_LTR_MSG_2);
--
2.17.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH V5 0/3] PCI: designware-ep: Fix DBI access before core init
2022-10-13 17:57 [PATCH V5 0/3] PCI: designware-ep: Fix DBI access before core init Vidya Sagar
` (2 preceding siblings ...)
2022-10-13 17:57 ` [PATCH V5 3/3] PCI: tegra194: " Vidya Sagar
@ 2022-10-14 6:10 ` Manivannan Sadhasivam
2023-02-14 13:03 ` Manivannan Sadhasivam
4 siblings, 0 replies; 13+ messages in thread
From: Manivannan Sadhasivam @ 2022-10-14 6:10 UTC (permalink / raw)
To: Vidya Sagar
Cc: jingoohan1, gustavo.pimentel, lpieralisi, robh, kw, bhelgaas,
mani, Sergey.Semin, dmitry.baryshkov, linmq006, ffclaire1224,
thierry.reding, jonathanh, linux-pci, linux-arm-msm,
linux-kernel, kthota, mmaddireddy, sagar.tv
Hi Vidya,
On Thu, Oct 13, 2022 at 11:27:09PM +0530, Vidya Sagar wrote:
> This series attempts to fix the issue with core register (Ex:- DBI) accesses
> causing system hang issues in platforms where there is a dependency on the
> availability of PCIe Reference clock from the host for their core
> initialization.
> This series is verified on Tegra194 & Tegra234 platforms.
>
> Manivannan, could you please verify on qcom platforms?
>
Currently I'm on paternity leave this week and next. Will test/review the latest
version once I'm back.
Thanks,
Mani
> V5:
> * Addressed review comments from Bjorn
> * Changed dw_pcie_ep_init_complete() to dw_pcie_ep_init_late()
> * Skipped memory allocation if done already. This is to avoid freeing and then
> allocating again during PERST# toggles from the host.
>
> V4:
> * Addressed review comments from Bjorn and Manivannan
> * Added .ep_init_late() ops
> * Added patches to refactor code in qcom and tegra platforms
>
> Vidya Sagar (3):
> PCI: designware-ep: Fix DBI access before core init
> PCI: qcom-ep: Refactor EP initialization completion
> PCI: tegra194: Refactor EP initialization completion
>
> .../pci/controller/dwc/pcie-designware-ep.c | 125 +++++++++++-------
> drivers/pci/controller/dwc/pcie-designware.h | 10 +-
> drivers/pci/controller/dwc/pcie-qcom-ep.c | 27 ++--
> drivers/pci/controller/dwc/pcie-tegra194.c | 4 +-
> 4 files changed, 97 insertions(+), 69 deletions(-)
>
> --
> 2.17.1
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH V5 1/3] PCI: designware-ep: Fix DBI access before core init
2022-10-13 17:57 ` [PATCH V5 1/3] " Vidya Sagar
@ 2022-10-15 22:00 ` Han Jingoo
2022-10-26 5:10 ` Manivannan Sadhasivam
1 sibling, 0 replies; 13+ messages in thread
From: Han Jingoo @ 2022-10-15 22:00 UTC (permalink / raw)
To: Vidya Sagar
Cc: gustavo.pimentel, lpieralisi, robh, kw, bhelgaas, Sergey.Semin,
dmitry.baryshkov, linmq006, ffclaire1224, thierry.reding,
jonathanh, mani, linux-pci, linux-arm-msm, linux-kernel, kthota,
mmaddireddy, sagar.tv
On Thu, Oct 13, 2022 Vidya Sagar <vidyas@nvidia.com> wrote:
>
> Platforms that cannot support their core initialization without the
> reference clock from the host, implement the feature 'core_init_notifier'
> to indicate the DesignWare sub-system about when their core is getting
> initialized. Any accesses to the core (Ex:- DBI) would the core being
> ready result in system hang in such systems (Ex:- tegra194).
> This patch moves any access to the core to dw_pcie_ep_init_complete() API
> which is effectively called only after the core initialization.
> It also introduces .ep_init_late() ops hook to be used for any post init
> work that platform drivers may have to do.
>
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> ---
> V5:
> * Changed dw_pcie_ep_init_complete() to dw_pcie_ep_init_late()
> * Skipped memory allocation if done already. This is to avoid freeing and then
> allocating again during PERST# toggles from the host.
>
> V4:
> * Addressed review comments from Bjorn and Manivannan
> * Moved dw_pcie_ep_init_complete() inside dw_pcie_ep_init_notify()
> * Added .ep_init_late() ops to perform late init tasks
>
> .../pci/controller/dwc/pcie-designware-ep.c | 125 +++++++++++-------
> drivers/pci/controller/dwc/pcie-designware.h | 10 +-
> 2 files changed, 80 insertions(+), 55 deletions(-)
Acked-by: Jingoo Han <jingoohan1@gmail.com>
The function name 'dw_pcie_ep_init_late' looks clear to me. Also,
commit messages
and comments are understandable. So, I am ok with the patches, but I also think
that we need to wait for Manivannan's Tested-by on qcom platforms.
Best regards,
Jingoo Han
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index 83ddb190292e..f300ea2f7bf7 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -23,14 +23,6 @@ void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
> }
> EXPORT_SYMBOL_GPL(dw_pcie_ep_linkup);
>
> -void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep)
> -{
> - struct pci_epc *epc = ep->epc;
> -
> - pci_epc_init_notify(epc);
> -}
> -EXPORT_SYMBOL_GPL(dw_pcie_ep_init_notify);
> -
> struct dw_pcie_ep_func *
> dw_pcie_ep_get_func_from_ep(struct dw_pcie_ep *ep, u8 func_no)
> {
> @@ -640,12 +632,17 @@ static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap)
> return 0;
> }
>
> -int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
> +static int dw_pcie_ep_init_late(struct dw_pcie_ep *ep)
> {
> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> + struct dw_pcie_ep_func *ep_func;
> + struct device *dev = pci->dev;
> + struct pci_epc *epc = ep->epc;
> unsigned int offset;
> unsigned int nbars;
> u8 hdr_type;
> + u8 func_no;
> + void *addr;
> u32 reg;
> int i;
>
> @@ -658,6 +655,51 @@ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
> return -EIO;
> }
>
> + dw_pcie_version_detect(pci);
> +
> + dw_pcie_iatu_detect(pci);
> +
> + if (!ep->ib_window_map) {
> + ep->ib_window_map = devm_bitmap_zalloc(dev, pci->num_ib_windows,
> + GFP_KERNEL);
> + if (!ep->ib_window_map)
> + return -ENOMEM;
> + }
> +
> + if (!ep->ob_window_map) {
> + ep->ob_window_map = devm_bitmap_zalloc(dev, pci->num_ob_windows,
> + GFP_KERNEL);
> + if (!ep->ob_window_map)
> + return -ENOMEM;
> + }
> +
> + if (!ep->outbound_addr) {
> + addr = devm_kcalloc(dev, pci->num_ob_windows, sizeof(phys_addr_t),
> + GFP_KERNEL);
> + if (!addr)
> + return -ENOMEM;
> + ep->outbound_addr = addr;
> + }
> +
> + for (func_no = 0; func_no < epc->max_functions; func_no++) {
> +
> + ep_func = dw_pcie_ep_get_func_from_ep(ep, func_no);
> + if (ep_func)
> + continue;
> +
> + ep_func = devm_kzalloc(dev, sizeof(*ep_func), GFP_KERNEL);
> + if (!ep_func)
> + return -ENOMEM;
> +
> + ep_func->func_no = func_no;
> + ep_func->msi_cap = dw_pcie_ep_find_capability(ep, func_no,
> + PCI_CAP_ID_MSI);
> + ep_func->msix_cap = dw_pcie_ep_find_capability(ep, func_no,
> + PCI_CAP_ID_MSIX);
> +
> + list_add_tail(&ep_func->list, &ep->func_list);
> + }
> +
> offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR);
>
> dw_pcie_dbi_ro_wr_en(pci);
> @@ -676,13 +718,28 @@ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
>
> return 0;
> }
> -EXPORT_SYMBOL_GPL(dw_pcie_ep_init_complete);
> +
> +int dw_pcie_ep_init_notify(struct dw_pcie_ep *ep)
> +{
> + struct pci_epc *epc = ep->epc;
> + int ret;
> +
> + ret = dw_pcie_ep_init_late(ep);
> + if (ret)
> + return ret;
> +
> + if (ep->ops->ep_init_late)
> + ep->ops->ep_init_late(ep);
> +
> + pci_epc_init_notify(epc);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(dw_pcie_ep_init_notify);
>
> int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> {
> int ret;
> - void *addr;
> - u8 func_no;
> struct resource *res;
> struct pci_epc *epc;
> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> @@ -690,7 +747,6 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> struct platform_device *pdev = to_platform_device(dev);
> struct device_node *np = dev->of_node;
> const struct pci_epc_features *epc_features;
> - struct dw_pcie_ep_func *ep_func;
>
> INIT_LIST_HEAD(&ep->func_list);
>
> @@ -719,26 +775,6 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> ep->phys_base = res->start;
> ep->addr_size = resource_size(res);
>
> - dw_pcie_version_detect(pci);
> -
> - dw_pcie_iatu_detect(pci);
> -
> - ep->ib_window_map = devm_bitmap_zalloc(dev, pci->num_ib_windows,
> - GFP_KERNEL);
> - if (!ep->ib_window_map)
> - return -ENOMEM;
> -
> - ep->ob_window_map = devm_bitmap_zalloc(dev, pci->num_ob_windows,
> - GFP_KERNEL);
> - if (!ep->ob_window_map)
> - return -ENOMEM;
> -
> - addr = devm_kcalloc(dev, pci->num_ob_windows, sizeof(phys_addr_t),
> - GFP_KERNEL);
> - if (!addr)
> - return -ENOMEM;
> - ep->outbound_addr = addr;
> -
> if (pci->link_gen < 1)
> pci->link_gen = of_pci_get_max_link_speed(np);
>
> @@ -755,20 +791,6 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> if (ret < 0)
> epc->max_functions = 1;
>
> - for (func_no = 0; func_no < epc->max_functions; func_no++) {
> - ep_func = devm_kzalloc(dev, sizeof(*ep_func), GFP_KERNEL);
> - if (!ep_func)
> - return -ENOMEM;
> -
> - ep_func->func_no = func_no;
> - ep_func->msi_cap = dw_pcie_ep_find_capability(ep, func_no,
> - PCI_CAP_ID_MSI);
> - ep_func->msix_cap = dw_pcie_ep_find_capability(ep, func_no,
> - PCI_CAP_ID_MSIX);
> -
> - list_add_tail(&ep_func->list, &ep->func_list);
> - }
> -
> if (ep->ops->ep_init)
> ep->ops->ep_init(ep);
>
> @@ -793,7 +815,14 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> return 0;
> }
>
> - ret = dw_pcie_ep_init_complete(ep);
> + /*
> + * NOTE:- Avoid accessing the hardware (Ex:- DBI space) before this
> + * step as platforms that implement 'core_init_notifier' feature may
> + * not have the hardware ready (i.e. core initialized) for access
> + * (Ex: tegra194). Any hardware access on such platforms result
> + * in system hard hang.
> + */
> + ret = dw_pcie_ep_init_late(ep);
> if (ret)
> goto err_free_epc_mem;
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 45fcdfc8c035..7252513956b7 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -253,6 +253,7 @@ struct dw_pcie_rp {
>
> struct dw_pcie_ep_ops {
> void (*ep_init)(struct dw_pcie_ep *ep);
> + void (*ep_init_late)(struct dw_pcie_ep *ep);
> int (*raise_irq)(struct dw_pcie_ep *ep, u8 func_no,
> enum pci_epc_irq_type type, u16 interrupt_num);
> const struct pci_epc_features* (*get_features)(struct dw_pcie_ep *ep);
> @@ -467,8 +468,7 @@ static inline void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus,
> #ifdef CONFIG_PCIE_DW_EP
> void dw_pcie_ep_linkup(struct dw_pcie_ep *ep);
> int dw_pcie_ep_init(struct dw_pcie_ep *ep);
> -int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep);
> -void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep);
> +int dw_pcie_ep_init_notify(struct dw_pcie_ep *ep);
> void dw_pcie_ep_exit(struct dw_pcie_ep *ep);
> int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no);
> int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
> @@ -490,15 +490,11 @@ static inline int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> return 0;
> }
>
> -static inline int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
> +static inline int dw_pcie_ep_init_notify(struct dw_pcie_ep *ep)
> {
> return 0;
> }
>
> -static inline void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep)
> -{
> -}
> -
> static inline void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
> {
> }
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH V5 1/3] PCI: designware-ep: Fix DBI access before core init
2022-10-13 17:57 ` [PATCH V5 1/3] " Vidya Sagar
2022-10-15 22:00 ` Han Jingoo
@ 2022-10-26 5:10 ` Manivannan Sadhasivam
1 sibling, 0 replies; 13+ messages in thread
From: Manivannan Sadhasivam @ 2022-10-26 5:10 UTC (permalink / raw)
To: Vidya Sagar
Cc: jingoohan1, gustavo.pimentel, lpieralisi, robh, kw, bhelgaas,
mani, Sergey.Semin, dmitry.baryshkov, linmq006, ffclaire1224,
thierry.reding, jonathanh, linux-pci, linux-arm-msm,
linux-kernel, kthota, mmaddireddy, sagar.tv
On Thu, Oct 13, 2022 at 11:27:10PM +0530, Vidya Sagar wrote:
> Platforms that cannot support their core initialization without the
> reference clock from the host, implement the feature 'core_init_notifier'
> to indicate the DesignWare sub-system about when their core is getting
> initialized. Any accesses to the core (Ex:- DBI) would the core being
> ready result in system hang in such systems (Ex:- tegra194).
> This patch moves any access to the core to dw_pcie_ep_init_complete() API
dw_pcie_ep_init_complete() got renamed to dw_pcie_ep_init_late()
> which is effectively called only after the core initialization.
> It also introduces .ep_init_late() ops hook to be used for any post init
> work that platform drivers may have to do.
>
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> ---
> V5:
> * Changed dw_pcie_ep_init_complete() to dw_pcie_ep_init_late()
> * Skipped memory allocation if done already. This is to avoid freeing and then
> allocating again during PERST# toggles from the host.
>
> V4:
> * Addressed review comments from Bjorn and Manivannan
> * Moved dw_pcie_ep_init_complete() inside dw_pcie_ep_init_notify()
> * Added .ep_init_late() ops to perform late init tasks
>
> .../pci/controller/dwc/pcie-designware-ep.c | 125 +++++++++++-------
> drivers/pci/controller/dwc/pcie-designware.h | 10 +-
> 2 files changed, 80 insertions(+), 55 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index 83ddb190292e..f300ea2f7bf7 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
[...]
> +int dw_pcie_ep_init_notify(struct dw_pcie_ep *ep)
> +{
> + struct pci_epc *epc = ep->epc;
> + int ret;
> +
> + ret = dw_pcie_ep_init_late(ep);
> + if (ret)
> + return ret;
> +
> + if (ep->ops->ep_init_late)
> + ep->ops->ep_init_late(ep);
I think you introduced this callback for the sake of Qcom driver I believe.
But it is not really required. I'll share more comments in patch 2/3.
Thanks,
Mani
> +
> + pci_epc_init_notify(epc);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(dw_pcie_ep_init_notify);
>
> int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> {
> int ret;
> - void *addr;
> - u8 func_no;
> struct resource *res;
> struct pci_epc *epc;
> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> @@ -690,7 +747,6 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> struct platform_device *pdev = to_platform_device(dev);
> struct device_node *np = dev->of_node;
> const struct pci_epc_features *epc_features;
> - struct dw_pcie_ep_func *ep_func;
>
> INIT_LIST_HEAD(&ep->func_list);
>
> @@ -719,26 +775,6 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> ep->phys_base = res->start;
> ep->addr_size = resource_size(res);
>
> - dw_pcie_version_detect(pci);
> -
> - dw_pcie_iatu_detect(pci);
> -
> - ep->ib_window_map = devm_bitmap_zalloc(dev, pci->num_ib_windows,
> - GFP_KERNEL);
> - if (!ep->ib_window_map)
> - return -ENOMEM;
> -
> - ep->ob_window_map = devm_bitmap_zalloc(dev, pci->num_ob_windows,
> - GFP_KERNEL);
> - if (!ep->ob_window_map)
> - return -ENOMEM;
> -
> - addr = devm_kcalloc(dev, pci->num_ob_windows, sizeof(phys_addr_t),
> - GFP_KERNEL);
> - if (!addr)
> - return -ENOMEM;
> - ep->outbound_addr = addr;
> -
> if (pci->link_gen < 1)
> pci->link_gen = of_pci_get_max_link_speed(np);
>
> @@ -755,20 +791,6 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> if (ret < 0)
> epc->max_functions = 1;
>
> - for (func_no = 0; func_no < epc->max_functions; func_no++) {
> - ep_func = devm_kzalloc(dev, sizeof(*ep_func), GFP_KERNEL);
> - if (!ep_func)
> - return -ENOMEM;
> -
> - ep_func->func_no = func_no;
> - ep_func->msi_cap = dw_pcie_ep_find_capability(ep, func_no,
> - PCI_CAP_ID_MSI);
> - ep_func->msix_cap = dw_pcie_ep_find_capability(ep, func_no,
> - PCI_CAP_ID_MSIX);
> -
> - list_add_tail(&ep_func->list, &ep->func_list);
> - }
> -
> if (ep->ops->ep_init)
> ep->ops->ep_init(ep);
>
> @@ -793,7 +815,14 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> return 0;
> }
>
> - ret = dw_pcie_ep_init_complete(ep);
> + /*
> + * NOTE:- Avoid accessing the hardware (Ex:- DBI space) before this
> + * step as platforms that implement 'core_init_notifier' feature may
> + * not have the hardware ready (i.e. core initialized) for access
> + * (Ex: tegra194). Any hardware access on such platforms result
> + * in system hard hang.
> + */
> + ret = dw_pcie_ep_init_late(ep);
> if (ret)
> goto err_free_epc_mem;
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 45fcdfc8c035..7252513956b7 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -253,6 +253,7 @@ struct dw_pcie_rp {
>
> struct dw_pcie_ep_ops {
> void (*ep_init)(struct dw_pcie_ep *ep);
> + void (*ep_init_late)(struct dw_pcie_ep *ep);
> int (*raise_irq)(struct dw_pcie_ep *ep, u8 func_no,
> enum pci_epc_irq_type type, u16 interrupt_num);
> const struct pci_epc_features* (*get_features)(struct dw_pcie_ep *ep);
> @@ -467,8 +468,7 @@ static inline void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus,
> #ifdef CONFIG_PCIE_DW_EP
> void dw_pcie_ep_linkup(struct dw_pcie_ep *ep);
> int dw_pcie_ep_init(struct dw_pcie_ep *ep);
> -int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep);
> -void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep);
> +int dw_pcie_ep_init_notify(struct dw_pcie_ep *ep);
> void dw_pcie_ep_exit(struct dw_pcie_ep *ep);
> int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no);
> int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
> @@ -490,15 +490,11 @@ static inline int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> return 0;
> }
>
> -static inline int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
> +static inline int dw_pcie_ep_init_notify(struct dw_pcie_ep *ep)
> {
> return 0;
> }
>
> -static inline void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep)
> -{
> -}
> -
> static inline void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
> {
> }
> --
> 2.17.1
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH V5 2/3] PCI: qcom-ep: Refactor EP initialization completion
2022-10-13 17:57 ` [PATCH V5 2/3] PCI: qcom-ep: Refactor EP initialization completion Vidya Sagar
@ 2022-10-26 5:30 ` Manivannan Sadhasivam
0 siblings, 0 replies; 13+ messages in thread
From: Manivannan Sadhasivam @ 2022-10-26 5:30 UTC (permalink / raw)
To: Vidya Sagar
Cc: jingoohan1, gustavo.pimentel, lpieralisi, robh, kw, bhelgaas,
Sergey.Semin, dmitry.baryshkov, linmq006, ffclaire1224,
thierry.reding, jonathanh, linux-pci, linux-arm-msm,
linux-kernel, kthota, mmaddireddy, sagar.tv
On Thu, Oct 13, 2022 at 11:27:11PM +0530, Vidya Sagar wrote:
> Move the post initialization code to .ep_init_late() call back and call
> only dw_pcie_ep_init_notify() which internally takes care of calling
> dw_pcie_ep_init_complete().
>
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> ---
> V5:
> * None
>
> V4:
> * New patch in this series
>
> drivers/pci/controller/dwc/pcie-qcom-ep.c | 27 ++++++++++++++---------
> 1 file changed, 16 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> index e33eb3871309..c418b20042aa 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> @@ -361,22 +361,12 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci)
> PARF_INT_ALL_LINK_UP;
> writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_MASK);
>
> - ret = dw_pcie_ep_init_complete(&pcie_ep->pci.ep);
> + ret = dw_pcie_ep_init_notify(&pcie_ep->pci.ep);
> if (ret) {
> dev_err(dev, "Failed to complete initialization: %d\n", ret);
> goto err_disable_resources;
> }
>
> - /*
> - * The physical address of the MMIO region which is exposed as the BAR
> - * should be written to MHI BASE registers.
> - */
> - writel_relaxed(pcie_ep->mmio_res->start,
> - pcie_ep->parf + PARF_MHI_BASE_ADDR_LOWER);
> - writel_relaxed(0, pcie_ep->parf + PARF_MHI_BASE_ADDR_UPPER);
Writes to the MHI base addresses are required before starting LTSSM and not
necessarily before core_init notifier. So you could just leave this code here
and get rid of .ep_init_late() callback.
And you should also rebase the series on top of v6.1-rcX as I've added few more
code in this function.
Thanks,
Mani
> -
> - dw_pcie_ep_init_notify(&pcie_ep->pci.ep);
> -
> /* Enable LTSSM */
> val = readl_relaxed(pcie_ep->parf + PARF_LTSSM);
> val |= BIT(8);
> @@ -643,8 +633,23 @@ static void qcom_pcie_ep_init(struct dw_pcie_ep *ep)
> dw_pcie_ep_reset_bar(pci, bar);
> }
>
> +static void qcom_pcie_ep_init_late(struct dw_pcie_ep *ep)
> +{
> + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> + struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
> +
> + /*
> + * The physical address of the MMIO region which is exposed as the BAR
> + * should be written to MHI BASE registers.
> + */
> + writel_relaxed(pcie_ep->mmio_res->start,
> + pcie_ep->parf + PARF_MHI_BASE_ADDR_LOWER);
> + writel_relaxed(0, pcie_ep->parf + PARF_MHI_BASE_ADDR_UPPER);
> +}
> +
> static const struct dw_pcie_ep_ops pci_ep_ops = {
> .ep_init = qcom_pcie_ep_init,
> + .ep_init_late = qcom_pcie_ep_init_late,
> .raise_irq = qcom_pcie_ep_raise_irq,
> .get_features = qcom_pcie_epc_get_features,
> };
> --
> 2.17.1
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH V5 0/3] PCI: designware-ep: Fix DBI access before core init
2022-10-13 17:57 [PATCH V5 0/3] PCI: designware-ep: Fix DBI access before core init Vidya Sagar
` (3 preceding siblings ...)
2022-10-14 6:10 ` [PATCH V5 0/3] PCI: designware-ep: Fix DBI access before core init Manivannan Sadhasivam
@ 2023-02-14 13:03 ` Manivannan Sadhasivam
2023-02-14 13:57 ` Vidya Sagar
4 siblings, 1 reply; 13+ messages in thread
From: Manivannan Sadhasivam @ 2023-02-14 13:03 UTC (permalink / raw)
To: Vidya Sagar
Cc: jingoohan1, gustavo.pimentel, lpieralisi, robh, kw, bhelgaas,
mani, Sergey.Semin, dmitry.baryshkov, linmq006, ffclaire1224,
thierry.reding, jonathanh, linux-pci, linux-arm-msm,
linux-kernel, kthota, mmaddireddy, sagar.tv
On Thu, Oct 13, 2022 at 11:27:09PM +0530, Vidya Sagar wrote:
> This series attempts to fix the issue with core register (Ex:- DBI) accesses
> causing system hang issues in platforms where there is a dependency on the
> availability of PCIe Reference clock from the host for their core
> initialization.
> This series is verified on Tegra194 & Tegra234 platforms.
>
> Manivannan, could you please verify on qcom platforms?
>
Vidya, any plan to respin this series? The EPC rework series is now merged for
v6.3.
Thanks,
Mani
> V5:
> * Addressed review comments from Bjorn
> * Changed dw_pcie_ep_init_complete() to dw_pcie_ep_init_late()
> * Skipped memory allocation if done already. This is to avoid freeing and then
> allocating again during PERST# toggles from the host.
>
> V4:
> * Addressed review comments from Bjorn and Manivannan
> * Added .ep_init_late() ops
> * Added patches to refactor code in qcom and tegra platforms
>
> Vidya Sagar (3):
> PCI: designware-ep: Fix DBI access before core init
> PCI: qcom-ep: Refactor EP initialization completion
> PCI: tegra194: Refactor EP initialization completion
>
> .../pci/controller/dwc/pcie-designware-ep.c | 125 +++++++++++-------
> drivers/pci/controller/dwc/pcie-designware.h | 10 +-
> drivers/pci/controller/dwc/pcie-qcom-ep.c | 27 ++--
> drivers/pci/controller/dwc/pcie-tegra194.c | 4 +-
> 4 files changed, 97 insertions(+), 69 deletions(-)
>
> --
> 2.17.1
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH V5 0/3] PCI: designware-ep: Fix DBI access before core init
2023-02-14 13:03 ` Manivannan Sadhasivam
@ 2023-02-14 13:57 ` Vidya Sagar
2023-03-07 15:18 ` Manivannan Sadhasivam
0 siblings, 1 reply; 13+ messages in thread
From: Vidya Sagar @ 2023-02-14 13:57 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: jingoohan1, gustavo.pimentel, lpieralisi, robh, kw, bhelgaas,
Sergey.Semin, dmitry.baryshkov, linmq006, ffclaire1224,
thierry.reding, jonathanh, linux-pci, linux-arm-msm,
linux-kernel, kthota, mmaddireddy, sagar.tv
On 2/14/2023 6:33 PM, Manivannan Sadhasivam wrote:
> External email: Use caution opening links or attachments
>
>
> On Thu, Oct 13, 2022 at 11:27:09PM +0530, Vidya Sagar wrote:
>> This series attempts to fix the issue with core register (Ex:- DBI) accesses
>> causing system hang issues in platforms where there is a dependency on the
>> availability of PCIe Reference clock from the host for their core
>> initialization.
>> This series is verified on Tegra194 & Tegra234 platforms.
>>
>> Manivannan, could you please verify on qcom platforms?
>>
>
> Vidya, any plan to respin this series? The EPC rework series is now merged for
> v6.3.
Yes. I'll send an updated series soon.
Currently, I'm observing some regression with linux-next on Tegra
platform for endpoint mode. I'll post the patches as soon as that is
resolved.
Thanks,
Vidya Sagar
>
> Thanks,
> Mani
>
>> V5:
>> * Addressed review comments from Bjorn
>> * Changed dw_pcie_ep_init_complete() to dw_pcie_ep_init_late()
>> * Skipped memory allocation if done already. This is to avoid freeing and then
>> allocating again during PERST# toggles from the host.
>>
>> V4:
>> * Addressed review comments from Bjorn and Manivannan
>> * Added .ep_init_late() ops
>> * Added patches to refactor code in qcom and tegra platforms
>>
>> Vidya Sagar (3):
>> PCI: designware-ep: Fix DBI access before core init
>> PCI: qcom-ep: Refactor EP initialization completion
>> PCI: tegra194: Refactor EP initialization completion
>>
>> .../pci/controller/dwc/pcie-designware-ep.c | 125 +++++++++++-------
>> drivers/pci/controller/dwc/pcie-designware.h | 10 +-
>> drivers/pci/controller/dwc/pcie-qcom-ep.c | 27 ++--
>> drivers/pci/controller/dwc/pcie-tegra194.c | 4 +-
>> 4 files changed, 97 insertions(+), 69 deletions(-)
>>
>> --
>> 2.17.1
>>
>
> --
> மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH V5 0/3] PCI: designware-ep: Fix DBI access before core init
2023-02-14 13:57 ` Vidya Sagar
@ 2023-03-07 15:18 ` Manivannan Sadhasivam
2023-05-15 7:40 ` Manivannan Sadhasivam
2023-08-25 12:38 ` Manivannan Sadhasivam
0 siblings, 2 replies; 13+ messages in thread
From: Manivannan Sadhasivam @ 2023-03-07 15:18 UTC (permalink / raw)
To: Vidya Sagar
Cc: Manivannan Sadhasivam, jingoohan1, gustavo.pimentel, lpieralisi,
robh, kw, bhelgaas, Sergey.Semin, dmitry.baryshkov, linmq006,
ffclaire1224, thierry.reding, jonathanh, linux-pci,
linux-arm-msm, linux-kernel, kthota, mmaddireddy, sagar.tv
On Tue, Feb 14, 2023 at 07:27:54PM +0530, Vidya Sagar wrote:
>
>
> On 2/14/2023 6:33 PM, Manivannan Sadhasivam wrote:
> > External email: Use caution opening links or attachments
> >
> >
> > On Thu, Oct 13, 2022 at 11:27:09PM +0530, Vidya Sagar wrote:
> > > This series attempts to fix the issue with core register (Ex:- DBI) accesses
> > > causing system hang issues in platforms where there is a dependency on the
> > > availability of PCIe Reference clock from the host for their core
> > > initialization.
> > > This series is verified on Tegra194 & Tegra234 platforms.
> > >
> > > Manivannan, could you please verify on qcom platforms?
> > >
> >
> > Vidya, any plan to respin this series? The EPC rework series is now merged for
> > v6.3.
>
> Yes. I'll send an updated series soon.
> Currently, I'm observing some regression with linux-next on Tegra platform
> for endpoint mode. I'll post the patches as soon as that is resolved.
>
Ping!
Thanks,
Mani
> Thanks,
> Vidya Sagar
>
> >
> > Thanks,
> > Mani
> >
> > > V5:
> > > * Addressed review comments from Bjorn
> > > * Changed dw_pcie_ep_init_complete() to dw_pcie_ep_init_late()
> > > * Skipped memory allocation if done already. This is to avoid freeing and then
> > > allocating again during PERST# toggles from the host.
> > >
> > > V4:
> > > * Addressed review comments from Bjorn and Manivannan
> > > * Added .ep_init_late() ops
> > > * Added patches to refactor code in qcom and tegra platforms
> > >
> > > Vidya Sagar (3):
> > > PCI: designware-ep: Fix DBI access before core init
> > > PCI: qcom-ep: Refactor EP initialization completion
> > > PCI: tegra194: Refactor EP initialization completion
> > >
> > > .../pci/controller/dwc/pcie-designware-ep.c | 125 +++++++++++-------
> > > drivers/pci/controller/dwc/pcie-designware.h | 10 +-
> > > drivers/pci/controller/dwc/pcie-qcom-ep.c | 27 ++--
> > > drivers/pci/controller/dwc/pcie-tegra194.c | 4 +-
> > > 4 files changed, 97 insertions(+), 69 deletions(-)
> > >
> > > --
> > > 2.17.1
> > >
> >
> > --
> > மணிவண்ணன் சதாசிவம்
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH V5 0/3] PCI: designware-ep: Fix DBI access before core init
2023-03-07 15:18 ` Manivannan Sadhasivam
@ 2023-05-15 7:40 ` Manivannan Sadhasivam
2023-08-25 12:38 ` Manivannan Sadhasivam
1 sibling, 0 replies; 13+ messages in thread
From: Manivannan Sadhasivam @ 2023-05-15 7:40 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Vidya Sagar, jingoohan1, gustavo.pimentel, lpieralisi, robh, kw,
bhelgaas, Sergey.Semin, dmitry.baryshkov, linmq006, ffclaire1224,
thierry.reding, jonathanh, linux-pci, linux-arm-msm,
linux-kernel, kthota, mmaddireddy, sagar.tv
On Tue, Mar 07, 2023 at 08:48:39PM +0530, Manivannan Sadhasivam wrote:
> On Tue, Feb 14, 2023 at 07:27:54PM +0530, Vidya Sagar wrote:
> >
> >
> > On 2/14/2023 6:33 PM, Manivannan Sadhasivam wrote:
> > > External email: Use caution opening links or attachments
> > >
> > >
> > > On Thu, Oct 13, 2022 at 11:27:09PM +0530, Vidya Sagar wrote:
> > > > This series attempts to fix the issue with core register (Ex:- DBI) accesses
> > > > causing system hang issues in platforms where there is a dependency on the
> > > > availability of PCIe Reference clock from the host for their core
> > > > initialization.
> > > > This series is verified on Tegra194 & Tegra234 platforms.
> > > >
> > > > Manivannan, could you please verify on qcom platforms?
> > > >
> > >
> > > Vidya, any plan to respin this series? The EPC rework series is now merged for
> > > v6.3.
> >
> > Yes. I'll send an updated series soon.
> > Currently, I'm observing some regression with linux-next on Tegra platform
> > for endpoint mode. I'll post the patches as soon as that is resolved.
> >
>
> Ping!
>
Ping again.
- Mani
> Thanks,
> Mani
>
> > Thanks,
> > Vidya Sagar
> >
> > >
> > > Thanks,
> > > Mani
> > >
> > > > V5:
> > > > * Addressed review comments from Bjorn
> > > > * Changed dw_pcie_ep_init_complete() to dw_pcie_ep_init_late()
> > > > * Skipped memory allocation if done already. This is to avoid freeing and then
> > > > allocating again during PERST# toggles from the host.
> > > >
> > > > V4:
> > > > * Addressed review comments from Bjorn and Manivannan
> > > > * Added .ep_init_late() ops
> > > > * Added patches to refactor code in qcom and tegra platforms
> > > >
> > > > Vidya Sagar (3):
> > > > PCI: designware-ep: Fix DBI access before core init
> > > > PCI: qcom-ep: Refactor EP initialization completion
> > > > PCI: tegra194: Refactor EP initialization completion
> > > >
> > > > .../pci/controller/dwc/pcie-designware-ep.c | 125 +++++++++++-------
> > > > drivers/pci/controller/dwc/pcie-designware.h | 10 +-
> > > > drivers/pci/controller/dwc/pcie-qcom-ep.c | 27 ++--
> > > > drivers/pci/controller/dwc/pcie-tegra194.c | 4 +-
> > > > 4 files changed, 97 insertions(+), 69 deletions(-)
> > > >
> > > > --
> > > > 2.17.1
> > > >
> > >
> > > --
> > > மணிவண்ணன் சதாசிவம்
>
> --
> மணிவண்ணன் சதாசிவம்
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH V5 0/3] PCI: designware-ep: Fix DBI access before core init
2023-03-07 15:18 ` Manivannan Sadhasivam
2023-05-15 7:40 ` Manivannan Sadhasivam
@ 2023-08-25 12:38 ` Manivannan Sadhasivam
1 sibling, 0 replies; 13+ messages in thread
From: Manivannan Sadhasivam @ 2023-08-25 12:38 UTC (permalink / raw)
To: Vidya Sagar
Cc: jingoohan1, gustavo.pimentel, lpieralisi, robh, kw, bhelgaas,
Sergey.Semin, dmitry.baryshkov, linmq006, ffclaire1224,
thierry.reding, jonathanh, linux-pci, linux-arm-msm,
linux-kernel, kthota, mmaddireddy, sagar.tv
On Tue, Mar 07, 2023 at 08:48:39PM +0530, Manivannan Sadhasivam wrote:
> On Tue, Feb 14, 2023 at 07:27:54PM +0530, Vidya Sagar wrote:
> >
> >
> > On 2/14/2023 6:33 PM, Manivannan Sadhasivam wrote:
> > > External email: Use caution opening links or attachments
> > >
> > >
> > > On Thu, Oct 13, 2022 at 11:27:09PM +0530, Vidya Sagar wrote:
> > > > This series attempts to fix the issue with core register (Ex:- DBI) accesses
> > > > causing system hang issues in platforms where there is a dependency on the
> > > > availability of PCIe Reference clock from the host for their core
> > > > initialization.
> > > > This series is verified on Tegra194 & Tegra234 platforms.
> > > >
> > > > Manivannan, could you please verify on qcom platforms?
> > > >
> > >
> > > Vidya, any plan to respin this series? The EPC rework series is now merged for
> > > v6.3.
> >
> > Yes. I'll send an updated series soon.
> > Currently, I'm observing some regression with linux-next on Tegra platform
> > for endpoint mode. I'll post the patches as soon as that is resolved.
> >
>
> Ping!
>
Vidya, are you planning to continue working on this series? If you do not have
time, please let me know.
- Mani
> Thanks,
> Mani
>
> > Thanks,
> > Vidya Sagar
> >
> > >
> > > Thanks,
> > > Mani
> > >
> > > > V5:
> > > > * Addressed review comments from Bjorn
> > > > * Changed dw_pcie_ep_init_complete() to dw_pcie_ep_init_late()
> > > > * Skipped memory allocation if done already. This is to avoid freeing and then
> > > > allocating again during PERST# toggles from the host.
> > > >
> > > > V4:
> > > > * Addressed review comments from Bjorn and Manivannan
> > > > * Added .ep_init_late() ops
> > > > * Added patches to refactor code in qcom and tegra platforms
> > > >
> > > > Vidya Sagar (3):
> > > > PCI: designware-ep: Fix DBI access before core init
> > > > PCI: qcom-ep: Refactor EP initialization completion
> > > > PCI: tegra194: Refactor EP initialization completion
> > > >
> > > > .../pci/controller/dwc/pcie-designware-ep.c | 125 +++++++++++-------
> > > > drivers/pci/controller/dwc/pcie-designware.h | 10 +-
> > > > drivers/pci/controller/dwc/pcie-qcom-ep.c | 27 ++--
> > > > drivers/pci/controller/dwc/pcie-tegra194.c | 4 +-
> > > > 4 files changed, 97 insertions(+), 69 deletions(-)
> > > >
> > > > --
> > > > 2.17.1
> > > >
> > >
> > > --
> > > மணிவண்ணன் சதாசிவம்
>
> --
> மணிவண்ணன் சதாசிவம்
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2023-08-25 12:39 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-10-13 17:57 [PATCH V5 0/3] PCI: designware-ep: Fix DBI access before core init Vidya Sagar
2022-10-13 17:57 ` [PATCH V5 1/3] " Vidya Sagar
2022-10-15 22:00 ` Han Jingoo
2022-10-26 5:10 ` Manivannan Sadhasivam
2022-10-13 17:57 ` [PATCH V5 2/3] PCI: qcom-ep: Refactor EP initialization completion Vidya Sagar
2022-10-26 5:30 ` Manivannan Sadhasivam
2022-10-13 17:57 ` [PATCH V5 3/3] PCI: tegra194: " Vidya Sagar
2022-10-14 6:10 ` [PATCH V5 0/3] PCI: designware-ep: Fix DBI access before core init Manivannan Sadhasivam
2023-02-14 13:03 ` Manivannan Sadhasivam
2023-02-14 13:57 ` Vidya Sagar
2023-03-07 15:18 ` Manivannan Sadhasivam
2023-05-15 7:40 ` Manivannan Sadhasivam
2023-08-25 12:38 ` Manivannan Sadhasivam
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