* [v9 0/8] Add minimal boot support for IPQ5018
@ 2023-06-08 12:21 Sricharan Ramabadhran
2023-06-08 12:21 ` [v9 1/8] dt-bindings: arm64: Add IPQ5018 clock and reset Sricharan Ramabadhran
` (7 more replies)
0 siblings, 8 replies; 13+ messages in thread
From: Sricharan Ramabadhran @ 2023-06-08 12:21 UTC (permalink / raw)
To: agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, ulf.hansson,
linus.walleij, catalin.marinas, will, p.zabel, linux-arm-msm,
devicetree, linux-kernel, linux-mmc, linux-gpio,
linux-arm-kernel, robimarko, krzysztof.kozlowski,
andy.shevchenko, quic_srichara
The IPQ5018 is Qualcomm's 802.11ax SoC for Routers,
Gateways and Access Points.
This series adds minimal board boot support for ipq5018-rdp432-c2 board.
[v9] Change only in patch 2/8
Sorted the headers and cleaned the unwanted ones
Added trailing comma for .parent_hws member
Removed the hunk touching ipq5332 kconfig (unintentionally)
[v8] Changed only in patch 4/8
Fixed Kconfig to add COMPILE_TEST and removed header of.h.
Instead using mod_devicetable.h. Added Linus reviewed-by
[v7] Fixed tz reserved region size in patch 7/8
[v6] Fixed patch [4/8] pinctrl driver for rebase issue.
[v5]
Added Reviewed-by tags from Krzysztof Kozlowski.
Changed patch [6/8] with [1] since its already Acked
Rebased patch [4/8] on top of [2] and fixed other comments
Fixed commit log for patch [7/8]
Fixed comments for patch [2/8]
[1] https://patchwork.kernel.org/project/linux-arm-msm/patch/1678164097-13247-4-git-send-email-quic_mmanikan@quicinc.com/
[2] https://lore.kernel.org/r/1683718725-14869-1-git-send-email-quic_rohiagar@quicinc.com
[v4]
Fixed all comments for clocks, schema, dts
Added Reviewed-by tags.
[v3]
Fixed all comments for clocks, schema fixes
Picked up Reviewed-by from Bjorn for pinctrl driver
[v2]
Fixed all comments and rebased for TOT.
Manikanta Mylavarapu (1):
dt-bindings: scm: Add compatible for IPQ5018
Sricharan Ramabadhran (7):
dt-bindings: arm64: Add IPQ5018 clock and reset
clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018
dt-bindings: pinctrl: qcom: Add support for ipq5018
pinctrl: qcom: Add IPQ5018 pinctrl driver
dt-bindings: qcom: Add ipq5018 bindings
arm64: dts: Add ipq5018 SoC and rdp432-c2 board support
arm64: defconfig: Enable IPQ5018 SoC base configs
.../devicetree/bindings/arm/qcom.yaml | 7 +
.../bindings/clock/qcom,ipq5018-gcc.yaml | 63 +
.../bindings/firmware/qcom,scm.yaml | 1 +
.../bindings/pinctrl/qcom,ipq5018-tlmm.yaml | 127 +
arch/arm64/boot/dts/qcom/Makefile | 1 +
.../arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts | 72 +
arch/arm64/boot/dts/qcom/ipq5018.dtsi | 250 ++
arch/arm64/configs/defconfig | 3 +
drivers/clk/qcom/Kconfig | 8 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gcc-ipq5018.c | 3724 +++++++++++++++++
drivers/pinctrl/qcom/Kconfig | 11 +
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-ipq5018.c | 783 ++++
include/dt-bindings/clock/qcom,gcc-ipq5018.h | 183 +
include/dt-bindings/reset/qcom,gcc-ipq5018.h | 122 +
16 files changed, 5357 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq5018-gcc.yaml
create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq5018-tlmm.yaml
create mode 100644 arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
create mode 100644 arch/arm64/boot/dts/qcom/ipq5018.dtsi
create mode 100644 drivers/clk/qcom/gcc-ipq5018.c
create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq5018.c
create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq5018.h
create mode 100644 include/dt-bindings/reset/qcom,gcc-ipq5018.h
--
2.34.1
^ permalink raw reply [flat|nested] 13+ messages in thread
* [v9 1/8] dt-bindings: arm64: Add IPQ5018 clock and reset
2023-06-08 12:21 [v9 0/8] Add minimal boot support for IPQ5018 Sricharan Ramabadhran
@ 2023-06-08 12:21 ` Sricharan Ramabadhran
2023-06-08 12:21 ` [v9 2/8] clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018 Sricharan Ramabadhran
` (6 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Sricharan Ramabadhran @ 2023-06-08 12:21 UTC (permalink / raw)
To: agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, ulf.hansson,
linus.walleij, catalin.marinas, will, p.zabel, linux-arm-msm,
devicetree, linux-kernel, linux-mmc, linux-gpio,
linux-arm-kernel, robimarko, krzysztof.kozlowski,
andy.shevchenko, quic_srichara
This patch adds support for the global clock controller found on
the IPQ5018 based devices.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Co-developed-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
---
.../bindings/clock/qcom,ipq5018-gcc.yaml | 63 ++++++
include/dt-bindings/clock/qcom,gcc-ipq5018.h | 183 ++++++++++++++++++
include/dt-bindings/reset/qcom,gcc-ipq5018.h | 122 ++++++++++++
3 files changed, 368 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq5018-gcc.yaml
create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq5018.h
create mode 100644 include/dt-bindings/reset/qcom,gcc-ipq5018.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5018-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5018-gcc.yaml
new file mode 100644
index 000000000000..ef84a0c95f7e
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,ipq5018-gcc.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,ipq5018-gcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller on IPQ5018
+
+maintainers:
+ - Sricharan Ramabadhran <quic_srichara@quicinc.com>
+
+description: |
+ Qualcomm global clock control module provides the clocks, resets and power
+ domains on IPQ5018
+
+ See also::
+ include/dt-bindings/clock/qcom,ipq5018-gcc.h
+ include/dt-bindings/reset/qcom,ipq5018-gcc.h
+
+properties:
+ compatible:
+ const: qcom,gcc-ipq5018
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Sleep clock source
+ - description: PCIE20 PHY0 pipe clock source
+ - description: PCIE20 PHY1 pipe clock source
+ - description: USB3 PHY pipe clock source
+ - description: GEPHY RX clock source
+ - description: GEPHY TX clock source
+ - description: UNIPHY RX clock source
+ - description: UNIPHY TX clk source
+
+required:
+ - compatible
+ - clocks
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ clock-controller@1800000 {
+ compatible = "qcom,gcc-ipq5018";
+ reg = <0x01800000 0x80000>;
+ clocks = <&xo_board_clk>,
+ <&sleep_clk>,
+ <&pcie20_phy0_pipe_clk>,
+ <&pcie20_phy1_pipe_clk>,
+ <&usb3_phy0_pipe_clk>,
+ <&gephy_rx_clk>,
+ <&gephy_tx_clk>,
+ <&uniphy_rx_clk>,
+ <&uniphy_tx_clk>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+...
diff --git a/include/dt-bindings/clock/qcom,gcc-ipq5018.h b/include/dt-bindings/clock/qcom,gcc-ipq5018.h
new file mode 100644
index 000000000000..f3de2fdfeea1
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-ipq5018.h
@@ -0,0 +1,183 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_5018_H
+#define _DT_BINDINGS_CLOCK_IPQ_GCC_5018_H
+
+#define GPLL0_MAIN 0
+#define GPLL0 1
+#define GPLL2_MAIN 2
+#define GPLL2 3
+#define GPLL4_MAIN 4
+#define GPLL4 5
+#define UBI32_PLL_MAIN 6
+#define UBI32_PLL 7
+#define ADSS_PWM_CLK_SRC 8
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC 9
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC 10
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC 11
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC 12
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC 13
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC 14
+#define BLSP1_UART1_APPS_CLK_SRC 15
+#define BLSP1_UART2_APPS_CLK_SRC 16
+#define CRYPTO_CLK_SRC 17
+#define GCC_ADSS_PWM_CLK 18
+#define GCC_BLSP1_AHB_CLK 19
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK 20
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK 21
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK 22
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK 23
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK 24
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK 25
+#define GCC_BLSP1_UART1_APPS_CLK 26
+#define GCC_BLSP1_UART2_APPS_CLK 27
+#define GCC_BTSS_LPO_CLK 28
+#define GCC_CMN_BLK_AHB_CLK 29
+#define GCC_CMN_BLK_SYS_CLK 30
+#define GCC_CRYPTO_AHB_CLK 31
+#define GCC_CRYPTO_AXI_CLK 32
+#define GCC_CRYPTO_CLK 33
+#define GCC_CRYPTO_PPE_CLK 34
+#define GCC_DCC_CLK 35
+#define GCC_GEPHY_RX_CLK 36
+#define GCC_GEPHY_TX_CLK 37
+#define GCC_GMAC0_CFG_CLK 38
+#define GCC_GMAC0_PTP_CLK 39
+#define GCC_GMAC0_RX_CLK 40
+#define GCC_GMAC0_SYS_CLK 41
+#define GCC_GMAC0_TX_CLK 42
+#define GCC_GMAC1_CFG_CLK 43
+#define GCC_GMAC1_PTP_CLK 44
+#define GCC_GMAC1_RX_CLK 45
+#define GCC_GMAC1_SYS_CLK 46
+#define GCC_GMAC1_TX_CLK 47
+#define GCC_GP1_CLK 48
+#define GCC_GP2_CLK 49
+#define GCC_GP3_CLK 50
+#define GCC_LPASS_CORE_AXIM_CLK 51
+#define GCC_LPASS_SWAY_CLK 52
+#define GCC_MDIO0_AHB_CLK 53
+#define GCC_MDIO1_AHB_CLK 54
+#define GCC_PCIE0_AHB_CLK 55
+#define GCC_PCIE0_AUX_CLK 56
+#define GCC_PCIE0_AXI_M_CLK 57
+#define GCC_PCIE0_AXI_S_BRIDGE_CLK 58
+#define GCC_PCIE0_AXI_S_CLK 59
+#define GCC_PCIE0_PIPE_CLK 60
+#define GCC_PCIE1_AHB_CLK 61
+#define GCC_PCIE1_AUX_CLK 62
+#define GCC_PCIE1_AXI_M_CLK 63
+#define GCC_PCIE1_AXI_S_BRIDGE_CLK 64
+#define GCC_PCIE1_AXI_S_CLK 65
+#define GCC_PCIE1_PIPE_CLK 66
+#define GCC_PRNG_AHB_CLK 67
+#define GCC_Q6_AXIM_CLK 68
+#define GCC_Q6_AXIM2_CLK 69
+#define GCC_Q6_AXIS_CLK 70
+#define GCC_Q6_AHB_CLK 71
+#define GCC_Q6_AHB_S_CLK 72
+#define GCC_Q6_TSCTR_1TO2_CLK 73
+#define GCC_Q6SS_ATBM_CLK 74
+#define GCC_Q6SS_PCLKDBG_CLK 75
+#define GCC_Q6SS_TRIG_CLK 76
+#define GCC_QDSS_AT_CLK 77
+#define GCC_QDSS_CFG_AHB_CLK 78
+#define GCC_QDSS_DAP_AHB_CLK 79
+#define GCC_QDSS_DAP_CLK 80
+#define GCC_QDSS_ETR_USB_CLK 81
+#define GCC_QDSS_EUD_AT_CLK 82
+#define GCC_QDSS_STM_CLK 83
+#define GCC_QDSS_TRACECLKIN_CLK 84
+#define GCC_QDSS_TSCTR_DIV8_CLK 85
+#define GCC_QPIC_AHB_CLK 86
+#define GCC_QPIC_CLK 87
+#define GCC_QPIC_IO_MACRO_CLK 88
+#define GCC_SDCC1_AHB_CLK 89
+#define GCC_SDCC1_APPS_CLK 90
+#define GCC_SLEEP_CLK_SRC 91
+#define GCC_SNOC_GMAC0_AHB_CLK 92
+#define GCC_SNOC_GMAC0_AXI_CLK 93
+#define GCC_SNOC_GMAC1_AHB_CLK 94
+#define GCC_SNOC_GMAC1_AXI_CLK 95
+#define GCC_SNOC_LPASS_AXIM_CLK 96
+#define GCC_SNOC_LPASS_SWAY_CLK 97
+#define GCC_SNOC_UBI0_AXI_CLK 98
+#define GCC_SYS_NOC_PCIE0_AXI_CLK 99
+#define GCC_SYS_NOC_PCIE1_AXI_CLK 100
+#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 101
+#define GCC_SYS_NOC_USB0_AXI_CLK 102
+#define GCC_SYS_NOC_WCSS_AHB_CLK 103
+#define GCC_UBI0_AXI_CLK 104
+#define GCC_UBI0_CFG_CLK 105
+#define GCC_UBI0_CORE_CLK 106
+#define GCC_UBI0_DBG_CLK 107
+#define GCC_UBI0_NC_AXI_CLK 108
+#define GCC_UBI0_UTCM_CLK 109
+#define GCC_UNIPHY_AHB_CLK 110
+#define GCC_UNIPHY_RX_CLK 111
+#define GCC_UNIPHY_SYS_CLK 112
+#define GCC_UNIPHY_TX_CLK 113
+#define GCC_USB0_AUX_CLK 114
+#define GCC_USB0_EUD_AT_CLK 115
+#define GCC_USB0_LFPS_CLK 116
+#define GCC_USB0_MASTER_CLK 117
+#define GCC_USB0_MOCK_UTMI_CLK 118
+#define GCC_USB0_PHY_CFG_AHB_CLK 119
+#define GCC_USB0_SLEEP_CLK 120
+#define GCC_WCSS_ACMT_CLK 121
+#define GCC_WCSS_AHB_S_CLK 122
+#define GCC_WCSS_AXI_M_CLK 123
+#define GCC_WCSS_AXI_S_CLK 124
+#define GCC_WCSS_DBG_IFC_APB_BDG_CLK 125
+#define GCC_WCSS_DBG_IFC_APB_CLK 126
+#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK 127
+#define GCC_WCSS_DBG_IFC_ATB_CLK 128
+#define GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK 129
+#define GCC_WCSS_DBG_IFC_DAPBUS_CLK 130
+#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK 131
+#define GCC_WCSS_DBG_IFC_NTS_CLK 132
+#define GCC_WCSS_ECAHB_CLK 133
+#define GCC_XO_CLK 134
+#define GCC_XO_CLK_SRC 135
+#define GMAC0_RX_CLK_SRC 136
+#define GMAC0_TX_CLK_SRC 137
+#define GMAC1_RX_CLK_SRC 138
+#define GMAC1_TX_CLK_SRC 139
+#define GMAC_CLK_SRC 140
+#define GP1_CLK_SRC 141
+#define GP2_CLK_SRC 142
+#define GP3_CLK_SRC 143
+#define LPASS_AXIM_CLK_SRC 144
+#define LPASS_SWAY_CLK_SRC 145
+#define PCIE0_AUX_CLK_SRC 146
+#define PCIE0_AXI_CLK_SRC 147
+#define PCIE1_AUX_CLK_SRC 148
+#define PCIE1_AXI_CLK_SRC 149
+#define PCNOC_BFDCD_CLK_SRC 150
+#define Q6_AXI_CLK_SRC 151
+#define QDSS_AT_CLK_SRC 152
+#define QDSS_STM_CLK_SRC 153
+#define QDSS_TSCTR_CLK_SRC 154
+#define QDSS_TRACECLKIN_CLK_SRC 155
+#define QPIC_IO_MACRO_CLK_SRC 156
+#define SDCC1_APPS_CLK_SRC 157
+#define SYSTEM_NOC_BFDCD_CLK_SRC 158
+#define UBI0_AXI_CLK_SRC 159
+#define UBI0_CORE_CLK_SRC 160
+#define USB0_AUX_CLK_SRC 161
+#define USB0_LFPS_CLK_SRC 162
+#define USB0_MASTER_CLK_SRC 163
+#define USB0_MOCK_UTMI_CLK_SRC 164
+#define WCSS_AHB_CLK_SRC 165
+#define PCIE0_PIPE_CLK_SRC 166
+#define PCIE1_PIPE_CLK_SRC 167
+#define USB0_PIPE_CLK_SRC 168
+#define GCC_USB0_PIPE_CLK 169
+#define GMAC0_RX_DIV_CLK_SRC 170
+#define GMAC0_TX_DIV_CLK_SRC 171
+#define GMAC1_RX_DIV_CLK_SRC 172
+#define GMAC1_TX_DIV_CLK_SRC 173
+#endif
diff --git a/include/dt-bindings/reset/qcom,gcc-ipq5018.h b/include/dt-bindings/reset/qcom,gcc-ipq5018.h
new file mode 100644
index 000000000000..8f03c92fc23b
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,gcc-ipq5018.h
@@ -0,0 +1,122 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_RESET_IPQ_GCC_5018_H
+#define _DT_BINDINGS_RESET_IPQ_GCC_5018_H
+
+#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 0
+#define GCC_BLSP1_BCR 1
+#define GCC_BLSP1_QUP1_BCR 2
+#define GCC_BLSP1_QUP2_BCR 3
+#define GCC_BLSP1_QUP3_BCR 4
+#define GCC_BLSP1_UART1_BCR 5
+#define GCC_BLSP1_UART2_BCR 6
+#define GCC_BOOT_ROM_BCR 7
+#define GCC_BTSS_BCR 8
+#define GCC_CMN_BLK_BCR 9
+#define GCC_CMN_LDO_BCR 10
+#define GCC_CE_BCR 11
+#define GCC_CRYPTO_BCR 12
+#define GCC_DCC_BCR 13
+#define GCC_DCD_BCR 14
+#define GCC_DDRSS_BCR 15
+#define GCC_EDPD_BCR 16
+#define GCC_GEPHY_BCR 17
+#define GCC_GEPHY_MDC_SW_ARES 18
+#define GCC_GEPHY_DSP_HW_ARES 19
+#define GCC_GEPHY_RX_ARES 20
+#define GCC_GEPHY_TX_ARES 21
+#define GCC_GMAC0_BCR 22
+#define GCC_GMAC0_CFG_ARES 23
+#define GCC_GMAC0_SYS_ARES 24
+#define GCC_GMAC1_BCR 25
+#define GCC_GMAC1_CFG_ARES 26
+#define GCC_GMAC1_SYS_ARES 27
+#define GCC_IMEM_BCR 28
+#define GCC_LPASS_BCR 29
+#define GCC_MDIO0_BCR 30
+#define GCC_MDIO1_BCR 31
+#define GCC_MPM_BCR 32
+#define GCC_PCIE0_BCR 33
+#define GCC_PCIE0_LINK_DOWN_BCR 34
+#define GCC_PCIE0_PHY_BCR 35
+#define GCC_PCIE0PHY_PHY_BCR 36
+#define GCC_PCIE0_PIPE_ARES 37
+#define GCC_PCIE0_SLEEP_ARES 38
+#define GCC_PCIE0_CORE_STICKY_ARES 39
+#define GCC_PCIE0_AXI_MASTER_ARES 40
+#define GCC_PCIE0_AXI_SLAVE_ARES 41
+#define GCC_PCIE0_AHB_ARES 42
+#define GCC_PCIE0_AXI_MASTER_STICKY_ARES 43
+#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 44
+#define GCC_PCIE1_BCR 45
+#define GCC_PCIE1_LINK_DOWN_BCR 46
+#define GCC_PCIE1_PHY_BCR 47
+#define GCC_PCIE1PHY_PHY_BCR 48
+#define GCC_PCIE1_PIPE_ARES 49
+#define GCC_PCIE1_SLEEP_ARES 50
+#define GCC_PCIE1_CORE_STICKY_ARES 51
+#define GCC_PCIE1_AXI_MASTER_ARES 52
+#define GCC_PCIE1_AXI_SLAVE_ARES 53
+#define GCC_PCIE1_AHB_ARES 54
+#define GCC_PCIE1_AXI_MASTER_STICKY_ARES 55
+#define GCC_PCIE1_AXI_SLAVE_STICKY_ARES 56
+#define GCC_PCNOC_BCR 57
+#define GCC_PCNOC_BUS_TIMEOUT0_BCR 58
+#define GCC_PCNOC_BUS_TIMEOUT1_BCR 59
+#define GCC_PCNOC_BUS_TIMEOUT2_BCR 60
+#define GCC_PCNOC_BUS_TIMEOUT3_BCR 61
+#define GCC_PCNOC_BUS_TIMEOUT4_BCR 62
+#define GCC_PCNOC_BUS_TIMEOUT5_BCR 63
+#define GCC_PCNOC_BUS_TIMEOUT6_BCR 64
+#define GCC_PCNOC_BUS_TIMEOUT7_BCR 65
+#define GCC_PCNOC_BUS_TIMEOUT8_BCR 66
+#define GCC_PCNOC_BUS_TIMEOUT9_BCR 67
+#define GCC_PCNOC_BUS_TIMEOUT10_BCR 68
+#define GCC_PCNOC_BUS_TIMEOUT11_BCR 69
+#define GCC_PRNG_BCR 70
+#define GCC_Q6SS_DBG_ARES 71
+#define GCC_Q6_AHB_S_ARES 72
+#define GCC_Q6_AHB_ARES 73
+#define GCC_Q6_AXIM2_ARES 74
+#define GCC_Q6_AXIM_ARES 75
+#define GCC_Q6_AXIS_ARES 76
+#define GCC_QDSS_BCR 77
+#define GCC_QPIC_BCR 78
+#define GCC_QUSB2_0_PHY_BCR 79
+#define GCC_SDCC1_BCR 80
+#define GCC_SEC_CTRL_BCR 81
+#define GCC_SPDM_BCR 82
+#define GCC_SYSTEM_NOC_BCR 83
+#define GCC_TCSR_BCR 84
+#define GCC_TLMM_BCR 85
+#define GCC_UBI0_AXI_ARES 86
+#define GCC_UBI0_AHB_ARES 87
+#define GCC_UBI0_NC_AXI_ARES 88
+#define GCC_UBI0_DBG_ARES 89
+#define GCC_UBI0_UTCM_ARES 90
+#define GCC_UBI0_CORE_ARES 91
+#define GCC_UBI32_BCR 92
+#define GCC_UNIPHY_BCR 93
+#define GCC_UNIPHY_AHB_ARES 94
+#define GCC_UNIPHY_SYS_ARES 95
+#define GCC_UNIPHY_RX_ARES 96
+#define GCC_UNIPHY_TX_ARES 97
+#define GCC_USB0_BCR 98
+#define GCC_USB0_PHY_BCR 99
+#define GCC_WCSS_BCR 100
+#define GCC_WCSS_DBG_ARES 101
+#define GCC_WCSS_ECAHB_ARES 102
+#define GCC_WCSS_ACMT_ARES 103
+#define GCC_WCSS_DBG_BDG_ARES 104
+#define GCC_WCSS_AHB_S_ARES 105
+#define GCC_WCSS_AXI_M_ARES 106
+#define GCC_WCSS_AXI_S_ARES 107
+#define GCC_WCSS_Q6_BCR 108
+#define GCC_WCSSAON_RESET 109
+#define GCC_UNIPHY_SOFT_RESET 110
+#define GCC_GEPHY_MISC_ARES 111
+
+#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [v9 2/8] clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018
2023-06-08 12:21 [v9 0/8] Add minimal boot support for IPQ5018 Sricharan Ramabadhran
2023-06-08 12:21 ` [v9 1/8] dt-bindings: arm64: Add IPQ5018 clock and reset Sricharan Ramabadhran
@ 2023-06-08 12:21 ` Sricharan Ramabadhran
2023-06-09 13:52 ` Konrad Dybcio
2023-06-08 12:21 ` [v9 3/8] dt-bindings: pinctrl: qcom: Add support for ipq5018 Sricharan Ramabadhran
` (5 subsequent siblings)
7 siblings, 1 reply; 13+ messages in thread
From: Sricharan Ramabadhran @ 2023-06-08 12:21 UTC (permalink / raw)
To: agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, ulf.hansson,
linus.walleij, catalin.marinas, will, p.zabel, linux-arm-msm,
devicetree, linux-kernel, linux-mmc, linux-gpio,
linux-arm-kernel, robimarko, krzysztof.kozlowski,
andy.shevchenko, quic_srichara
Add support for the global clock controller found on IPQ5018
based devices.
Co-developed-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Co-developed-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
---
[v9] Sorted the headers and cleaned the unwanted ones
Added trailing comma for .parent_hws member
Removed the hunk touching ipq5332 kconfig (unintentionally)
drivers/clk/qcom/Kconfig | 8 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gcc-ipq5018.c | 3724 ++++++++++++++++++++++++++++++++
3 files changed, 3733 insertions(+)
create mode 100644 drivers/clk/qcom/gcc-ipq5018.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 9cd1f05d436b..8ed74fa007e5 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -145,6 +145,14 @@ config IPQ_GCC_4019
Say Y if you want to use peripheral devices such as UART, SPI,
i2c, USB, SD/eMMC, etc.
+config IPQ_GCC_5018
+ tristate "IPQ5018 Global Clock Controller"
+ depends on ARM64 || COMPILE_TEST
+ help
+ Support for global clock controller on ipq5018 devices.
+ Say Y if you want to use peripheral devices such as UART, SPI,
+ i2c, USB, SD/eMMC, etc.
+
config IPQ_GCC_5332
tristate "IPQ5332 Global Clock Controller"
depends on ARM64 || COMPILE_TEST
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 75d035150118..1393ee62d8cf 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o
obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o
obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o
obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
+obj-$(CONFIG_IPQ_GCC_5018) += gcc-ipq5018.o
obj-$(CONFIG_IPQ_GCC_5332) += gcc-ipq5332.o
obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
diff --git a/drivers/clk/qcom/gcc-ipq5018.c b/drivers/clk/qcom/gcc-ipq5018.c
new file mode 100644
index 000000000000..96f5cac180cb
--- /dev/null
+++ b/drivers/clk/qcom/gcc-ipq5018.c
@@ -0,0 +1,3724 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright (c) 2023, The Linux Foundation. All rights reserved.
+ */
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/qcom,gcc-ipq5018.h>
+#include <dt-bindings/reset/qcom,gcc-ipq5018.h>
+
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "clk-regmap-divider.h"
+#include "clk-regmap-mux.h"
+#include "clk-regmap-phy-mux.h"
+#include "reset.h"
+
+/* Need to match the order of clocks in DT binding */
+enum {
+ DT_XO,
+ DT_SLEEP_CLK,
+ DT_PCIE20_PHY0_PIPE_CLK,
+ DT_PCIE20_PHY1_PIPE_CLK,
+ DT_USB3_PHY0_CC_PIPE_CLK,
+ DT_GEPHY_RX_CLK,
+ DT_GEPHY_TX_CLK,
+ DT_UNIPHY_RX_CLK,
+ DT_UNIPHY_TX_CLK,
+};
+
+enum {
+ P_XO,
+ P_CORE_PI_SLEEP_CLK,
+ P_PCIE20_PHY0_PIPE,
+ P_PCIE20_PHY1_PIPE,
+ P_USB3PHY_0_PIPE,
+ P_GEPHY_RX,
+ P_GEPHY_TX,
+ P_UNIPHY_RX,
+ P_UNIPHY_TX,
+ P_GPLL0,
+ P_GPLL0_DIV2,
+ P_GPLL2,
+ P_GPLL4,
+ P_UBI32_PLL,
+};
+
+static const struct clk_parent_data gcc_xo_data[] = {
+ { .index = DT_XO },
+};
+
+static const struct clk_parent_data gcc_sleep_clk_data[] = {
+ { .index = DT_SLEEP_CLK },
+};
+
+static struct clk_alpha_pll gpll0_main = {
+ .offset = 0x21000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .enable_reg = 0x0b000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gpll0_main",
+ .parent_data = gcc_xo_data,
+ .num_parents = ARRAY_SIZE(gcc_xo_data),
+ .ops = &clk_alpha_pll_stromer_ops,
+ },
+ },
+};
+
+static struct clk_alpha_pll gpll2_main = {
+ .offset = 0x4a000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .enable_reg = 0x0b000,
+ .enable_mask = BIT(2),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gpll2_main",
+ .parent_data = gcc_xo_data,
+ .num_parents = ARRAY_SIZE(gcc_xo_data),
+ .ops = &clk_alpha_pll_stromer_ops,
+ },
+ },
+};
+
+static struct clk_alpha_pll gpll4_main = {
+ .offset = 0x24000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .enable_reg = 0x0b000,
+ .enable_mask = BIT(5),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gpll4_main",
+ .parent_data = gcc_xo_data,
+ .num_parents = ARRAY_SIZE(gcc_xo_data),
+ .ops = &clk_alpha_pll_stromer_ops,
+ },
+ },
+};
+
+static struct clk_alpha_pll ubi32_pll_main = {
+ .offset = 0x25000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .enable_reg = 0x0b000,
+ .enable_mask = BIT(6),
+ .hw.init = &(struct clk_init_data) {
+ .name = "ubi32_pll_main",
+ .parent_data = gcc_xo_data,
+ .num_parents = ARRAY_SIZE(gcc_xo_data),
+ .ops = &clk_alpha_pll_stromer_ops,
+ },
+ },
+};
+
+static struct clk_alpha_pll_postdiv gpll0 = {
+ .offset = 0x21000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .width = 4,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "gpll0",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gpll0_main.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ro_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_alpha_pll_postdiv gpll2 = {
+ .offset = 0x4a000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .width = 4,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "gpll2",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gpll2_main.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ro_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_alpha_pll_postdiv gpll4 = {
+ .offset = 0x24000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .width = 4,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "gpll4",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gpll4_main.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ro_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_alpha_pll_postdiv ubi32_pll = {
+ .offset = 0x25000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .width = 4,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "ubi32_pll",
+ .parent_hws = (const struct clk_hw *[]) {
+ &ubi32_pll_main.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ro_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_fixed_factor gpll0_out_main_div2 = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data) {
+ .name = "gpll0_out_main_div2",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gpll0_main.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = {
+ { .index = DT_XO },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll0_out_main_div2.hw },
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL0_DIV2, 4 },
+};
+
+static const struct clk_parent_data gcc_xo_gpll0[] = {
+ { .index = DT_XO },
+ { .hw = &gpll0.clkr.hw },
+};
+
+static const struct parent_map gcc_xo_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+};
+
+static const struct clk_parent_data gcc_xo_gpll0_out_main_div2_gpll0[] = {
+ { .index = DT_XO },
+ { .hw = &gpll0_out_main_div2.hw },
+ { .hw = &gpll0.clkr.hw },
+};
+
+static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0_DIV2, 2 },
+ { P_GPLL0, 1 },
+};
+
+static const struct clk_parent_data gcc_xo_ubi32_gpll0[] = {
+ { .index = DT_XO },
+ { .hw = &ubi32_pll.clkr.hw },
+ { .hw = &gpll0.clkr.hw },
+};
+
+static const struct parent_map gcc_xo_ubi32_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_UBI32_PLL, 1 },
+ { P_GPLL0, 2 },
+};
+
+static const struct clk_parent_data gcc_xo_gpll0_gpll2[] = {
+ { .index = DT_XO },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll2.clkr.hw },
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL2, 2 },
+};
+
+static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll4[] = {
+ { .index = DT_XO },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll2.clkr.hw },
+ { .hw = &gpll4.clkr.hw },
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll2_gpll4_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL2, 2 },
+ { P_GPLL4, 3 },
+};
+
+static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
+ { .index = DT_XO },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll4.clkr.hw },
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL4, 2 },
+};
+
+static const struct clk_parent_data gcc_xo_gpll0_core_pi_sleep_clk[] = {
+ { .index = DT_XO },
+ { .hw = &gpll0.clkr.hw },
+ { .index = DT_SLEEP_CLK },
+};
+
+static const struct parent_map gcc_xo_gpll0_core_pi_sleep_clk_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 2 },
+ { P_CORE_PI_SLEEP_CLK, 6 },
+};
+
+static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk[] = {
+ { .index = DT_XO },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll0_out_main_div2.hw },
+ { .index = DT_SLEEP_CLK },
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL0_DIV2, 4 },
+ { P_CORE_PI_SLEEP_CLK, 6 },
+};
+
+static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
+ { .index = DT_XO },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll2.clkr.hw },
+ { .hw = &gpll0_out_main_div2.hw },
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL2, 2 },
+ { P_GPLL0_DIV2, 4 },
+};
+
+static const struct clk_parent_data gcc_xo_gpll4_gpll0_gpll0_out_main_div2[] = {
+ { .index = DT_XO },
+ { .hw = &gpll4.clkr.hw },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll0_out_main_div2.hw },
+};
+
+static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1[] = {
+ { P_XO, 0 },
+ { P_GPLL4, 1 },
+ { P_GPLL0, 2 },
+ { P_GPLL0_DIV2, 4 },
+};
+
+static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map2[] = {
+ { P_XO, 0 },
+ { P_GPLL4, 1 },
+ { P_GPLL0, 3 },
+ { P_GPLL0_DIV2, 4 },
+};
+
+static const struct clk_parent_data gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0[] = {
+ { .index = DT_XO },
+ { .index = DT_GEPHY_RX_CLK },
+ { .index = DT_GEPHY_TX_CLK },
+ { .hw = &ubi32_pll.clkr.hw },
+ { .hw = &gpll0.clkr.hw },
+};
+
+static const struct parent_map gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_GEPHY_RX, 1 },
+ { P_GEPHY_TX, 2 },
+ { P_UBI32_PLL, 3 },
+ { P_GPLL0, 4 },
+};
+
+static const struct clk_parent_data gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0[] = {
+ { .index = DT_XO },
+ { .index = DT_GEPHY_TX_CLK },
+ { .index = DT_GEPHY_RX_CLK },
+ { .hw = &ubi32_pll.clkr.hw },
+ { .hw = &gpll0.clkr.hw },
+};
+
+static const struct parent_map gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_GEPHY_TX, 1 },
+ { P_GEPHY_RX, 2 },
+ { P_UBI32_PLL, 3 },
+ { P_GPLL0, 4 },
+};
+
+static const struct clk_parent_data gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0[] = {
+ { .index = DT_XO },
+ { .index = DT_UNIPHY_RX_CLK },
+ { .index = DT_UNIPHY_TX_CLK },
+ { .hw = &ubi32_pll.clkr.hw },
+ { .hw = &gpll0.clkr.hw },
+};
+
+static const struct parent_map gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_UNIPHY_RX, 1 },
+ { P_UNIPHY_TX, 2 },
+ { P_UBI32_PLL, 3 },
+ { P_GPLL0, 4 },
+};
+
+static const struct clk_parent_data gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0[] = {
+ { .index = DT_XO },
+ { .index = DT_UNIPHY_TX_CLK },
+ { .index = DT_UNIPHY_RX_CLK },
+ { .hw = &ubi32_pll.clkr.hw },
+ { .hw = &gpll0.clkr.hw },
+};
+
+static const struct parent_map gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_UNIPHY_TX, 1 },
+ { P_UNIPHY_RX, 2 },
+ { P_UBI32_PLL, 3 },
+ { P_GPLL0, 4 },
+};
+
+static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = {
+ { .index = DT_PCIE20_PHY0_PIPE_CLK },
+ { .index = DT_XO },
+};
+
+static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = {
+ { P_PCIE20_PHY0_PIPE, 0 },
+ { P_XO, 2 },
+};
+
+static const struct clk_parent_data gcc_pcie20_phy1_pipe_clk_xo[] = {
+ { .index = DT_PCIE20_PHY1_PIPE_CLK },
+ { .index = DT_XO },
+};
+
+static const struct parent_map gcc_pcie20_phy1_pipe_clk_xo_map[] = {
+ { P_PCIE20_PHY1_PIPE, 0 },
+ { P_XO, 2 },
+};
+
+static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {
+ { .index = DT_USB3_PHY0_CC_PIPE_CLK },
+ { .index = DT_XO },
+};
+
+static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
+ { P_USB3PHY_0_PIPE, 0 },
+ { P_XO, 2 },
+};
+
+static const struct freq_tbl ftbl_adss_pwm_clk_src[] = {
+ F(24000000, P_XO, 1, 0, 0),
+ F(100000000, P_GPLL0, 8, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 adss_pwm_clk_src = {
+ .cmd_rcgr = 0x1f008,
+ .freq_tbl = ftbl_adss_pwm_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "adss_pwm_clk_src",
+ .parent_data = gcc_xo_gpll0,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_apss_axi_clk_src[] = {
+ F(400000000, P_GPLL0, 2, 0, 0),
+ { }
+};
+
+static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = {
+ F(50000000, P_GPLL0, 16, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x0200c,
+ .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "blsp1_qup1_i2c_apps_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x03000,
+ .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "blsp1_qup2_i2c_apps_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x04000,
+ .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "blsp1_qup3_i2c_apps_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = {
+ F(960000, P_XO, 10, 2, 5),
+ F(4800000, P_XO, 5, 0, 0),
+ F(9600000, P_XO, 2, 4, 5),
+ F(16000000, P_GPLL0, 10, 1, 5),
+ F(24000000, P_XO, 1, 0, 0),
+ F(50000000, P_GPLL0, 16, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
+ .cmd_rcgr = 0x02024,
+ .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "blsp1_qup1_spi_apps_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
+ .cmd_rcgr = 0x03014,
+ .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "blsp1_qup2_spi_apps_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
+ .cmd_rcgr = 0x04014,
+ .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "blsp1_qup3_spi_apps_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = {
+ F(3686400, P_GPLL0_DIV2, 1, 144, 15625),
+ F(7372800, P_GPLL0_DIV2, 1, 288, 15625),
+ F(14745600, P_GPLL0_DIV2, 1, 576, 15625),
+ F(24000000, P_XO, 1, 0, 0),
+ F(25000000, P_GPLL0, 16, 1, 2),
+ F(40000000, P_GPLL0, 1, 1, 20),
+ F(46400000, P_GPLL0, 1, 29, 500),
+ F(48000000, P_GPLL0, 1, 3, 50),
+ F(51200000, P_GPLL0, 1, 8, 125),
+ F(56000000, P_GPLL0, 1, 7, 100),
+ F(58982400, P_GPLL0, 1, 1152, 15625),
+ F(60000000, P_GPLL0, 1, 3, 40),
+ F(64000000, P_GPLL0, 10, 4, 5),
+ { }
+};
+
+static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
+ .cmd_rcgr = 0x02044,
+ .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "blsp1_uart1_apps_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
+ .cmd_rcgr = 0x03034,
+ .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "blsp1_uart2_apps_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_crypto_clk_src[] = {
+ F(160000000, P_GPLL0, 5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 crypto_clk_src = {
+ .cmd_rcgr = 0x16004,
+ .freq_tbl = ftbl_crypto_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "crypto_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gmac0_tx_clk_src[] = {
+ F(2500000, P_GEPHY_TX, 5, 0, 0),
+ F(24000000, P_XO, 1, 0, 0),
+ F(25000000, P_GEPHY_TX, 5, 0, 0),
+ F(125000000, P_GEPHY_TX, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gmac0_rx_clk_src = {
+ .cmd_rcgr = 0x68020,
+ .parent_map = gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0_map,
+ .hid_width = 5,
+ .freq_tbl = ftbl_gmac0_tx_clk_src,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "gmac0_rx_clk_src",
+ .parent_data = gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0,
+ .num_parents = ARRAY_SIZE(gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div gmac0_rx_div_clk_src = {
+ .reg = 0x68420,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(struct clk_init_data) {
+ .name = "gmac0_rx_div_clk_src",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gmac0_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static struct clk_rcg2 gmac0_tx_clk_src = {
+ .cmd_rcgr = 0x68028,
+ .parent_map = gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0_map,
+ .hid_width = 5,
+ .freq_tbl = ftbl_gmac0_tx_clk_src,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "gmac0_tx_clk_src",
+ .parent_data = gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0,
+ .num_parents = ARRAY_SIZE(gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div gmac0_tx_div_clk_src = {
+ .reg = 0x68424,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(struct clk_init_data) {
+ .name = "gmac0_tx_div_clk_src",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gmac0_tx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static const struct freq_tbl ftbl_gmac1_rx_clk_src[] = {
+ F(2500000, P_UNIPHY_RX, 12.5, 0, 0),
+ F(24000000, P_XO, 1, 0, 0),
+ F(25000000, P_UNIPHY_RX, 2.5, 0, 0),
+ F(125000000, P_UNIPHY_RX, 2.5, 0, 0),
+ F(125000000, P_UNIPHY_RX, 1, 0, 0),
+ F(312500000, P_UNIPHY_RX, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gmac1_rx_clk_src = {
+ .cmd_rcgr = 0x68030,
+ .parent_map = gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0_map,
+ .hid_width = 5,
+ .freq_tbl = ftbl_gmac1_rx_clk_src,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "gmac1_rx_clk_src",
+ .parent_data = gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0,
+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div gmac1_rx_div_clk_src = {
+ .reg = 0x68430,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(struct clk_init_data) {
+ .name = "gmac1_rx_div_clk_src",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gmac1_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static const struct freq_tbl ftbl_gmac1_tx_clk_src[] = {
+ F(2500000, P_UNIPHY_TX, 12.5, 0, 0),
+ F(24000000, P_XO, 1, 0, 0),
+ F(25000000, P_UNIPHY_TX, 2.5, 0, 0),
+ F(125000000, P_UNIPHY_TX, 2.5, 0, 0),
+ F(125000000, P_UNIPHY_TX, 1, 0, 0),
+ F(312500000, P_UNIPHY_TX, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gmac1_tx_clk_src = {
+ .cmd_rcgr = 0x68038,
+ .parent_map = gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0_map,
+ .hid_width = 5,
+ .freq_tbl = ftbl_gmac1_tx_clk_src,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "gmac1_tx_clk_src",
+ .parent_data = gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0,
+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div gmac1_tx_div_clk_src = {
+ .reg = 0x68434,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(struct clk_init_data) {
+ .name = "gmac1_tx_div_clk_src",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gmac1_tx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static const struct freq_tbl ftbl_gmac_clk_src[] = {
+ F(240000000, P_GPLL4, 5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gmac_clk_src = {
+ .cmd_rcgr = 0x68080,
+ .parent_map = gcc_xo_gpll0_gpll4_map,
+ .hid_width = 5,
+ .freq_tbl = ftbl_gmac_clk_src,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "gmac_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll4,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gp_clk_src[] = {
+ F(200000000, P_GPLL0, 4, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gp1_clk_src = {
+ .cmd_rcgr = 0x08004,
+ .freq_tbl = ftbl_gp_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "gp1_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gp2_clk_src = {
+ .cmd_rcgr = 0x09004,
+ .freq_tbl = ftbl_gp_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "gp2_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gp3_clk_src = {
+ .cmd_rcgr = 0x0a004,
+ .freq_tbl = ftbl_gp_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "gp3_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_lpass_axim_clk_src[] = {
+ F(133333334, P_GPLL0, 6, 0, 0),
+ { }
+};
+
+struct clk_rcg2 lpass_axim_clk_src = {
+ .cmd_rcgr = 0x2E028,
+ .freq_tbl = ftbl_lpass_axim_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "lpass_axim_clk_src",
+ .parent_data = gcc_xo_gpll0,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_lpass_sway_clk_src[] = {
+ F(66666667, P_GPLL0, 12, 0, 0),
+ { }
+};
+
+struct clk_rcg2 lpass_sway_clk_src = {
+ .cmd_rcgr = 0x2E040,
+ .freq_tbl = ftbl_lpass_sway_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "lpass_sway_clk_src",
+ .parent_data = gcc_xo_gpll0,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_pcie0_aux_clk_src[] = {
+ F(2000000, P_XO, 12, 0, 0),
+};
+
+static struct clk_rcg2 pcie0_aux_clk_src = {
+ .cmd_rcgr = 0x75020,
+ .freq_tbl = ftbl_pcie0_aux_clk_src,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "pcie0_aux_clk_src",
+ .parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_pcie0_axi_clk_src[] = {
+ F(240000000, P_GPLL4, 5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 pcie0_axi_clk_src = {
+ .cmd_rcgr = 0x75050,
+ .freq_tbl = ftbl_pcie0_axi_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll4_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "pcie0_axi_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll4,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 pcie1_aux_clk_src = {
+ .cmd_rcgr = 0x76020,
+ .freq_tbl = ftbl_pcie0_aux_clk_src,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "pcie1_aux_clk_src",
+ .parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 pcie1_axi_clk_src = {
+ .cmd_rcgr = 0x76050,
+ .freq_tbl = ftbl_gp_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "pcie1_axi_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_mux pcie0_pipe_clk_src = {
+ .reg = 0x7501c,
+ .shift = 8,
+ .width = 2,
+ .parent_map = gcc_pcie20_phy0_pipe_clk_xo_map,
+ .clkr = {
+ .hw.init = &(struct clk_init_data) {
+ .name = "pcie0_pipe_clk_src",
+ .parent_data = gcc_pcie20_phy0_pipe_clk_xo,
+ .num_parents = ARRAY_SIZE(gcc_pcie20_phy0_pipe_clk_xo),
+ .ops = &clk_regmap_mux_closest_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static struct clk_regmap_mux pcie1_pipe_clk_src = {
+ .reg = 0x7601c,
+ .shift = 8,
+ .width = 2,
+ .parent_map = gcc_pcie20_phy1_pipe_clk_xo_map, .clkr = {
+ .hw.init = &(struct clk_init_data) {
+ .name = "pcie1_pipe_clk_src",
+ .parent_data = gcc_pcie20_phy1_pipe_clk_xo,
+ .num_parents = ARRAY_SIZE(gcc_pcie20_phy1_pipe_clk_xo),
+ .ops = &clk_regmap_mux_closest_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = {
+ F(100000000, P_GPLL0, 8, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
+ .cmd_rcgr = 0x27000,
+ .freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "pcnoc_bfdcd_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_fixed_factor pcnoc_clk_src = {
+ .mult = 1,
+ .div = 1,
+ .hw.init = &(struct clk_init_data) {
+ .name = "pcnoc_clk_src",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct freq_tbl ftbl_qdss_at_clk_src[] = {
+ F(240000000, P_GPLL4, 5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 qdss_at_clk_src = {
+ .cmd_rcgr = 0x2900c,
+ .freq_tbl = ftbl_qdss_at_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "qdss_at_clk_src",
+ .parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_qdss_stm_clk_src[] = {
+ F(200000000, P_GPLL0, 4, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 qdss_stm_clk_src = {
+ .cmd_rcgr = 0x2902C,
+ .freq_tbl = ftbl_qdss_stm_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "qdss_stm_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_qdss_traceclkin_clk_src[] = {
+ F(266666667, P_GPLL0, 3, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 qdss_traceclkin_clk_src = {
+ .cmd_rcgr = 0x29048,
+ .freq_tbl = ftbl_qdss_traceclkin_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "qdss_traceclkin_clk_src",
+ .parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_qdss_tsctr_clk_src[] = {
+ F(600000000, P_GPLL4, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 qdss_tsctr_clk_src = {
+ .cmd_rcgr = 0x29064,
+ .freq_tbl = ftbl_qdss_tsctr_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "qdss_tsctr_clk_src",
+ .parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_fixed_factor qdss_tsctr_div2_clk_src = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data) {
+ .name = "qdss_tsctr_div2_clk_src",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qdss_tsctr_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_fixed_factor_ops,
+ },
+};
+
+static struct clk_fixed_factor qdss_dap_sync_clk_src = {
+ .mult = 1,
+ .div = 4,
+ .hw.init = &(struct clk_init_data) {
+ .name = "qdss_dap_sync_clk_src",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qdss_tsctr_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ },
+};
+
+static struct clk_fixed_factor eud_at_clk_src = {
+ .mult = 1,
+ .div = 6,
+ .hw.init = &(struct clk_init_data) {
+ .name = "eud_at_clk_src",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qdss_at_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct freq_tbl ftbl_qpic_io_macro_clk_src[] = {
+ F(24000000, P_XO, 1, 0, 0),
+ F(100000000, P_GPLL0, 8, 0, 0),
+ F(200000000, P_GPLL0, 4, 0, 0),
+ F(320000000, P_GPLL0, 2.5, 0, 0),
+};
+
+static struct clk_rcg2 qpic_io_macro_clk_src = {
+ .cmd_rcgr = 0x57010,
+ .freq_tbl = ftbl_qpic_io_macro_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll2_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "qpic_io_macro_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
+ F(143713, P_XO, 1, 1, 167),
+ F(400000, P_XO, 1, 1, 60),
+ F(24000000, P_XO, 1, 0, 0),
+ F(48000000, P_GPLL2, 12, 1, 2),
+ F(96000000, P_GPLL2, 12, 0, 0),
+ F(177777778, P_GPLL0, 1, 2, 9),
+ F(192000000, P_GPLL2, 6, 0, 0),
+ F(200000000, P_GPLL0, 4, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 sdcc1_apps_clk_src = {
+ .cmd_rcgr = 0x42004,
+ .freq_tbl = ftbl_sdcc1_apps_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "sdcc1_apps_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
+ .ops = &clk_rcg2_floor_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = {
+ F(266666667, P_GPLL0, 3, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 system_noc_bfdcd_clk_src = {
+ .cmd_rcgr = 0x26004,
+ .freq_tbl = ftbl_system_noc_bfdcd_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "system_noc_bfdcd_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_fixed_factor system_noc_clk_src = {
+ .mult = 1,
+ .div = 1,
+ .hw.init = &(struct clk_init_data) {
+ .name = "system_noc_clk_src",
+ .parent_hws = (const struct clk_hw *[]) {
+ &system_noc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_rcg2 ubi0_axi_clk_src = {
+ .cmd_rcgr = 0x68088,
+ .freq_tbl = ftbl_apss_axi_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll2_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "ubi0_axi_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
+ .ops = &clk_rcg2_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct freq_tbl ftbl_ubi0_core_clk_src[] = {
+ F(850000000, P_UBI32_PLL, 1, 0, 0),
+ F(1000000000, P_UBI32_PLL, 1, 0, 0),
+};
+
+static struct clk_rcg2 ubi0_core_clk_src = {
+ .cmd_rcgr = 0x68100,
+ .freq_tbl = ftbl_ubi0_core_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_ubi32_gpll0_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "ubi0_core_clk_src",
+ .parent_data = gcc_xo_ubi32_gpll0,
+ .num_parents = ARRAY_SIZE(gcc_xo_ubi32_gpll0),
+ .ops = &clk_rcg2_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_rcg2 usb0_aux_clk_src = {
+ .cmd_rcgr = 0x3e05c,
+ .freq_tbl = ftbl_pcie0_aux_clk_src,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "usb0_aux_clk_src",
+ .parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_usb0_lfps_clk_src[] = {
+ F(25000000, P_GPLL0, 16, 1, 2),
+ { }
+};
+
+static struct clk_rcg2 usb0_lfps_clk_src = {
+ .cmd_rcgr = 0x3e090,
+ .freq_tbl = ftbl_usb0_lfps_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "usb0_lfps_clk_src",
+ .parent_data = gcc_xo_gpll0,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 usb0_master_clk_src = {
+ .cmd_rcgr = 0x3e00c,
+ .freq_tbl = ftbl_gp_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "usb0_master_clk_src",
+ .parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_usb0_mock_utmi_clk_src[] = {
+ F(60000000, P_GPLL4, 10, 1, 2),
+ { }
+};
+
+static struct clk_rcg2 usb0_mock_utmi_clk_src = {
+ .cmd_rcgr = 0x3e020,
+ .freq_tbl = ftbl_usb0_mock_utmi_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map2,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "usb0_mock_utmi_clk_src",
+ .parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_mux usb0_pipe_clk_src = {
+ .reg = 0x3e048,
+ .shift = 8,
+ .width = 2,
+ .parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map,
+ .clkr = {
+ .hw.init = &(struct clk_init_data) {
+ .name = "usb0_pipe_clk_src",
+ .parent_data = gcc_usb3phy_0_cc_pipe_clk_xo,
+ .num_parents = ARRAY_SIZE(gcc_usb3phy_0_cc_pipe_clk_xo),
+ .ops = &clk_regmap_mux_closest_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static const struct freq_tbl ftbl_q6_axi_clk_src[] = {
+ F(400000000, P_GPLL0, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 q6_axi_clk_src = {
+ .cmd_rcgr = 0x59120,
+ .freq_tbl = ftbl_q6_axi_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll2_gpll4_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "q6_axi_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll2_gpll4,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll4),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_wcss_ahb_clk_src[] = {
+ F(133333333, P_GPLL0, 6, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 wcss_ahb_clk_src = {
+ .cmd_rcgr = 0x59020,
+ .freq_tbl = ftbl_wcss_ahb_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "wcss_ahb_clk_src",
+ .parent_data = gcc_xo_gpll0,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_branch gcc_sleep_clk_src = {
+ .halt_reg = 0x30000,
+ .clkr = {
+ .enable_reg = 0x30000,
+ .enable_mask = BIT(1),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_sleep_clk_src",
+ .parent_data = gcc_sleep_clk_data,
+ .num_parents = ARRAY_SIZE(gcc_sleep_clk_data),
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_xo_clk_src = {
+ .halt_reg = 0x30018,
+ .clkr = {
+ .enable_reg = 0x30018,
+ .enable_mask = BIT(1),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_xo_clk_src",
+ .parent_data = gcc_xo_data,
+ .num_parents = ARRAY_SIZE(gcc_xo_data),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_xo_clk = {
+ .halt_reg = 0x30030,
+ .clkr = {
+ .enable_reg = 0x30030,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_xo_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gcc_xo_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_adss_pwm_clk = {
+ .halt_reg = 0x1f020,
+ .clkr = {
+ .enable_reg = 0x1f020,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_adss_pwm_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &adss_pwm_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_ahb_clk = {
+ .halt_reg = 0x01008,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x0b004,
+ .enable_mask = BIT(10),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_blsp1_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcnoc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
+ .halt_reg = 0x02008,
+ .clkr = {
+ .enable_reg = 0x02008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_blsp1_qup1_i2c_apps_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &blsp1_qup1_i2c_apps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
+ .halt_reg = 0x02004,
+ .clkr = {
+ .enable_reg = 0x02004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_blsp1_qup1_spi_apps_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &blsp1_qup1_spi_apps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
+ .halt_reg = 0x03010,
+ .clkr = {
+ .enable_reg = 0x03010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_blsp1_qup2_i2c_apps_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &blsp1_qup2_i2c_apps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
+ .halt_reg = 0x0300c,
+ .clkr = {
+ .enable_reg = 0x0300c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_blsp1_qup2_spi_apps_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &blsp1_qup2_spi_apps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
+ .halt_reg = 0x04010,
+ .clkr = {
+ .enable_reg = 0x04010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_blsp1_qup3_i2c_apps_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &blsp1_qup3_i2c_apps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
+ .halt_reg = 0x0400c,
+ .clkr = {
+ .enable_reg = 0x0400c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_blsp1_qup3_spi_apps_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &blsp1_qup3_spi_apps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_uart1_apps_clk = {
+ .halt_reg = 0x0203c,
+ .clkr = {
+ .enable_reg = 0x0203c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_blsp1_uart1_apps_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &blsp1_uart1_apps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_uart2_apps_clk = {
+ .halt_reg = 0x0302c,
+ .clkr = {
+ .enable_reg = 0x0302c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_blsp1_uart2_apps_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &blsp1_uart2_apps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_btss_lpo_clk = {
+ .halt_reg = 0x1c004,
+ .clkr = {
+ .enable_reg = 0x1c004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_btss_lpo_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_cmn_blk_ahb_clk = {
+ .halt_reg = 0x56308,
+ .clkr = {
+ .enable_reg = 0x56308,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_cmn_blk_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcnoc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_cmn_blk_sys_clk = {
+ .halt_reg = 0x5630c,
+ .clkr = {
+ .enable_reg = 0x5630c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_cmn_blk_sys_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gcc_xo_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_crypto_ahb_clk = {
+ .halt_reg = 0x16024,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x0b004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_crypto_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcnoc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_crypto_axi_clk = {
+ .halt_reg = 0x16020,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x0b004,
+ .enable_mask = BIT(1),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_crypto_axi_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcnoc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_crypto_clk = {
+ .halt_reg = 0x1601c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x0b004,
+ .enable_mask = BIT(2),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_crypto_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &crypto_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_dcc_clk = {
+ .halt_reg = 0x77004,
+ .clkr = {
+ .enable_reg = 0x77004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_dcc_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcnoc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gephy_rx_clk = {
+ .halt_reg = 0x56010,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x56010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_gephy_rx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gmac0_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static struct clk_branch gcc_gephy_tx_clk = {
+ .halt_reg = 0x56014,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x56014,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_gephy_tx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gmac0_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static struct clk_branch gcc_gmac0_cfg_clk = {
+ .halt_reg = 0x68304,
+ .clkr = {
+ .enable_reg = 0x68304,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_gmac0_cfg_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gmac_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gmac0_ptp_clk = {
+ .halt_reg = 0x68300,
+ .clkr = {
+ .enable_reg = 0x68300,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_gmac0_ptp_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gmac_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gmac0_rx_clk = {
+ .halt_reg = 0x68240,
+ .clkr = {
+ .enable_reg = 0x68240,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_gmac0_rx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gmac0_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static struct clk_branch gcc_gmac0_sys_clk = {
+ .halt_reg = 0x68190,
+ .halt_check = BRANCH_HALT_DELAY,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x683190,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_gmac0_sys_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gmac_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gmac0_tx_clk = {
+ .halt_reg = 0x68244,
+ .clkr = {
+ .enable_reg = 0x68244,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_gmac0_tx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gmac0_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static struct clk_branch gcc_gmac1_cfg_clk = {
+ .halt_reg = 0x68324,
+ .clkr = {
+ .enable_reg = 0x68324,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_gmac1_cfg_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gmac_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gmac1_ptp_clk = {
+ .halt_reg = 0x68320,
+ .clkr = {
+ .enable_reg = 0x68320,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_gmac1_ptp_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gmac_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gmac1_rx_clk = {
+ .halt_reg = 0x68248,
+ .clkr = {
+ .enable_reg = 0x68248,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_gmac1_rx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gmac1_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static struct clk_branch gcc_gmac1_sys_clk = {
+ .halt_reg = 0x68310,
+ .clkr = {
+ .enable_reg = 0x68310,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_gmac1_sys_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gmac_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gmac1_tx_clk = {
+ .halt_reg = 0x6824c,
+ .clkr = {
+ .enable_reg = 0x6824c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_gmac1_tx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gmac1_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static struct clk_branch gcc_gp1_clk = {
+ .halt_reg = 0x08000,
+ .clkr = {
+ .enable_reg = 0x08000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_gp1_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gp1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gp2_clk = {
+ .halt_reg = 0x09000,
+ .clkr = {
+ .enable_reg = 0x09000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_gp2_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gp2_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gp3_clk = {
+ .halt_reg = 0x0a000,
+ .clkr = {
+ .enable_reg = 0x0a000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_gp3_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gp3_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_lpass_core_axim_clk = {
+ .halt_reg = 0x2E048,
+ .halt_check = BRANCH_VOTED,
+ .clkr = {
+ .enable_reg = 0x2E048,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_lpass_core_axim_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &lpass_axim_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_lpass_sway_clk = {
+ .halt_reg = 0x2E04C,
+ .clkr = {
+ .enable_reg = 0x2E04C,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_lpass_sway_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &lpass_sway_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mdio0_ahb_clk = {
+ .halt_reg = 0x58004,
+ .clkr = {
+ .enable_reg = 0x58004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_mdioi0_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcnoc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mdio1_ahb_clk = {
+ .halt_reg = 0x58014,
+ .clkr = {
+ .enable_reg = 0x58014,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_mdio1_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcnoc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie0_ahb_clk = {
+ .halt_reg = 0x75010,
+ .clkr = {
+ .enable_reg = 0x75010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_pcie0_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcnoc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie0_aux_clk = {
+ .halt_reg = 0x75014,
+ .clkr = {
+ .enable_reg = 0x75014,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_pcie0_aux_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcie0_aux_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie0_axi_m_clk = {
+ .halt_reg = 0x75008,
+ .clkr = {
+ .enable_reg = 0x75008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_pcie0_axi_m_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcie0_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie0_axi_s_bridge_clk = {
+ .halt_reg = 0x75048,
+ .clkr = {
+ .enable_reg = 0x75048,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_pcie0_axi_s_bridge_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcie0_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie0_axi_s_clk = {
+ .halt_reg = 0x7500c,
+ .clkr = {
+ .enable_reg = 0x7500c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_pcie0_axi_s_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcie0_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie0_pipe_clk = {
+ .halt_reg = 0x75018,
+ .halt_check = BRANCH_HALT_DELAY,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x75018,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_pcie0_pipe_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcie0_pipe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie1_ahb_clk = {
+ .halt_reg = 0x76010,
+ .clkr = {
+ .enable_reg = 0x76010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_pcie1_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcnoc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie1_aux_clk = {
+ .halt_reg = 0x76014,
+ .clkr = {
+ .enable_reg = 0x76014,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_pcie1_aux_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcie1_aux_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie1_axi_m_clk = {
+ .halt_reg = 0x76008,
+ .clkr = {
+ .enable_reg = 0x76008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_pcie1_axi_m_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcie1_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie1_axi_s_bridge_clk = {
+ .halt_reg = 0x76048,
+ .clkr = {
+ .enable_reg = 0x76048,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_pcie1_axi_s_bridge_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcie1_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie1_axi_s_clk = {
+ .halt_reg = 0x7600c,
+ .clkr = {
+ .enable_reg = 0x7600c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_pcie1_axi_s_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcie1_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie1_pipe_clk = {
+ .halt_reg = 8,
+ .halt_check = BRANCH_HALT_DELAY,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x76018,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_pcie1_pipe_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcie1_pipe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_prng_ahb_clk = {
+ .halt_reg = 0x13004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x0b004,
+ .enable_mask = BIT(8),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_prng_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcnoc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_q6_ahb_clk = {
+ .halt_reg = 0x59138,
+ .clkr = {
+ .enable_reg = 0x59138,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_q6_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &wcss_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_q6_ahb_s_clk = {
+ .halt_reg = 0x5914C,
+ .clkr = {
+ .enable_reg = 0x5914C,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_q6_ahb_s_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &wcss_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_q6_axim_clk = {
+ .halt_reg = 0x5913C,
+ .clkr = {
+ .enable_reg = 0x5913C,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_q6_axim_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &q6_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_q6_axim2_clk = {
+ .halt_reg = 0x59150,
+ .clkr = {
+ .enable_reg = 0x59150,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_q6_axim2_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &q6_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_q6_axis_clk = {
+ .halt_reg = 0x59154,
+ .clkr = {
+ .enable_reg = 0x59154,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_q6_axis_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &system_noc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_q6_tsctr_1to2_clk = {
+ .halt_reg = 0x59148,
+ .clkr = {
+ .enable_reg = 0x59148,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_q6_tsctr_1to2_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qdss_tsctr_div2_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_q6ss_atbm_clk = {
+ .halt_reg = 0x59144,
+ .clkr = {
+ .enable_reg = 0x59144,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_q6ss_atbm_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qdss_at_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_q6ss_pclkdbg_clk = {
+ .halt_reg = 0x59140,
+ .clkr = {
+ .enable_reg = 0x59140,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_q6ss_pclkdbg_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qdss_dap_sync_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_q6ss_trig_clk = {
+ .halt_reg = 0x59128,
+ .clkr = {
+ .enable_reg = 0x59128,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_q6ss_trig_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qdss_dap_sync_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qdss_at_clk = {
+ .halt_reg = 0x29024,
+ .clkr = {
+ .enable_reg = 0x29024,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_qdss_at_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qdss_at_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qdss_dap_clk = {
+ .halt_reg = 0x29084,
+ .clkr = {
+ .enable_reg = 0x29084,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_qdss_dap_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qdss_tsctr_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qdss_cfg_ahb_clk = {
+ .halt_reg = 0x29008,
+ .clkr = {
+ .enable_reg = 0x29008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_qdss_cfg_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcnoc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qdss_dap_ahb_clk = {
+ .halt_reg = 0x29004,
+ .clkr = {
+ .enable_reg = 0x29004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_qdss_dap_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcnoc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qdss_etr_usb_clk = {
+ .halt_reg = 0x29028,
+ .clkr = {
+ .enable_reg = 0x29028,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_qdss_etr_usb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &system_noc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qdss_eud_at_clk = {
+ .halt_reg = 0x29020,
+ .clkr = {
+ .enable_reg = 0x29020,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_qdss_eud_at_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &eud_at_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qdss_stm_clk = {
+ .halt_reg = 0x29044,
+ .clkr = {
+ .enable_reg = 0x29044,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_qdss_stm_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qdss_stm_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qdss_traceclkin_clk = {
+ .halt_reg = 0x29060,
+ .clkr = {
+ .enable_reg = 0x29060,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_qdss_traceclkin_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qdss_traceclkin_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qdss_tsctr_div8_clk = {
+ .halt_reg = 0x2908c,
+ .clkr = {
+ .enable_reg = 0x2908c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_qdss_tsctr_div8_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qdss_tsctr_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qpic_ahb_clk = {
+ .halt_reg = 0x57024,
+ .clkr = {
+ .enable_reg = 0x57024,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_qpic_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcnoc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qpic_clk = {
+ .halt_reg = 0x57020,
+ .clkr = {
+ .enable_reg = 0x57020,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_qpic_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcnoc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qpic_io_macro_clk = {
+ .halt_reg = 0x5701c,
+ .clkr = {
+ .enable_reg = 0x5701c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_qpic_io_macro_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qpic_io_macro_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc1_ahb_clk = {
+ .halt_reg = 0x4201c,
+ .clkr = {
+ .enable_reg = 0x4201c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_sdcc1_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcnoc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc1_apps_clk = {
+ .halt_reg = 0x42018,
+ .clkr = {
+ .enable_reg = 0x42018,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_sdcc1_apps_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &sdcc1_apps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_snoc_gmac0_ahb_clk = {
+ .halt_reg = 0x260a0,
+ .clkr = {
+ .enable_reg = 0x260a0,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_snoc_gmac0_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gmac_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_snoc_gmac0_axi_clk = {
+ .halt_reg = 0x26084,
+ .clkr = {
+ .enable_reg = 0x26084,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_snoc_gmac0_axi_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gmac_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_snoc_gmac1_ahb_clk = {
+ .halt_reg = 0x260a4,
+ .clkr = {
+ .enable_reg = 0x260a4,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_snoc_gmac1_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gmac_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_snoc_gmac1_axi_clk = {
+ .halt_reg = 0x26088,
+ .clkr = {
+ .enable_reg = 0x26088,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_snoc_gmac1_axi_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gmac_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_snoc_lpass_axim_clk = {
+ .halt_reg = 0x26074,
+ .clkr = {
+ .enable_reg = 0x26074,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_snoc_lpass_axim_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &lpass_axim_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_snoc_lpass_sway_clk = {
+ .halt_reg = 0x26078,
+ .clkr = {
+ .enable_reg = 0x26078,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_snoc_lpass_sway_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &lpass_sway_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_snoc_ubi0_axi_clk = {
+ .halt_reg = 0x26094,
+ .clkr = {
+ .enable_reg = 0x26094,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_snoc_ubi0_axi_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &ubi0_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sys_noc_pcie0_axi_clk = {
+ .halt_reg = 0x26048,
+ .clkr = {
+ .enable_reg = 0x26048,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_sys_noc_pcie0_axi_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcie0_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sys_noc_pcie1_axi_clk = {
+ .halt_reg = 0x2604c,
+ .clkr = {
+ .enable_reg = 0x2604c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_sys_noc_pcie1_axi_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcie1_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sys_noc_qdss_stm_axi_clk = {
+ .halt_reg = 0x26024,
+ .clkr = {
+ .enable_reg = 0x26024,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_sys_noc_qdss_stm_axi_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qdss_stm_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sys_noc_usb0_axi_clk = {
+ .halt_reg = 0x26040,
+ .clkr = {
+ .enable_reg = 0x26040,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_sys_noc_usb0_axi_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &usb0_master_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sys_noc_wcss_ahb_clk = {
+ .halt_reg = 0x26034,
+ .clkr = {
+ .enable_reg = 0x26034,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_sys_noc_wcss_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &wcss_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ubi0_axi_clk = {
+ .halt_reg = 0x68200,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x68200,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_ubi0_axi_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &ubi0_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ubi0_cfg_clk = {
+ .halt_reg = 0x68160,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x68160,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_ubi0_cfg_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcnoc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ubi0_dbg_clk = {
+ .halt_reg = 0x68214,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x68214,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_ubi0_dbg_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qdss_tsctr_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ubi0_core_clk = {
+ .halt_reg = 0x68210,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x68210,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_ubi0_core_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &ubi0_core_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ubi0_nc_axi_clk = {
+ .halt_reg = 0x68204,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x68204,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_ubi0_nc_axi_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &system_noc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ubi0_utcm_clk = {
+ .halt_reg = 0x68208,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x68208,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_ubi0_utcm_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &system_noc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy_ahb_clk = {
+ .halt_reg = 0x56108,
+ .clkr = {
+ .enable_reg = 0x56108,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_uniphy_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcnoc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy_rx_clk = {
+ .halt_reg = 0x56110,
+ .clkr = {
+ .enable_reg = 0x56110,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_uniphy_rx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gmac1_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy_tx_clk = {
+ .halt_reg = 0x56114,
+ .clkr = {
+ .enable_reg = 0x56114,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_uniphy_tx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gmac1_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy_sys_clk = {
+ .halt_reg = 0x5610C,
+ .clkr = {
+ .enable_reg = 0x5610C,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_uniphy_sys_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gcc_xo_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_aux_clk = {
+ .halt_reg = 0x3e044,
+ .clkr = {
+ .enable_reg = 0x3e044,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_usb0_aux_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &usb0_aux_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_eud_at_clk = {
+ .halt_reg = 0x3e04c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x3e04c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_usb0_eud_at_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &eud_at_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_lfps_clk = {
+ .halt_reg = 0x3e050,
+ .clkr = {
+ .enable_reg = 0x3e050,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_usb0_lfps_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &usb0_lfps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_master_clk = {
+ .halt_reg = 0x3e000,
+ .clkr = {
+ .enable_reg = 0x3e000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_usb0_master_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &usb0_master_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_mock_utmi_clk = {
+ .halt_reg = 0x3e008,
+ .clkr = {
+ .enable_reg = 0x3e008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_usb0_mock_utmi_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &usb0_mock_utmi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
+ .halt_reg = 0x3e080,
+ .clkr = {
+ .enable_reg = 0x3e080,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_usb0_phy_cfg_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcnoc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_sleep_clk = {
+ .halt_reg = 0x3e004,
+ .clkr = {
+ .enable_reg = 0x3e004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_usb0_sleep_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gcc_sleep_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_pipe_clk = {
+ .halt_reg = 0x3e040,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x3e040,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_usb0_pipe_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &usb0_pipe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_wcss_acmt_clk = {
+ .halt_reg = 0x59064,
+ .clkr = {
+ .enable_reg = 0x59064,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_wcss_acmt_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &wcss_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_wcss_ahb_s_clk = {
+ .halt_reg = 0x59034,
+ .clkr = {
+ .enable_reg = 0x59034,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_wcss_ahb_s_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &wcss_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_wcss_axi_m_clk = {
+ .halt_reg = 0x5903C,
+ .clkr = {
+ .enable_reg = 0x5903C,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_wcss_axi_m_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &system_noc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_wcss_axi_s_clk = {
+ .halt_reg = 0x59068,
+ .clkr = {
+ .enable_reg = 0x59068,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_wi_s_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &system_noc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_wcss_dbg_ifc_apb_bdg_clk = {
+ .halt_reg = 0x59050,
+ .clkr = {
+ .enable_reg = 0x59050,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_wcss_dbg_ifc_apb_bdg_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qdss_dap_sync_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_wcss_dbg_ifc_apb_clk = {
+ .halt_reg = 0x59040,
+ .clkr = {
+ .enable_reg = 0x59040,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_wcss_dbg_ifc_apb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qdss_dap_sync_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_wcss_dbg_ifc_atb_bdg_clk = {
+ .halt_reg = 0x59054,
+ .clkr = {
+ .enable_reg = 0x59054,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_wcss_dbg_ifc_atb_bdg_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qdss_at_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_wcss_dbg_ifc_atb_clk = {
+ .halt_reg = 0x59044,
+ .clkr = {
+ .enable_reg = 0x59044,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_wcss_dbg_ifc_atb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qdss_at_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_wcss_dbg_ifc_dapbus_bdg_clk = {
+ .halt_reg = 0x59060,
+ .clkr = {
+ .enable_reg = 0x59060,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_wcss_dbg_ifc_dapbus_bdg_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qdss_dap_sync_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_wcss_dbg_ifc_dapbus_clk = {
+ .halt_reg = 0x5905C,
+ .clkr = {
+ .enable_reg = 0x5905C,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_wcss_dbg_ifc_dapbus_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qdss_dap_sync_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_wcss_dbg_ifc_nts_bdg_clk = {
+ .halt_reg = 0x59058,
+ .clkr = {
+ .enable_reg = 0x59058,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_wcss_dbg_ifc_nts_bdg_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qdss_tsctr_div2_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_wcss_dbg_ifc_nts_clk = {
+ .halt_reg = 0x59048,
+ .clkr = {
+ .enable_reg = 0x59048,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_wcss_dbg_ifc_nts_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qdss_tsctr_div2_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_wcss_ecahb_clk = {
+ .halt_reg = 0x59038,
+ .clkr = {
+ .enable_reg = 0x59038,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_wcss_ecahb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &wcss_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_hw *gcc_ipq5018_hws[] = {
+ &gpll0_out_main_div2.hw,
+ &pcnoc_clk_src.hw,
+ &system_noc_clk_src.hw,
+ &qdss_dap_sync_clk_src.hw,
+ &qdss_tsctr_div2_clk_src.hw,
+ &eud_at_clk_src.hw,
+};
+
+static const struct alpha_pll_config ubi32_pll_config = {
+ .l = 0x29,
+ .alpha = 0xAAAAAAAA,
+ .alpha_hi = 0xAA,
+ .config_ctl_val = 0x4001075b,
+ .main_output_mask = BIT(0),
+ .aux_output_mask = BIT(1),
+ .alpha_en_mask = BIT(24),
+ .vco_val = 0x1,
+ .vco_mask = GENMASK(21, 20),
+ .test_ctl_val = 0x0,
+ .test_ctl_hi_val = 0x0,
+};
+
+static struct clk_regmap *gcc_ipq5018_clks[] = {
+ [GPLL0_MAIN] = &gpll0_main.clkr,
+ [GPLL0] = &gpll0.clkr,
+ [GPLL2_MAIN] = &gpll2_main.clkr,
+ [GPLL2] = &gpll2.clkr,
+ [GPLL4_MAIN] = &gpll4_main.clkr,
+ [GPLL4] = &gpll4.clkr,
+ [UBI32_PLL_MAIN] = &ubi32_pll_main.clkr,
+ [UBI32_PLL] = &ubi32_pll.clkr,
+ [ADSS_PWM_CLK_SRC] = &adss_pwm_clk_src.clkr,
+ [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
+ [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
+ [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
+ [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
+ [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
+ [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
+ [GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,
+ [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
+ [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
+ [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
+ [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
+ [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
+ [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
+ [GCC_BTSS_LPO_CLK] = &gcc_btss_lpo_clk.clkr,
+ [GCC_CMN_BLK_AHB_CLK] = &gcc_cmn_blk_ahb_clk.clkr,
+ [GCC_CMN_BLK_SYS_CLK] = &gcc_cmn_blk_sys_clk.clkr,
+ [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
+ [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
+ [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
+ [GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
+ [GCC_GEPHY_RX_CLK] = &gcc_gephy_rx_clk.clkr,
+ [GCC_GEPHY_TX_CLK] = &gcc_gephy_tx_clk.clkr,
+ [GCC_GMAC0_CFG_CLK] = &gcc_gmac0_cfg_clk.clkr,
+ [GCC_GMAC0_PTP_CLK] = &gcc_gmac0_ptp_clk.clkr,
+ [GCC_GMAC0_RX_CLK] = &gcc_gmac0_rx_clk.clkr,
+ [GCC_GMAC0_SYS_CLK] = &gcc_gmac0_sys_clk.clkr,
+ [GCC_GMAC0_TX_CLK] = &gcc_gmac0_tx_clk.clkr,
+ [GCC_GMAC1_CFG_CLK] = &gcc_gmac1_cfg_clk.clkr,
+ [GCC_GMAC1_PTP_CLK] = &gcc_gmac1_ptp_clk.clkr,
+ [GCC_GMAC1_RX_CLK] = &gcc_gmac1_rx_clk.clkr,
+ [GCC_GMAC1_SYS_CLK] = &gcc_gmac1_sys_clk.clkr,
+ [GCC_GMAC1_TX_CLK] = &gcc_gmac1_tx_clk.clkr,
+ [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
+ [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
+ [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
+ [GCC_LPASS_CORE_AXIM_CLK] = &gcc_lpass_core_axim_clk.clkr,
+ [GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr,
+ [GCC_MDIO0_AHB_CLK] = &gcc_mdio0_ahb_clk.clkr,
+ [GCC_MDIO1_AHB_CLK] = &gcc_mdio1_ahb_clk.clkr,
+ [GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
+ [GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
+ [GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
+ [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
+ [GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
+ [GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr,
+ [GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr,
+ [GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr,
+ [GCC_PCIE1_AXI_S_BRIDGE_CLK] = &gcc_pcie1_axi_s_bridge_clk.clkr,
+ [GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr,
+ [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
+ [GCC_Q6_AXIM_CLK] = &gcc_q6_axim_clk.clkr,
+ [GCC_Q6_AXIM2_CLK] = &gcc_q6_axim2_clk.clkr,
+ [GCC_Q6_AXIS_CLK] = &gcc_q6_axis_clk.clkr,
+ [GCC_Q6_AHB_CLK] = &gcc_q6_ahb_clk.clkr,
+ [GCC_Q6_AHB_S_CLK] = &gcc_q6_ahb_s_clk.clkr,
+ [GCC_Q6_TSCTR_1TO2_CLK] = &gcc_q6_tsctr_1to2_clk.clkr,
+ [GCC_Q6SS_ATBM_CLK] = &gcc_q6ss_atbm_clk.clkr,
+ [GCC_Q6SS_PCLKDBG_CLK] = &gcc_q6ss_pclkdbg_clk.clkr,
+ [GCC_Q6SS_TRIG_CLK] = &gcc_q6ss_trig_clk.clkr,
+ [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr,
+ [GCC_QDSS_CFG_AHB_CLK] = &gcc_qdss_cfg_ahb_clk.clkr,
+ [GCC_QDSS_DAP_AHB_CLK] = &gcc_qdss_dap_ahb_clk.clkr,
+ [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
+ [GCC_QDSS_ETR_USB_CLK] = &gcc_qdss_etr_usb_clk.clkr,
+ [GCC_QDSS_EUD_AT_CLK] = &gcc_qdss_eud_at_clk.clkr,
+ [GCC_QDSS_STM_CLK] = &gcc_qdss_stm_clk.clkr,
+ [GCC_QDSS_TRACECLKIN_CLK] = &gcc_qdss_traceclkin_clk.clkr,
+ [GCC_QDSS_TSCTR_DIV8_CLK] = &gcc_qdss_tsctr_div8_clk.clkr,
+ [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
+ [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
+ [GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr,
+ [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
+ [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
+ [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
+ [GCC_SNOC_GMAC0_AHB_CLK] = &gcc_snoc_gmac0_ahb_clk.clkr,
+ [GCC_SNOC_GMAC0_AXI_CLK] = &gcc_snoc_gmac0_axi_clk.clkr,
+ [GCC_SNOC_GMAC1_AHB_CLK] = &gcc_snoc_gmac1_ahb_clk.clkr,
+ [GCC_SNOC_GMAC1_AXI_CLK] = &gcc_snoc_gmac1_axi_clk.clkr,
+ [GCC_SNOC_LPASS_AXIM_CLK] = &gcc_snoc_lpass_axim_clk.clkr,
+ [GCC_SNOC_LPASS_SWAY_CLK] = &gcc_snoc_lpass_sway_clk.clkr,
+ [GCC_SNOC_UBI0_AXI_CLK] = &gcc_snoc_ubi0_axi_clk.clkr,
+ [GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr,
+ [GCC_SYS_NOC_PCIE1_AXI_CLK] = &gcc_sys_noc_pcie1_axi_clk.clkr,
+ [GCC_SYS_NOC_QDSS_STM_AXI_CLK] = &gcc_sys_noc_qdss_stm_axi_clk.clkr,
+ [GCC_SYS_NOC_USB0_AXI_CLK] = &gcc_sys_noc_usb0_axi_clk.clkr,
+ [GCC_SYS_NOC_WCSS_AHB_CLK] = &gcc_sys_noc_wcss_ahb_clk.clkr,
+ [GCC_UBI0_AXI_CLK] = &gcc_ubi0_axi_clk.clkr,
+ [GCC_UBI0_CFG_CLK] = &gcc_ubi0_cfg_clk.clkr,
+ [GCC_UBI0_CORE_CLK] = &gcc_ubi0_core_clk.clkr,
+ [GCC_UBI0_DBG_CLK] = &gcc_ubi0_dbg_clk.clkr,
+ [GCC_UBI0_NC_AXI_CLK] = &gcc_ubi0_nc_axi_clk.clkr,
+ [GCC_UBI0_UTCM_CLK] = &gcc_ubi0_utcm_clk.clkr,
+ [GCC_UNIPHY_AHB_CLK] = &gcc_uniphy_ahb_clk.clkr,
+ [GCC_UNIPHY_RX_CLK] = &gcc_uniphy_rx_clk.clkr,
+ [GCC_UNIPHY_SYS_CLK] = &gcc_uniphy_sys_clk.clkr,
+ [GCC_UNIPHY_TX_CLK] = &gcc_uniphy_tx_clk.clkr,
+ [GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
+ [GCC_USB0_EUD_AT_CLK] = &gcc_usb0_eud_at_clk.clkr,
+ [GCC_USB0_LFPS_CLK] = &gcc_usb0_lfps_clk.clkr,
+ [GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
+ [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
+ [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
+ [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
+ [GCC_WCSS_ACMT_CLK] = &gcc_wcss_acmt_clk.clkr,
+ [GCC_WCSS_AHB_S_CLK] = &gcc_wcss_ahb_s_clk.clkr,
+ [GCC_WCSS_AXI_M_CLK] = &gcc_wcss_axi_m_clk.clkr,
+ [GCC_WCSS_AXI_S_CLK] = &gcc_wcss_axi_s_clk.clkr,
+ [GCC_WCSS_DBG_IFC_APB_BDG_CLK] = &gcc_wcss_dbg_ifc_apb_bdg_clk.clkr,
+ [GCC_WCSS_DBG_IFC_APB_CLK] = &gcc_wcss_dbg_ifc_apb_clk.clkr,
+ [GCC_WCSS_DBG_IFC_ATB_BDG_CLK] = &gcc_wcss_dbg_ifc_atb_bdg_clk.clkr,
+ [GCC_WCSS_DBG_IFC_ATB_CLK] = &gcc_wcss_dbg_ifc_atb_clk.clkr,
+ [GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK] = &gcc_wcss_dbg_ifc_dapbus_bdg_clk.clkr,
+ [GCC_WCSS_DBG_IFC_DAPBUS_CLK] = &gcc_wcss_dbg_ifc_dapbus_clk.clkr,
+ [GCC_WCSS_DBG_IFC_NTS_BDG_CLK] = &gcc_wcss_dbg_ifc_nts_bdg_clk.clkr,
+ [GCC_WCSS_DBG_IFC_NTS_CLK] = &gcc_wcss_dbg_ifc_nts_clk.clkr,
+ [GCC_WCSS_ECAHB_CLK] = &gcc_wcss_ecahb_clk.clkr,
+ [GCC_XO_CLK] = &gcc_xo_clk.clkr,
+ [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
+ [GMAC0_RX_CLK_SRC] = &gmac0_rx_clk_src.clkr,
+ [GMAC0_RX_DIV_CLK_SRC] = &gmac0_rx_div_clk_src.clkr,
+ [GMAC0_TX_CLK_SRC] = &gmac0_tx_clk_src.clkr,
+ [GMAC0_TX_DIV_CLK_SRC] = &gmac0_tx_div_clk_src.clkr,
+ [GMAC1_RX_CLK_SRC] = &gmac1_rx_clk_src.clkr,
+ [GMAC1_RX_DIV_CLK_SRC] = &gmac1_rx_div_clk_src.clkr,
+ [GMAC1_TX_CLK_SRC] = &gmac1_tx_clk_src.clkr,
+ [GMAC1_TX_DIV_CLK_SRC] = &gmac1_tx_div_clk_src.clkr,
+ [GMAC_CLK_SRC] = &gmac_clk_src.clkr,
+ [GP1_CLK_SRC] = &gp1_clk_src.clkr,
+ [GP2_CLK_SRC] = &gp2_clk_src.clkr,
+ [GP3_CLK_SRC] = &gp3_clk_src.clkr,
+ [LPASS_AXIM_CLK_SRC] = &lpass_axim_clk_src.clkr,
+ [LPASS_SWAY_CLK_SRC] = &lpass_sway_clk_src.clkr,
+ [PCIE0_AUX_CLK_SRC] = &pcie0_aux_clk_src.clkr,
+ [PCIE0_AXI_CLK_SRC] = &pcie0_axi_clk_src.clkr,
+ [PCIE1_AUX_CLK_SRC] = &pcie1_aux_clk_src.clkr,
+ [PCIE1_AXI_CLK_SRC] = &pcie1_axi_clk_src.clkr,
+ [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
+ [Q6_AXI_CLK_SRC] = &q6_axi_clk_src.clkr,
+ [QDSS_AT_CLK_SRC] = &qdss_at_clk_src.clkr,
+ [QDSS_STM_CLK_SRC] = &qdss_stm_clk_src.clkr,
+ [QDSS_TSCTR_CLK_SRC] = &qdss_tsctr_clk_src.clkr,
+ [QDSS_TRACECLKIN_CLK_SRC] = &qdss_traceclkin_clk_src.clkr,
+ [QPIC_IO_MACRO_CLK_SRC] = &qpic_io_macro_clk_src.clkr,
+ [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
+ [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
+ [UBI0_AXI_CLK_SRC] = &ubi0_axi_clk_src.clkr,
+ [UBI0_CORE_CLK_SRC] = &ubi0_core_clk_src.clkr,
+ [USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr,
+ [USB0_LFPS_CLK_SRC] = &usb0_lfps_clk_src.clkr,
+ [USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr,
+ [USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr,
+ [WCSS_AHB_CLK_SRC] = &wcss_ahb_clk_src.clkr,
+ [PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,
+ [PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr,
+ [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
+ [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,
+ [USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
+ [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
+};
+
+static const struct qcom_reset_map gcc_ipq5018_resets[] = {
+ [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 },
+ [GCC_BLSP1_BCR] = { 0x01000, 0 },
+ [GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
+ [GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 },
+ [GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 },
+ [GCC_BLSP1_UART1_BCR] = { 0x02038, 0 },
+ [GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
+ [GCC_BOOT_ROM_BCR] = { 0x13008, 0 },
+ [GCC_BTSS_BCR] = { 0x1c000, 0 },
+ [GCC_CMN_BLK_BCR] = { 0x56300, 0 },
+ [GCC_CMN_LDO_BCR] = { 0x33000, 0 },
+ [GCC_CE_BCR] = { 0x33014, 0 },
+ [GCC_CRYPTO_BCR] = { 0x16000, 0 },
+ [GCC_DCC_BCR] = { 0x77000, 0 },
+ [GCC_DCD_BCR] = { 0x2a000, 0 },
+ [GCC_DDRSS_BCR] = { 0x1e000, 0 },
+ [GCC_EDPD_BCR] = { 0x3a000, 0 },
+ [GCC_GEPHY_BCR] = { 0x56000, 0 },
+ [GCC_GEPHY_MDC_SW_ARES] = { 0x56004, 0 },
+ [GCC_GEPHY_DSP_HW_ARES] = { 0x56004, 1 },
+ [GCC_GEPHY_RX_ARES] = { 0x56004, 2 },
+ [GCC_GEPHY_TX_ARES] = { 0x56004, 3 },
+ [GCC_GMAC0_BCR] = { 0x19000, 0 },
+ [GCC_GMAC0_CFG_ARES] = { 0x68428, 0 },
+ [GCC_GMAC0_SYS_ARES] = { 0x68428, 1 },
+ [GCC_GMAC1_BCR] = { 0x19100, 0 },
+ [GCC_GMAC1_CFG_ARES] = { 0x68438, 0 },
+ [GCC_GMAC1_SYS_ARES] = { 0x68438, 1 },
+ [GCC_IMEM_BCR] = { 0x0e000, 0 },
+ [GCC_LPASS_BCR] = { 0x2e000, 0 },
+ [GCC_MDIO0_BCR] = { 0x58000, 0 },
+ [GCC_MDIO1_BCR] = { 0x58010, 0 },
+ [GCC_MPM_BCR] = { 0x2c000, 0 },
+ [GCC_PCIE0_BCR] = { 0x75004, 0 },
+ [GCC_PCIE0_LINK_DOWN_BCR] = { 0x750a8, 0 },
+ [GCC_PCIE0_PHY_BCR] = { 0x75038, 0 },
+ [GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 },
+ [GCC_PCIE0_PIPE_ARES] = { 0x75040, 0 },
+ [GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 },
+ [GCC_PCIE0_CORE_STICKY_ARES] = { 0x75040, 2 },
+ [GCC_PCIE0_AXI_MASTER_ARES] = { 0x75040, 3 },
+ [GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 },
+ [GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
+ [GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
+ [GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 },
+ [GCC_PCIE1_BCR] = { 0x76004, 0 },
+ [GCC_PCIE1_LINK_DOWN_BCR] = { 0x76044, 0 },
+ [GCC_PCIE1_PHY_BCR] = { 0x76038, 0 },
+ [GCC_PCIE1PHY_PHY_BCR] = { 0x7603c, 0 },
+ [GCC_PCIE1_PIPE_ARES] = { 0x76040, 0 },
+ [GCC_PCIE1_SLEEP_ARES] = { 0x76040, 1 },
+ [GCC_PCIE1_CORE_STICKY_ARES] = { 0x76040, 2 },
+ [GCC_PCIE1_AXI_MASTER_ARES] = { 0x76040, 3 },
+ [GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 },
+ [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
+ [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
+ [GCC_PCIE1_AXI_SLAVE_STICKY_ARES] = { 0x76040, 7 },
+ [GCC_PCNOC_BCR] = { 0x27018, 0 },
+ [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 },
+ [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 },
+ [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 },
+ [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 },
+ [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 },
+ [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 },
+ [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 },
+ [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 },
+ [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 },
+ [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 },
+ [GCC_PCNOC_BUS_TIMEOUT10_BCR] = { 0x48050, 0 },
+ [GCC_PCNOC_BUS_TIMEOUT11_BCR] = { 0x48058, 0 },
+ [GCC_PRNG_BCR] = { 0x13000, 0 },
+ [GCC_Q6SS_DBG_ARES] = { 0x59110, 0 },
+ [GCC_Q6_AHB_S_ARES] = { 0x59110, 1 },
+ [GCC_Q6_AHB_ARES] = { 0x59110, 2 },
+ [GCC_Q6_AXIM2_ARES] = { 0x59110, 3 },
+ [GCC_Q6_AXIM_ARES] = { 0x59110, 4 },
+ [GCC_Q6_AXIS_ARES] = { 0x59158, 0 },
+ [GCC_QDSS_BCR] = { 0x29000, 0 },
+ [GCC_QPIC_BCR] = { 0x57018, 0 },
+ [GCC_QUSB2_0_PHY_BCR] = { 0x41030, 0 },
+ [GCC_SDCC1_BCR] = { 0x42000, 0 },
+ [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
+ [GCC_SPDM_BCR] = { 0x2f000, 0 },
+ [GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 },
+ [GCC_TCSR_BCR] = { 0x28000, 0 },
+ [GCC_TLMM_BCR] = { 0x34000, 0 },
+ [GCC_UBI0_AXI_ARES] = { 0x680},
+ [GCC_UBI0_AHB_ARES] = { 0x68010, 1 },
+ [GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 },
+ [GCC_UBI0_DBG_ARES] = { 0x68010, 3 },
+ [GCC_UBI0_UTCM_ARES] = { 0x68010, 6 },
+ [GCC_UBI0_CORE_ARES] = { 0x68010, 7 },
+ [GCC_UBI32_BCR] = { 0x19064, 0 },
+ [GCC_UNIPHY_BCR] = { 0x56100, 0 },
+ [GCC_UNIPHY_AHB_ARES] = { 0x56104, 0 },
+ [GCC_UNIPHY_SYS_ARES] = { 0x56104, 1 },
+ [GCC_UNIPHY_RX_ARES] = { 0x56104, 4 },
+ [GCC_UNIPHY_TX_ARES] = { 0x56104, 5 },
+ [GCC_UNIPHY_SOFT_RESET] = {0x56104, 0 },
+ [GCC_USB0_BCR] = { 0x3e070, 0 },
+ [GCC_USB0_PHY_BCR] = { 0x3e034, 0 },
+ [GCC_WCSS_BCR] = { 0x18000, 0 },
+ [GCC_WCSS_DBG_ARES] = { 0x59008, 0 },
+ [GCC_WCSS_ECAHB_ARES] = { 0x59008, 1 },
+ [GCC_WCSS_ACMT_ARES] = { 0x59008, 2 },
+ [GCC_WCSS_DBG_BDG_ARES] = { 0x59008, 3 },
+ [GCC_WCSS_AHB_S_ARES] = { 0x59008, 4 },
+ [GCC_WCSS_AXI_M_ARES] = { 0x59008, 5 },
+ [GCC_WCSS_AXI_S_ARES] = { 0x59008, 6 },
+ [GCC_WCSS_Q6_BCR] = { 0x18004, 0 },
+ [GCC_WCSSAON_RESET] = { 0x59010, 0},
+ [GCC_GEPHY_MISC_ARES] = { 0x56004, 0 },
+};
+
+static const struct of_device_id gcc_ipq5018_match_table[] = {
+ { .compatible = "qcom,gcc-ipq5018" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, gcc_ipq5018_match_table);
+
+static const struct regmap_config gcc_ipq5018_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x7fffc,
+ .fast_io = true,
+};
+
+static const struct qcom_cc_desc gcc_ipq5018_desc = {
+ .config = &gcc_ipq5018_regmap_config,
+ .clks = gcc_ipq5018_clks,
+ .num_clks = ARRAY_SIZE(gcc_ipq5018_clks),
+ .resets = gcc_ipq5018_resets,
+ .num_resets = ARRAY_SIZE(gcc_ipq5018_resets),
+ .clk_hws = gcc_ipq5018_hws,
+ .num_clk_hws = ARRAY_SIZE(gcc_ipq5018_hws),
+};
+
+static int gcc_ipq5018_probe(struct platform_device *pdev)
+{
+ struct regmap *regmap;
+ struct qcom_cc_desc ipq5018_desc = gcc_ipq5018_desc;
+
+ regmap = qcom_cc_map(pdev, &ipq5018_desc);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
+
+ return qcom_cc_really_probe(pdev, &ipq5018_desc, regmap);
+}
+
+static struct platform_driver gcc_ipq5018_driver = {
+ .probe = gcc_ipq5018_probe,
+ .driver = {
+ .name = "qcom,gcc-ipq5018",
+ .of_match_table = gcc_ipq5018_match_table,
+ },
+};
+
+static int __init gcc_ipq5018_init(void)
+{
+ return platform_driver_register(&gcc_ipq5018_driver);
+}
+core_initcall(gcc_ipq5018_init);
+
+static void __exit gcc_ipq5018_exit(void)
+{
+ platform_driver_unregister(&gcc_ipq5018_driver);
+}
+module_exit(gcc_ipq5018_exit);
+
+MODULE_DESCRIPTION("Qualcomm Technologies, Inc. GCC IPQ5018 Driver");
+MODULE_LICENSE("GPL");
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [v9 3/8] dt-bindings: pinctrl: qcom: Add support for ipq5018
2023-06-08 12:21 [v9 0/8] Add minimal boot support for IPQ5018 Sricharan Ramabadhran
2023-06-08 12:21 ` [v9 1/8] dt-bindings: arm64: Add IPQ5018 clock and reset Sricharan Ramabadhran
2023-06-08 12:21 ` [v9 2/8] clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018 Sricharan Ramabadhran
@ 2023-06-08 12:21 ` Sricharan Ramabadhran
2023-06-09 7:00 ` Linus Walleij
2023-06-08 12:21 ` [v9 4/8] pinctrl: qcom: Add IPQ5018 pinctrl driver Sricharan Ramabadhran
` (4 subsequent siblings)
7 siblings, 1 reply; 13+ messages in thread
From: Sricharan Ramabadhran @ 2023-06-08 12:21 UTC (permalink / raw)
To: agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, ulf.hansson,
linus.walleij, catalin.marinas, will, p.zabel, linux-arm-msm,
devicetree, linux-kernel, linux-mmc, linux-gpio,
linux-arm-kernel, robimarko, krzysztof.kozlowski,
andy.shevchenko, quic_srichara
Add device tree binding Documentation details for ipq5018
pinctrl driver.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Co-developed-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
Co-developed-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
---
.../bindings/pinctrl/qcom,ipq5018-tlmm.yaml | 127 ++++++++++++++++++
1 file changed, 127 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq5018-tlmm.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq5018-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5018-tlmm.yaml
new file mode 100644
index 000000000000..fad0118fd521
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5018-tlmm.yaml
@@ -0,0 +1,127 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,ipq5018-tlmm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm IPQ5018 TLMM pin controller
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+ - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+
+description:
+ Top Level Mode Multiplexer pin controller in Qualcomm IPQ5018 SoC.
+
+properties:
+ compatible:
+ const: qcom,ipq5018-tlmm
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+ "#interrupt-cells": true
+ gpio-controller: true
+ "#gpio-cells": true
+ gpio-ranges: true
+ wakeup-parent: true
+
+ gpio-reserved-ranges:
+ minItems: 1
+ maxItems: 24
+
+ gpio-line-names:
+ maxItems: 47
+
+patternProperties:
+ "-state$":
+ oneOf:
+ - $ref: "#/$defs/qcom-ipq5018-tlmm-state"
+ - patternProperties:
+ "-pins$":
+ $ref: "#/$defs/qcom-ipq5018-tlmm-state"
+ additionalProperties: false
+
+$defs:
+ qcom-ipq5018-tlmm-state:
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+ $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
+ unevaluatedProperties: false
+
+ properties:
+ pins:
+ description:
+ List of gpio pins affected by the properties specified in this
+ subnode.
+ items:
+ pattern: "^gpio([0-9]|[1-3][0-9]|4[0-6])$"
+ minItems: 1
+ maxItems: 8
+
+ function:
+ description:
+ Specify the alternative function to be configured for the specified
+ pins.
+
+ enum: [ atest_char, audio_pdm0, audio_pdm1, audio_rxbclk, audio_rxd,
+ audio_rxfsync, audio_rxmclk, audio_txbclk, audio_txd,
+ audio_txfsync, audio_txmclk, blsp0_i2c, blsp0_spi, blsp0_uart0,
+ blsp0_uart1, blsp1_i2c0, blsp1_i2c1, blsp1_spi0, blsp1_spi1,
+ blsp1_uart0, blsp1_uart1, blsp1_uart2, blsp2_i2c0, blsp2_i2c1,
+ blsp2_spi, blsp2_spi0, blsp2_spi1, btss, burn0, burn1, cri_trng,
+ cri_trng0, cri_trng1, cxc_clk, cxc_data, dbg_out, eud_gpio,
+ gcc_plltest, gcc_tlmm, gpio, led0, led2, mac0, mac1, mdc, mdio,
+ pcie0_clk, pcie0_wake, pcie1_clk, pcie1_wake, pll_test,
+ prng_rosc, pwm0, pwm1, pwm2, pwm3, qdss_cti_trig_in_a0,
+ qdss_cti_trig_in_a1, qdss_cti_trig_in_b0, qdss_cti_trig_in_b1,
+ qdss_cti_trig_out_a0, qdss_cti_trig_out_a1,
+ qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, qdss_traceclk_a,
+ qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b,
+ qdss_tracedata_a, qdss_tracedata_b, qspi_clk, qspi_cs,
+ qspi_data, reset_out, sdc1_clk, sdc1_cmd, sdc1_data, wci_txd,
+ wci_rxd, wsa_swrm, wsi_clk3, wsi_data3, wsis_reset, xfem ]
+
+ required:
+ - pins
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ tlmm: pinctrl@1000000 {
+ compatible = "qcom,ipq5018-tlmm";
+ reg = <0x01000000 0x300000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 47>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+
+ uart-w-state {
+ rx-pins {
+ pins = "gpio33";
+ function = "blsp1_uart1";
+ bias-pull-down;
+ };
+
+ tx-pins {
+ pins = "gpio34";
+ function = "blsp1_uart1";
+ bias-pull-down;
+ };
+ };
+ };
+...
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [v9 4/8] pinctrl: qcom: Add IPQ5018 pinctrl driver
2023-06-08 12:21 [v9 0/8] Add minimal boot support for IPQ5018 Sricharan Ramabadhran
` (2 preceding siblings ...)
2023-06-08 12:21 ` [v9 3/8] dt-bindings: pinctrl: qcom: Add support for ipq5018 Sricharan Ramabadhran
@ 2023-06-08 12:21 ` Sricharan Ramabadhran
2023-06-09 7:01 ` Linus Walleij
2023-06-08 12:21 ` [v9 5/8] dt-bindings: qcom: Add ipq5018 bindings Sricharan Ramabadhran
` (3 subsequent siblings)
7 siblings, 1 reply; 13+ messages in thread
From: Sricharan Ramabadhran @ 2023-06-08 12:21 UTC (permalink / raw)
To: agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, ulf.hansson,
linus.walleij, catalin.marinas, will, p.zabel, linux-arm-msm,
devicetree, linux-kernel, linux-mmc, linux-gpio,
linux-arm-kernel, robimarko, krzysztof.kozlowski,
andy.shevchenko, quic_srichara
Add pinctrl definitions for the TLMM of IPQ5018.
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Co-developed-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
Co-developed-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
---
drivers/pinctrl/qcom/Kconfig | 11 +
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-ipq5018.c | 783 +++++++++++++++++++++++++
3 files changed, 795 insertions(+)
create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq5018.c
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 28b19458b20d..726ab6960b34 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -39,6 +39,17 @@ config PINCTRL_IPQ4019
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm IPQ4019 platform.
+config PINCTRL_IPQ5018
+ tristate "Qualcomm Technologies, Inc. IPQ5018 pin controller driver"
+ depends on OF || COMPILE_TEST
+ depends on ARM64 || COMPILE_TEST
+ select PINCTRL_MSM
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for
+ the Qualcomm Technologies Inc. TLMM block found on the
+ Qualcomm Technologies Inc. IPQ5018 platform. Select this for
+ IPQ5018.
+
config PINCTRL_IPQ8064
tristate "Qualcomm IPQ8064 pin controller driver"
depends on OF
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 3e1fdf46c0ca..426ddbf35f32 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -4,6 +4,7 @@ obj-$(CONFIG_PINCTRL_MSM) += pinctrl-msm.o
obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o
obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o
obj-$(CONFIG_PINCTRL_IPQ4019) += pinctrl-ipq4019.o
+obj-$(CONFIG_PINCTRL_IPQ5018) += pinctrl-ipq5018.o
obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o
obj-$(CONFIG_PINCTRL_IPQ5332) += pinctrl-ipq5332.o
obj-$(CONFIG_PINCTRL_IPQ8074) += pinctrl-ipq8074.o
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq5018.c b/drivers/pinctrl/qcom/pinctrl-ipq5018.c
new file mode 100644
index 000000000000..ed58f750f1eb
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-ipq5018.c
@@ -0,0 +1,783 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2019-2021, 2023 The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/module.h>
+#include <linux/mod_devicetable.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-msm.h"
+
+#define REG_SIZE 0x1000
+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
+ { \
+ .grp = PINCTRL_PINGROUP("gpio" #id, \
+ gpio##id##_pins, \
+ ARRAY_SIZE(gpio##id##_pins)), \
+ .funcs = (int[]){ \
+ msm_mux_gpio, /* gpio mode */ \
+ msm_mux_##f1, \
+ msm_mux_##f2, \
+ msm_mux_##f3, \
+ msm_mux_##f4, \
+ msm_mux_##f5, \
+ msm_mux_##f6, \
+ msm_mux_##f7, \
+ msm_mux_##f8, \
+ msm_mux_##f9 \
+ }, \
+ .nfuncs = 10, \
+ .ctl_reg = REG_SIZE * id, \
+ .io_reg = 0x4 + REG_SIZE * id, \
+ .intr_cfg_reg = 0x8 + REG_SIZE * id, \
+ .intr_status_reg = 0xc + REG_SIZE * id, \
+ .intr_target_reg = 0x8 + REG_SIZE * id, \
+ .mux_bit = 2, \
+ .pull_bit = 0, \
+ .drv_bit = 6, \
+ .oe_bit = 9, \
+ .in_bit = 0, \
+ .out_bit = 1, \
+ .intr_enable_bit = 0, \
+ .intr_status_bit = 0, \
+ .intr_target_bit = 5, \
+ .intr_target_kpss_val = 3, \
+ .intr_raw_status_bit = 4, \
+ .intr_polarity_bit = 1, \
+ .intr_detection_bit = 2, \
+ .intr_detection_width = 2, \
+ }
+
+static const struct pinctrl_pin_desc ipq5018_pins[] = {
+ PINCTRL_PIN(0, "GPIO_0"),
+ PINCTRL_PIN(1, "GPIO_1"),
+ PINCTRL_PIN(2, "GPIO_2"),
+ PINCTRL_PIN(3, "GPIO_3"),
+ PINCTRL_PIN(4, "GPIO_4"),
+ PINCTRL_PIN(5, "GPIO_5"),
+ PINCTRL_PIN(6, "GPIO_6"),
+ PINCTRL_PIN(7, "GPIO_7"),
+ PINCTRL_PIN(8, "GPIO_8"),
+ PINCTRL_PIN(9, "GPIO_9"),
+ PINCTRL_PIN(10, "GPIO_10"),
+ PINCTRL_PIN(11, "GPIO_11"),
+ PINCTRL_PIN(12, "GPIO_12"),
+ PINCTRL_PIN(13, "GPIO_13"),
+ PINCTRL_PIN(14, "GPIO_14"),
+ PINCTRL_PIN(15, "GPIO_15"),
+ PINCTRL_PIN(16, "GPIO_16"),
+ PINCTRL_PIN(17, "GPIO_17"),
+ PINCTRL_PIN(18, "GPIO_18"),
+ PINCTRL_PIN(19, "GPIO_19"),
+ PINCTRL_PIN(20, "GPIO_20"),
+ PINCTRL_PIN(21, "GPIO_21"),
+ PINCTRL_PIN(22, "GPIO_22"),
+ PINCTRL_PIN(23, "GPIO_23"),
+ PINCTRL_PIN(24, "GPIO_24"),
+ PINCTRL_PIN(25, "GPIO_25"),
+ PINCTRL_PIN(26, "GPIO_26"),
+ PINCTRL_PIN(27, "GPIO_27"),
+ PINCTRL_PIN(28, "GPIO_28"),
+ PINCTRL_PIN(29, "GPIO_29"),
+ PINCTRL_PIN(30, "GPIO_30"),
+ PINCTRL_PIN(31, "GPIO_31"),
+ PINCTRL_PIN(32, "GPIO_32"),
+ PINCTRL_PIN(33, "GPIO_33"),
+ PINCTRL_PIN(34, "GPIO_34"),
+ PINCTRL_PIN(35, "GPIO_35"),
+ PINCTRL_PIN(36, "GPIO_36"),
+ PINCTRL_PIN(37, "GPIO_37"),
+ PINCTRL_PIN(38, "GPIO_38"),
+ PINCTRL_PIN(39, "GPIO_39"),
+ PINCTRL_PIN(40, "GPIO_40"),
+ PINCTRL_PIN(41, "GPIO_41"),
+ PINCTRL_PIN(42, "GPIO_42"),
+ PINCTRL_PIN(43, "GPIO_43"),
+ PINCTRL_PIN(44, "GPIO_44"),
+ PINCTRL_PIN(45, "GPIO_45"),
+ PINCTRL_PIN(46, "GPIO_46"),
+};
+
+#define DECLARE_MSM_GPIO_PINS(pin) \
+ static const unsigned int gpio##pin##_pins[] = { pin }
+DECLARE_MSM_GPIO_PINS(0);
+DECLARE_MSM_GPIO_PINS(1);
+DECLARE_MSM_GPIO_PINS(2);
+DECLARE_MSM_GPIO_PINS(3);
+DECLARE_MSM_GPIO_PINS(4);
+DECLARE_MSM_GPIO_PINS(5);
+DECLARE_MSM_GPIO_PINS(6);
+DECLARE_MSM_GPIO_PINS(7);
+DECLARE_MSM_GPIO_PINS(8);
+DECLARE_MSM_GPIO_PINS(9);
+DECLARE_MSM_GPIO_PINS(10);
+DECLARE_MSM_GPIO_PINS(11);
+DECLARE_MSM_GPIO_PINS(12);
+DECLARE_MSM_GPIO_PINS(13);
+DECLARE_MSM_GPIO_PINS(14);
+DECLARE_MSM_GPIO_PINS(15);
+DECLARE_MSM_GPIO_PINS(16);
+DECLARE_MSM_GPIO_PINS(17);
+DECLARE_MSM_GPIO_PINS(18);
+DECLARE_MSM_GPIO_PINS(19);
+DECLARE_MSM_GPIO_PINS(20);
+DECLARE_MSM_GPIO_PINS(21);
+DECLARE_MSM_GPIO_PINS(22);
+DECLARE_MSM_GPIO_PINS(23);
+DECLARE_MSM_GPIO_PINS(24);
+DECLARE_MSM_GPIO_PINS(25);
+DECLARE_MSM_GPIO_PINS(26);
+DECLARE_MSM_GPIO_PINS(27);
+DECLARE_MSM_GPIO_PINS(28);
+DECLARE_MSM_GPIO_PINS(29);
+DECLARE_MSM_GPIO_PINS(30);
+DECLARE_MSM_GPIO_PINS(31);
+DECLARE_MSM_GPIO_PINS(32);
+DECLARE_MSM_GPIO_PINS(33);
+DECLARE_MSM_GPIO_PINS(34);
+DECLARE_MSM_GPIO_PINS(35);
+DECLARE_MSM_GPIO_PINS(36);
+DECLARE_MSM_GPIO_PINS(37);
+DECLARE_MSM_GPIO_PINS(38);
+DECLARE_MSM_GPIO_PINS(39);
+DECLARE_MSM_GPIO_PINS(40);
+DECLARE_MSM_GPIO_PINS(41);
+DECLARE_MSM_GPIO_PINS(42);
+DECLARE_MSM_GPIO_PINS(43);
+DECLARE_MSM_GPIO_PINS(44);
+DECLARE_MSM_GPIO_PINS(45);
+DECLARE_MSM_GPIO_PINS(46);
+
+enum ipq5018_functions {
+ msm_mux_atest_char,
+ msm_mux_audio_pdm0,
+ msm_mux_audio_pdm1,
+ msm_mux_audio_rxbclk,
+ msm_mux_audio_rxd,
+ msm_mux_audio_rxfsync,
+ msm_mux_audio_rxmclk,
+ msm_mux_audio_txbclk,
+ msm_mux_audio_txd,
+ msm_mux_audio_txfsync,
+ msm_mux_audio_txmclk,
+ msm_mux_blsp0_i2c,
+ msm_mux_blsp0_spi,
+ msm_mux_blsp0_uart0,
+ msm_mux_blsp0_uart1,
+ msm_mux_blsp1_i2c0,
+ msm_mux_blsp1_i2c1,
+ msm_mux_blsp1_spi0,
+ msm_mux_blsp1_spi1,
+ msm_mux_blsp1_uart0,
+ msm_mux_blsp1_uart1,
+ msm_mux_blsp1_uart2,
+ msm_mux_blsp2_i2c0,
+ msm_mux_blsp2_i2c1,
+ msm_mux_blsp2_spi,
+ msm_mux_blsp2_spi0,
+ msm_mux_blsp2_spi1,
+ msm_mux_btss,
+ msm_mux_burn0,
+ msm_mux_burn1,
+ msm_mux_cri_trng,
+ msm_mux_cri_trng0,
+ msm_mux_cri_trng1,
+ msm_mux_cxc_clk,
+ msm_mux_cxc_data,
+ msm_mux_dbg_out,
+ msm_mux_eud_gpio,
+ msm_mux_gcc_plltest,
+ msm_mux_gcc_tlmm,
+ msm_mux_gpio,
+ msm_mux_led0,
+ msm_mux_led2,
+ msm_mux_mac0,
+ msm_mux_mac1,
+ msm_mux_mdc,
+ msm_mux_mdio,
+ msm_mux_pcie0_clk,
+ msm_mux_pcie0_wake,
+ msm_mux_pcie1_clk,
+ msm_mux_pcie1_wake,
+ msm_mux_pll_test,
+ msm_mux_prng_rosc,
+ msm_mux_pwm0,
+ msm_mux_pwm1,
+ msm_mux_pwm2,
+ msm_mux_pwm3,
+ msm_mux_qdss_cti_trig_in_a0,
+ msm_mux_qdss_cti_trig_in_a1,
+ msm_mux_qdss_cti_trig_in_b0,
+ msm_mux_qdss_cti_trig_in_b1,
+ msm_mux_qdss_cti_trig_out_a0,
+ msm_mux_qdss_cti_trig_out_a1,
+ msm_mux_qdss_cti_trig_out_b0,
+ msm_mux_qdss_cti_trig_out_b1,
+ msm_mux_qdss_traceclk_a,
+ msm_mux_qdss_traceclk_b,
+ msm_mux_qdss_tracectl_a,
+ msm_mux_qdss_tracectl_b,
+ msm_mux_qdss_tracedata_a,
+ msm_mux_qdss_tracedata_b,
+ msm_mux_qspi_clk,
+ msm_mux_qspi_cs,
+ msm_mux_qspi_data,
+ msm_mux_reset_out,
+ msm_mux_sdc1_clk,
+ msm_mux_sdc1_cmd,
+ msm_mux_sdc1_data,
+ msm_mux_wci_txd,
+ msm_mux_wci_rxd,
+ msm_mux_wsa_swrm,
+ msm_mux_wsi_clk3,
+ msm_mux_wsi_data3,
+ msm_mux_wsis_reset,
+ msm_mux_xfem,
+ msm_mux__,
+};
+
+static const char * const atest_char_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio37",
+};
+
+static const char * const _groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
+ "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
+ "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
+ "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
+ "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
+ "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio44", "gpio45", "gpio46",
+};
+
+static const char * const wci_txd_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3",
+ "gpio42", "gpio43", "gpio44", "gpio45",
+};
+
+static const char * const wci_rxd_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3",
+ "gpio42", "gpio43", "gpio44", "gpio45",
+};
+
+static const char * const xfem_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3",
+ "gpio42", "gpio43", "gpio44", "gpio45",
+};
+
+static const char * const qdss_cti_trig_out_a0_groups[] = {
+ "gpio0",
+};
+
+static const char * const qdss_cti_trig_in_a0_groups[] = {
+ "gpio1",
+};
+
+static const char * const qdss_cti_trig_out_a1_groups[] = {
+ "gpio2",
+};
+
+static const char * const qdss_cti_trig_in_a1_groups[] = {
+ "gpio3",
+};
+
+static const char * const sdc1_data_groups[] = {
+ "gpio4", "gpio5", "gpio6", "gpio7",
+};
+
+static const char * const qspi_data_groups[] = {
+ "gpio4",
+ "gpio5",
+ "gpio6",
+ "gpio7",
+};
+
+static const char * const blsp1_spi1_groups[] = {
+ "gpio4", "gpio5", "gpio6", "gpio7",
+};
+
+static const char * const btss_groups[] = {
+ "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", "gpio17", "gpio18",
+ "gpio19", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
+};
+
+static const char * const dbg_out_groups[] = {
+ "gpio4",
+};
+
+static const char * const qdss_traceclk_a_groups[] = {
+ "gpio4",
+};
+
+static const char * const burn0_groups[] = {
+ "gpio4",
+};
+
+static const char * const cxc_clk_groups[] = {
+ "gpio5",
+};
+
+static const char * const blsp1_i2c1_groups[] = {
+ "gpio5", "gpio6",
+};
+
+static const char * const qdss_tracectl_a_groups[] = {
+ "gpio5",
+};
+
+static const char * const burn1_groups[] = {
+ "gpio5",
+};
+
+static const char * const cxc_data_groups[] = {
+ "gpio6",
+};
+
+static const char * const qdss_tracedata_a_groups[] = {
+ "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", "gpio12",
+ "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19",
+ "gpio20", "gpio21",
+};
+
+static const char * const mac0_groups[] = {
+ "gpio7",
+};
+
+static const char * const sdc1_cmd_groups[] = {
+ "gpio8",
+};
+
+static const char * const qspi_cs_groups[] = {
+ "gpio8",
+};
+
+static const char * const mac1_groups[] = {
+ "gpio8",
+};
+
+static const char * const sdc1_clk_groups[] = {
+ "gpio9",
+};
+
+static const char * const qspi_clk_groups[] = {
+ "gpio9",
+};
+
+static const char * const blsp0_spi_groups[] = {
+ "gpio10", "gpio11", "gpio12", "gpio13",
+};
+
+static const char * const blsp1_uart0_groups[] = {
+ "gpio10", "gpio11", "gpio12", "gpio13",
+};
+
+static const char * const gcc_plltest_groups[] = {
+ "gpio10", "gpio12",
+};
+
+static const char * const gcc_tlmm_groups[] = {
+ "gpio11",
+};
+
+static const char * const blsp0_i2c_groups[] = {
+ "gpio12", "gpio13",
+};
+
+static const char * const pcie0_clk_groups[] = {
+ "gpio14",
+};
+
+static const char * const cri_trng0_groups[] = {
+ "gpio14",
+};
+
+static const char * const cri_trng1_groups[] = {
+ "gpio15",
+};
+
+static const char * const pcie0_wake_groups[] = {
+ "gpio16",
+};
+
+static const char * const cri_trng_groups[] = {
+ "gpio16",
+};
+
+static const char * const pcie1_clk_groups[] = {
+ "gpio17",
+};
+
+static const char * const prng_rosc_groups[] = {
+ "gpio17",
+};
+
+static const char * const blsp1_spi0_groups[] = {
+ "gpio18", "gpio19", "gpio20", "gpio21",
+};
+
+static const char * const pcie1_wake_groups[] = {
+ "gpio19",
+};
+
+static const char * const blsp1_i2c0_groups[] = {
+ "gpio19", "gpio20",
+};
+
+static const char * const blsp0_uart0_groups[] = {
+ "gpio20", "gpio21",
+};
+
+static const char * const pll_test_groups[] = {
+ "gpio22",
+};
+
+static const char * const eud_gpio_groups[] = {
+ "gpio22", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
+};
+
+static const char * const audio_rxmclk_groups[] = {
+ "gpio23", "gpio23",
+};
+
+static const char * const audio_pdm0_groups[] = {
+ "gpio23", "gpio24",
+};
+
+static const char * const blsp2_spi1_groups[] = {
+ "gpio23", "gpio24", "gpio25", "gpio26",
+};
+
+static const char * const blsp1_uart2_groups[] = {
+ "gpio23", "gpio24", "gpio25", "gpio26",
+};
+
+static const char * const qdss_tracedata_b_groups[] = {
+ "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
+ "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
+ "gpio37", "gpio38",
+};
+
+static const char * const audio_rxbclk_groups[] = {
+ "gpio24",
+};
+
+static const char * const audio_rxfsync_groups[] = {
+ "gpio25",
+};
+
+static const char * const audio_pdm1_groups[] = {
+ "gpio25", "gpio26",
+};
+
+static const char * const blsp2_i2c1_groups[] = {
+ "gpio25", "gpio26",
+};
+
+static const char * const audio_rxd_groups[] = {
+ "gpio26",
+};
+
+static const char * const audio_txmclk_groups[] = {
+ "gpio27", "gpio27",
+};
+
+static const char * const wsa_swrm_groups[] = {
+ "gpio27", "gpio28",
+};
+
+static const char * const blsp2_spi_groups[] = {
+ "gpio27",
+};
+
+static const char * const audio_txbclk_groups[] = {
+ "gpio28",
+};
+
+static const char * const blsp0_uart1_groups[] = {
+ "gpio28", "gpio29",
+};
+
+static const char * const audio_txfsync_groups[] = {
+ "gpio29",
+};
+
+static const char * const audio_txd_groups[] = {
+ "gpio30",
+};
+
+static const char * const wsis_reset_groups[] = {
+ "gpio30",
+};
+
+static const char * const blsp2_spi0_groups[] = {
+ "gpio31", "gpio32", "gpio33", "gpio34",
+};
+
+static const char * const blsp1_uart1_groups[] = {
+ "gpio31", "gpio32", "gpio33", "gpio34",
+};
+
+static const char * const blsp2_i2c0_groups[] = {
+ "gpio33", "gpio34",
+};
+
+static const char * const mdc_groups[] = {
+ "gpio36",
+};
+
+static const char * const wsi_clk3_groups[] = {
+ "gpio36",
+};
+
+static const char * const mdio_groups[] = {
+ "gpio37",
+};
+
+static const char * const wsi_data3_groups[] = {
+ "gpio37",
+};
+
+static const char * const qdss_traceclk_b_groups[] = {
+ "gpio39",
+};
+
+static const char * const reset_out_groups[] = {
+ "gpio40",
+};
+
+static const char * const qdss_tracectl_b_groups[] = {
+ "gpio40",
+};
+
+static const char * const pwm0_groups[] = {
+ "gpio42",
+};
+
+static const char * const qdss_cti_trig_out_b0_groups[] = {
+ "gpio42",
+};
+
+static const char * const pwm1_groups[] = {
+ "gpio43",
+};
+
+static const char * const qdss_cti_trig_in_b0_groups[] = {
+ "gpio43",
+};
+
+static const char * const pwm2_groups[] = {
+ "gpio44",
+};
+
+static const char * const qdss_cti_trig_out_b1_groups[] = {
+ "gpio44",
+};
+
+static const char * const pwm3_groups[] = {
+ "gpio45",
+};
+
+static const char * const qdss_cti_trig_in_b1_groups[] = {
+ "gpio45",
+};
+
+static const char * const led0_groups[] = {
+ "gpio46", "gpio30", "gpio10",
+};
+
+static const char * const led2_groups[] = {
+ "gpio30",
+};
+
+static const char * const gpio_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
+ "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
+ "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
+ "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
+ "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
+ "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio44", "gpio45", "gpio46",
+};
+
+static const struct pinfunction ipq5018_functions[] = {
+ MSM_PIN_FUNCTION(atest_char),
+ MSM_PIN_FUNCTION(audio_pdm0),
+ MSM_PIN_FUNCTION(audio_pdm1),
+ MSM_PIN_FUNCTION(audio_rxbclk),
+ MSM_PIN_FUNCTION(audio_rxd),
+ MSM_PIN_FUNCTION(audio_rxfsync),
+ MSM_PIN_FUNCTION(audio_rxmclk),
+ MSM_PIN_FUNCTION(audio_txbclk),
+ MSM_PIN_FUNCTION(audio_txd),
+ MSM_PIN_FUNCTION(audio_txfsync),
+ MSM_PIN_FUNCTION(audio_txmclk),
+ MSM_PIN_FUNCTION(blsp0_i2c),
+ MSM_PIN_FUNCTION(blsp0_spi),
+ MSM_PIN_FUNCTION(blsp0_uart0),
+ MSM_PIN_FUNCTION(blsp0_uart1),
+ MSM_PIN_FUNCTION(blsp1_i2c0),
+ MSM_PIN_FUNCTION(blsp1_i2c1),
+ MSM_PIN_FUNCTION(blsp1_spi0),
+ MSM_PIN_FUNCTION(blsp1_spi1),
+ MSM_PIN_FUNCTION(blsp1_uart0),
+ MSM_PIN_FUNCTION(blsp1_uart1),
+ MSM_PIN_FUNCTION(blsp1_uart2),
+ MSM_PIN_FUNCTION(blsp2_i2c0),
+ MSM_PIN_FUNCTION(blsp2_i2c1),
+ MSM_PIN_FUNCTION(blsp2_spi),
+ MSM_PIN_FUNCTION(blsp2_spi0),
+ MSM_PIN_FUNCTION(blsp2_spi1),
+ MSM_PIN_FUNCTION(btss),
+ MSM_PIN_FUNCTION(burn0),
+ MSM_PIN_FUNCTION(burn1),
+ MSM_PIN_FUNCTION(cri_trng),
+ MSM_PIN_FUNCTION(cri_trng0),
+ MSM_PIN_FUNCTION(cri_trng1),
+ MSM_PIN_FUNCTION(cxc_clk),
+ MSM_PIN_FUNCTION(cxc_data),
+ MSM_PIN_FUNCTION(dbg_out),
+ MSM_PIN_FUNCTION(eud_gpio),
+ MSM_PIN_FUNCTION(gcc_plltest),
+ MSM_PIN_FUNCTION(gcc_tlmm),
+ MSM_PIN_FUNCTION(gpio),
+ MSM_PIN_FUNCTION(led0),
+ MSM_PIN_FUNCTION(led2),
+ MSM_PIN_FUNCTION(mac0),
+ MSM_PIN_FUNCTION(mac1),
+ MSM_PIN_FUNCTION(mdc),
+ MSM_PIN_FUNCTION(mdio),
+ MSM_PIN_FUNCTION(pcie0_clk),
+ MSM_PIN_FUNCTION(pcie0_wake),
+ MSM_PIN_FUNCTION(pcie1_clk),
+ MSM_PIN_FUNCTION(pcie1_wake),
+ MSM_PIN_FUNCTION(pll_test),
+ MSM_PIN_FUNCTION(prng_rosc),
+ MSM_PIN_FUNCTION(pwm0),
+ MSM_PIN_FUNCTION(pwm1),
+ MSM_PIN_FUNCTION(pwm2),
+ MSM_PIN_FUNCTION(pwm3),
+ MSM_PIN_FUNCTION(qdss_cti_trig_in_a0),
+ MSM_PIN_FUNCTION(qdss_cti_trig_in_a1),
+ MSM_PIN_FUNCTION(qdss_cti_trig_in_b0),
+ MSM_PIN_FUNCTION(qdss_cti_trig_in_b1),
+ MSM_PIN_FUNCTION(qdss_cti_trig_out_a0),
+ MSM_PIN_FUNCTION(qdss_cti_trig_out_a1),
+ MSM_PIN_FUNCTION(qdss_cti_trig_out_b0),
+ MSM_PIN_FUNCTION(qdss_cti_trig_out_b1),
+ MSM_PIN_FUNCTION(qdss_traceclk_a),
+ MSM_PIN_FUNCTION(qdss_traceclk_b),
+ MSM_PIN_FUNCTION(qdss_tracectl_a),
+ MSM_PIN_FUNCTION(qdss_tracectl_b),
+ MSM_PIN_FUNCTION(qdss_tracedata_a),
+ MSM_PIN_FUNCTION(qdss_tracedata_b),
+ MSM_PIN_FUNCTION(qspi_clk),
+ MSM_PIN_FUNCTION(qspi_cs),
+ MSM_PIN_FUNCTION(qspi_data),
+ MSM_PIN_FUNCTION(reset_out),
+ MSM_PIN_FUNCTION(sdc1_clk),
+ MSM_PIN_FUNCTION(sdc1_cmd),
+ MSM_PIN_FUNCTION(sdc1_data),
+ MSM_PIN_FUNCTION(wci_txd),
+ MSM_PIN_FUNCTION(wci_rxd),
+ MSM_PIN_FUNCTION(wsa_swrm),
+ MSM_PIN_FUNCTION(wsi_clk3),
+ MSM_PIN_FUNCTION(wsi_data3),
+ MSM_PIN_FUNCTION(wsis_reset),
+ MSM_PIN_FUNCTION(xfem),
+};
+
+static const struct msm_pingroup ipq5018_groups[] = {
+ PINGROUP(0, atest_char, _, qdss_cti_trig_out_a0, wci_txd, wci_rxd, xfem, _, _, _),
+ PINGROUP(1, atest_char, _, qdss_cti_trig_in_a0, wci_txd, wci_rxd, xfem, _, _, _),
+ PINGROUP(2, atest_char, _, qdss_cti_trig_out_a1, wci_txd, wci_rxd, xfem, _, _, _),
+ PINGROUP(3, atest_char, _, qdss_cti_trig_in_a1, wci_txd, wci_rxd, xfem, _, _, _),
+ PINGROUP(4, sdc1_data, qspi_data, blsp1_spi1, btss, dbg_out, qdss_traceclk_a, _, burn0, _),
+ PINGROUP(5, sdc1_data, qspi_data, cxc_clk, blsp1_spi1, blsp1_i2c1, btss, _, qdss_tracectl_a, _),
+ PINGROUP(6, sdc1_data, qspi_data, cxc_data, blsp1_spi1, blsp1_i2c1, btss, _, qdss_tracedata_a, _),
+ PINGROUP(7, sdc1_data, qspi_data, mac0, blsp1_spi1, btss, _, qdss_tracedata_a, _, _),
+ PINGROUP(8, sdc1_cmd, qspi_cs, mac1, btss, _, qdss_tracedata_a, _, _, _),
+ PINGROUP(9, sdc1_clk, qspi_clk, _, qdss_tracedata_a, _, _, _, _, _),
+ PINGROUP(10, blsp0_spi, blsp1_uart0, led0, gcc_plltest, qdss_tracedata_a, _, _, _, _),
+ PINGROUP(11, blsp0_spi, blsp1_uart0, _, gcc_tlmm, qdss_tracedata_a, _, _, _, _),
+ PINGROUP(12, blsp0_spi, blsp0_i2c, blsp1_uart0, _, gcc_plltest, qdss_tracedata_a, _, _, _),
+ PINGROUP(13, blsp0_spi, blsp0_i2c, blsp1_uart0, _, qdss_tracedata_a, _, _, _, _),
+ PINGROUP(14, pcie0_clk, _, _, cri_trng0, qdss_tracedata_a, _, _, _, _),
+ PINGROUP(15, _, _, cri_trng1, qdss_tracedata_a, _, _, _, _, _),
+ PINGROUP(16, pcie0_wake, _, _, cri_trng, qdss_tracedata_a, _, _, _, _),
+ PINGROUP(17, pcie1_clk, btss, _, prng_rosc, qdss_tracedata_a, _, _, _, _),
+ PINGROUP(18, blsp1_spi0, btss, _, qdss_tracedata_a, _, _, _, _, _),
+ PINGROUP(19, pcie1_wake, blsp1_spi0, blsp1_i2c0, btss, _, qdss_tracedata_a, _, _, _),
+ PINGROUP(20, blsp0_uart0, blsp1_spi0, blsp1_i2c0, _, qdss_tracedata_a, _, _, _, _),
+ PINGROUP(21, blsp0_uart0, blsp1_spi0, _, qdss_tracedata_a, _, _, _, _, _),
+ PINGROUP(22, _, pll_test, eud_gpio, _, _, _, _, _, _),
+ PINGROUP(23, audio_rxmclk, audio_pdm0, audio_rxmclk, blsp2_spi1, blsp1_uart2, btss, _, qdss_tracedata_b, _),
+ PINGROUP(24, audio_rxbclk, audio_pdm0, blsp2_spi1, blsp1_uart2, btss, _, qdss_tracedata_b, _, _),
+ PINGROUP(25, audio_rxfsync, audio_pdm1, blsp2_i2c1, blsp2_spi1, blsp1_uart2, btss, _, qdss_tracedata_b, _),
+ PINGROUP(26, audio_rxd, audio_pdm1, blsp2_i2c1, blsp2_spi1, blsp1_uart2, btss, _, qdss_tracedata_b, _),
+ PINGROUP(27, audio_txmclk, wsa_swrm, audio_txmclk, blsp2_spi, btss, _, qdss_tracedata_b, _, _),
+ PINGROUP(28, audio_txbclk, wsa_swrm, blsp0_uart1, btss, qdss_tracedata_b, _, _, _, _),
+ PINGROUP(29, audio_txfsync, _, blsp0_uart1, _, qdss_tracedata_b, _, _, _, _),
+ PINGROUP(30, audio_txd, led2, led0, _, _, _, _, _, _),
+ PINGROUP(31, blsp2_spi0, blsp1_uart1, _, qdss_tracedata_b, eud_gpio, _, _, _, _),
+ PINGROUP(32, blsp2_spi0, blsp1_uart1, _, qdss_tracedata_b, eud_gpio, _, _, _, _),
+ PINGROUP(33, blsp2_i2c0, blsp2_spi0, blsp1_uart1, _, qdss_tracedata_b, eud_gpio, _, _, _),
+ PINGROUP(34, blsp2_i2c0, blsp2_spi0, blsp1_uart1, _, qdss_tracedata_b, eud_gpio, _, _, _),
+ PINGROUP(35, _, qdss_tracedata_b, eud_gpio, _, _, _, _, _, _),
+ PINGROUP(36, mdc, qdss_tracedata_b, _, wsi_clk3, _, _, _, _, _),
+ PINGROUP(37, mdio, atest_char, qdss_tracedata_b, _, wsi_data3, _, _, _, _),
+ PINGROUP(38, qdss_tracedata_b, _, _, _, _, _, _, _, _),
+ PINGROUP(39, qdss_traceclk_b, _, _, _, _, _, _, _, _),
+ PINGROUP(40, reset_out, qdss_tracectl_b, _, _, _, _, _, _, _),
+ PINGROUP(41, _, _, _, _, _, _, _, _, _),
+ PINGROUP(42, pwm0, qdss_cti_trig_out_b0, wci_txd, wci_rxd, xfem, _, _, _, _),
+ PINGROUP(43, pwm1, qdss_cti_trig_in_b0, wci_txd, wci_rxd, xfem, _, _, _, _),
+ PINGROUP(44, pwm2, qdss_cti_trig_out_b1, wci_txd, wci_rxd, xfem, _, _, _, _),
+ PINGROUP(45, pwm3, qdss_cti_trig_in_b1, wci_txd, wci_rxd, xfem, _, _, _, _),
+ PINGROUP(46, led0, _, _, _, _, _, _, _, _),
+};
+
+static const struct msm_pinctrl_soc_data ipq5018_pinctrl = {
+ .pins = ipq5018_pins,
+ .npins = ARRAY_SIZE(ipq5018_pins),
+ .functions = ipq5018_functions,
+ .nfunctions = ARRAY_SIZE(ipq5018_functions),
+ .groups = ipq5018_groups,
+ .ngroups = ARRAY_SIZE(ipq5018_groups),
+ .ngpios = 47,
+};
+
+static int ipq5018_pinctrl_probe(struct platform_device *pdev)
+{
+ return msm_pinctrl_probe(pdev, &ipq5018_pinctrl);
+}
+
+static const struct of_device_id ipq5018_pinctrl_of_match[] = {
+ { .compatible = "qcom,ipq5018-tlmm", },
+ { }
+};
+MODULE_DEVICE_TABLE(of, ipq5018_pinctrl_of_match);
+
+static struct platform_driver ipq5018_pinctrl_driver = {
+ .driver = {
+ .name = "ipq5018-tlmm",
+ .of_match_table = ipq5018_pinctrl_of_match,
+ },
+ .probe = ipq5018_pinctrl_probe,
+ .remove = msm_pinctrl_remove,
+};
+
+static int __init ipq5018_pinctrl_init(void)
+{
+ return platform_driver_register(&ipq5018_pinctrl_driver);
+}
+arch_initcall(ipq5018_pinctrl_init);
+
+static void __exit ipq5018_pinctrl_exit(void)
+{
+ platform_driver_unregister(&ipq5018_pinctrl_driver);
+}
+module_exit(ipq5018_pinctrl_exit);
+
+MODULE_DESCRIPTION("Qualcomm Technologies Inc ipq5018 pinctrl driver");
+MODULE_LICENSE("GPL");
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [v9 5/8] dt-bindings: qcom: Add ipq5018 bindings
2023-06-08 12:21 [v9 0/8] Add minimal boot support for IPQ5018 Sricharan Ramabadhran
` (3 preceding siblings ...)
2023-06-08 12:21 ` [v9 4/8] pinctrl: qcom: Add IPQ5018 pinctrl driver Sricharan Ramabadhran
@ 2023-06-08 12:21 ` Sricharan Ramabadhran
2023-06-08 12:21 ` [v9 6/8] dt-bindings: scm: Add compatible for IPQ5018 Sricharan Ramabadhran
` (2 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Sricharan Ramabadhran @ 2023-06-08 12:21 UTC (permalink / raw)
To: agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, ulf.hansson,
linus.walleij, catalin.marinas, will, p.zabel, linux-arm-msm,
devicetree, linux-kernel, linux-mmc, linux-gpio,
linux-arm-kernel, robimarko, krzysztof.kozlowski,
andy.shevchenko, quic_srichara
Document the new ipq5018 SOC/board device tree bindings.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
---
Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 8302d1ee280d..8026a0c40ef9 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -30,6 +30,7 @@ description: |
apq8084
apq8096
ipq4018
+ ipq5018
ipq5332
ipq6018
ipq8074
@@ -101,6 +102,7 @@ description: |
hk10-c2
idp
liquid
+ rdp432-c2
mtp
qrd
rb2
@@ -335,6 +337,11 @@ properties:
- qcom,ipq4019-dk04.1-c1
- const: qcom,ipq4019
+ - items:
+ - enum:
+ - qcom,ipq5018-rdp432-c2
+ - const: qcom,ipq5018
+
- items:
- enum:
- qcom,ipq5332-ap-mi01.2
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [v9 6/8] dt-bindings: scm: Add compatible for IPQ5018
2023-06-08 12:21 [v9 0/8] Add minimal boot support for IPQ5018 Sricharan Ramabadhran
` (4 preceding siblings ...)
2023-06-08 12:21 ` [v9 5/8] dt-bindings: qcom: Add ipq5018 bindings Sricharan Ramabadhran
@ 2023-06-08 12:21 ` Sricharan Ramabadhran
2023-06-08 12:21 ` [v9 7/8] arm64: dts: Add ipq5018 SoC and rdp432-c2 board support Sricharan Ramabadhran
2023-06-08 12:21 ` [v9 8/8] arm64: defconfig: Enable IPQ5018 SoC base configs Sricharan Ramabadhran
7 siblings, 0 replies; 13+ messages in thread
From: Sricharan Ramabadhran @ 2023-06-08 12:21 UTC (permalink / raw)
To: agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, ulf.hansson,
linus.walleij, catalin.marinas, will, p.zabel, linux-arm-msm,
devicetree, linux-kernel, linux-mmc, linux-gpio,
linux-arm-kernel, robimarko, krzysztof.kozlowski,
andy.shevchenko, quic_srichara
From: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
Add the scm compatible string for IPQ5018 SoC
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
---
Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
index 367d04ad1923..ec5f5c0170b5 100644
--- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
+++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
@@ -24,6 +24,7 @@ properties:
- qcom,scm-apq8064
- qcom,scm-apq8084
- qcom,scm-ipq4019
+ - qcom,scm-ipq5018
- qcom,scm-ipq5332
- qcom,scm-ipq6018
- qcom,scm-ipq806x
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [v9 7/8] arm64: dts: Add ipq5018 SoC and rdp432-c2 board support
2023-06-08 12:21 [v9 0/8] Add minimal boot support for IPQ5018 Sricharan Ramabadhran
` (5 preceding siblings ...)
2023-06-08 12:21 ` [v9 6/8] dt-bindings: scm: Add compatible for IPQ5018 Sricharan Ramabadhran
@ 2023-06-08 12:21 ` Sricharan Ramabadhran
2023-06-08 12:21 ` [v9 8/8] arm64: defconfig: Enable IPQ5018 SoC base configs Sricharan Ramabadhran
7 siblings, 0 replies; 13+ messages in thread
From: Sricharan Ramabadhran @ 2023-06-08 12:21 UTC (permalink / raw)
To: agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, ulf.hansson,
linus.walleij, catalin.marinas, will, p.zabel, linux-arm-msm,
devicetree, linux-kernel, linux-mmc, linux-gpio,
linux-arm-kernel, robimarko, krzysztof.kozlowski,
andy.shevchenko, quic_srichara
Add initial device tree support for the Qualcomm IPQ5018 SoC and
rdp432-c2 board.
Few things like 'reboot' does not work because, couple of more 'SCM'
APIS are needed to clear some TrustZone settings. Those will be
posted separately.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Co-developed-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Co-developed-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
.../arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts | 72 +++++
arch/arm64/boot/dts/qcom/ipq5018.dtsi | 250 ++++++++++++++++++
3 files changed, 323 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
create mode 100644 arch/arm64/boot/dts/qcom/ipq5018.dtsi
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 4f9e81253e18..a2572f4a3729 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -4,6 +4,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8039-t2.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
+dtb-$(CONFIG_ARCH_QCOM) += ipq5018-rdp432-c2.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq5332-mi01.2.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp442.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp468.dtb
diff --git a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
new file mode 100644
index 000000000000..e636a1cb9b77
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * IPQ5018 MP03.1-C2 board device tree source
+ *
+ * Copyright (c) 2023 The Linux Foundation. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "ipq5018.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ5018/AP-RDP432.1-C2";
+ compatible = "qcom,ipq5018-rdp432-c2", "qcom,ipq5018";
+
+ aliases {
+ serial0 = &blsp1_uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&blsp1_uart1 {
+ pinctrl-0 = <&uart1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&sdhc_1 {
+ pinctrl-0 = <&sdc_default_state>;
+ pinctrl-names = "default";
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ max-frequency = <192000000>;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&sleep_clk {
+ clock-frequency = <32000>;
+};
+
+&tlmm {
+ sdc_default_state: sdc-default-state {
+ clk-pins {
+ pins = "gpio9";
+ function = "sdc1_clk";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "gpio8";
+ function = "sdc1_cmd";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "gpio4", "gpio5", "gpio6", "gpio7";
+ function = "sdc1_data";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ };
+};
+
+&xo_board_clk {
+ clock-frequency = <24000000>;
+};
diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
new file mode 100644
index 000000000000..9f13d2dcdfd5
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
@@ -0,0 +1,250 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * IPQ5018 SoC device tree source
+ *
+ * Copyright (c) 2023 The Linux Foundation. All rights reserved.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,gcc-ipq5018.h>
+#include <dt-bindings/reset/qcom,gcc-ipq5018.h>
+
+/ {
+ interrupt-parent = <&intc>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clocks {
+ sleep_clk: sleep-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ xo_board_clk: xo-board-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+
+ L2_0: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <0x80000>;
+ cache-unified;
+ };
+ };
+
+ firmware {
+ scm {
+ compatible = "qcom,scm-ipq5018", "qcom,scm";
+ };
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the size */
+ reg = <0x0 0x40000000 0x0 0x0>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ tz_region: tz@4ac00000 {
+ reg = <0x0 0x4ac00000 0x0 0x200000>;
+ no-map;
+ };
+ };
+
+ soc: soc@0 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0xffffffff>;
+
+ tlmm: pinctrl@1000000 {
+ compatible = "qcom,ipq5018-tlmm";
+ reg = <0x01000000 0x300000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 47>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ uart1_pins: uart1-state {
+ pins = "gpio31", "gpio32", "gpio33", "gpio34";
+ function = "blsp1_uart1";
+ drive-strength = <8>;
+ bias-pull-down;
+ };
+ };
+
+ gcc: clock-controller@1800000 {
+ compatible = "qcom,gcc-ipq5018";
+ reg = <0x01800000 0x80000>;
+ clocks = <&xo_board_clk>,
+ <&sleep_clk>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ sdhc_1: mmc@7804000 {
+ compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0x7804000 0x1000>;
+ reg-names = "hc";
+
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
+ <&xo_board_clk>;
+ clock-names = "iface", "core", "xo";
+ non-removable;
+ status = "disabled";
+ };
+
+ blsp1_uart1: serial@78af000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x078af000 0x200>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
+ intc: interrupt-controller@b000000 {
+ compatible = "qcom,msm-qgic2";
+ reg = <0x0b000000 0x1000>, /* GICD */
+ <0x0b002000 0x2000>, /* GICC */
+ <0x0b001000 0x1000>, /* GICH */
+ <0x0b004000 0x2000>; /* GICV */
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0b00a000 0x1ffa>;
+
+ v2m0: v2m@0 {
+ compatible = "arm,gic-v2m-frame";
+ reg = <0x00000000 0xff8>;
+ msi-controller;
+ };
+
+ v2m1: v2m@1000 {
+ compatible = "arm,gic-v2m-frame";
+ reg = <0x00001000 0xff8>;
+ msi-controller;
+ };
+ };
+
+ timer@b120000 {
+ compatible = "arm,armv7-timer-mem";
+ reg = <0x0b120000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ frame@b120000 {
+ reg = <0x0b121000 0x1000>,
+ <0x0b122000 0x1000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <0>;
+ };
+
+ frame@b123000 {
+ reg = <0xb123000 0x1000>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <1>;
+ status = "disabled";
+ };
+
+ frame@b124000 {
+ frame-number = <2>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0b124000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@b125000 {
+ reg = <0x0b125000 0x1000>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <3>;
+ status = "disabled";
+ };
+
+ frame@b126000 {
+ reg = <0x0b126000 0x1000>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <4>;
+ status = "disabled";
+ };
+
+ frame@b127000 {
+ reg = <0x0b127000 0x1000>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <5>;
+ status = "disabled";
+ };
+
+ frame@b128000 {
+ reg = <0x0b128000 0x1000>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <6>;
+ status = "disabled";
+ };
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [v9 8/8] arm64: defconfig: Enable IPQ5018 SoC base configs
2023-06-08 12:21 [v9 0/8] Add minimal boot support for IPQ5018 Sricharan Ramabadhran
` (6 preceding siblings ...)
2023-06-08 12:21 ` [v9 7/8] arm64: dts: Add ipq5018 SoC and rdp432-c2 board support Sricharan Ramabadhran
@ 2023-06-08 12:21 ` Sricharan Ramabadhran
7 siblings, 0 replies; 13+ messages in thread
From: Sricharan Ramabadhran @ 2023-06-08 12:21 UTC (permalink / raw)
To: agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, ulf.hansson,
linus.walleij, catalin.marinas, will, p.zabel, linux-arm-msm,
devicetree, linux-kernel, linux-mmc, linux-gpio,
linux-arm-kernel, robimarko, krzysztof.kozlowski,
andy.shevchenko, quic_srichara
Enables clk & pinctrl related configs
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
---
arch/arm64/configs/defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index e05706d3893d..d6b2667f1baa 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -557,6 +557,7 @@ CONFIG_PINCTRL_IMX8ULP=y
CONFIG_PINCTRL_IMX93=y
CONFIG_PINCTRL_MSM=y
CONFIG_PINCTRL_IPQ8074=y
+CONFIG_PINCTRL_IPQ5018=y
CONFIG_PINCTRL_IPQ5332=y
CONFIG_PINCTRL_IPQ6018=y
CONFIG_PINCTRL_IPQ9574=y
@@ -1168,6 +1169,8 @@ CONFIG_QCOM_CLK_SMD_RPM=y
CONFIG_QCOM_CLK_RPMH=y
CONFIG_IPQ_APSS_6018=y
CONFIG_IPQ_GCC_5332=y
+CONFIG_IPQ_APSS_5018=y
+CONFIG_IPQ_GCC_5018=y
CONFIG_IPQ_GCC_6018=y
CONFIG_IPQ_GCC_8074=y
CONFIG_IPQ_GCC_9574=y
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [v9 3/8] dt-bindings: pinctrl: qcom: Add support for ipq5018
2023-06-08 12:21 ` [v9 3/8] dt-bindings: pinctrl: qcom: Add support for ipq5018 Sricharan Ramabadhran
@ 2023-06-09 7:00 ` Linus Walleij
0 siblings, 0 replies; 13+ messages in thread
From: Linus Walleij @ 2023-06-09 7:00 UTC (permalink / raw)
To: Sricharan Ramabadhran
Cc: agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, ulf.hansson,
catalin.marinas, will, p.zabel, linux-arm-msm, devicetree,
linux-kernel, linux-mmc, linux-gpio, linux-arm-kernel, robimarko,
krzysztof.kozlowski, andy.shevchenko
On Thu, Jun 8, 2023 at 2:23 PM Sricharan Ramabadhran
<quic_srichara@quicinc.com> wrote:
> Add device tree binding Documentation details for ipq5018
> pinctrl driver.
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Co-developed-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
> Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
> Co-developed-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Patch applied to the pinctrl tree for v6.5.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [v9 4/8] pinctrl: qcom: Add IPQ5018 pinctrl driver
2023-06-08 12:21 ` [v9 4/8] pinctrl: qcom: Add IPQ5018 pinctrl driver Sricharan Ramabadhran
@ 2023-06-09 7:01 ` Linus Walleij
0 siblings, 0 replies; 13+ messages in thread
From: Linus Walleij @ 2023-06-09 7:01 UTC (permalink / raw)
To: Sricharan Ramabadhran
Cc: agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, ulf.hansson,
catalin.marinas, will, p.zabel, linux-arm-msm, devicetree,
linux-kernel, linux-mmc, linux-gpio, linux-arm-kernel, robimarko,
krzysztof.kozlowski, andy.shevchenko
On Thu, Jun 8, 2023 at 2:23 PM Sricharan Ramabadhran
<quic_srichara@quicinc.com> wrote:
> Add pinctrl definitions for the TLMM of IPQ5018.
>
> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
> Co-developed-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
> Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
> Co-developed-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Patch applied to the pinctrl tree for v6.5.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [v9 2/8] clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018
2023-06-08 12:21 ` [v9 2/8] clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018 Sricharan Ramabadhran
@ 2023-06-09 13:52 ` Konrad Dybcio
2023-06-11 4:49 ` Sricharan Ramabadhran
0 siblings, 1 reply; 13+ messages in thread
From: Konrad Dybcio @ 2023-06-09 13:52 UTC (permalink / raw)
To: Sricharan Ramabadhran, agross, andersson, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, ulf.hansson,
linus.walleij, catalin.marinas, will, p.zabel, linux-arm-msm,
devicetree, linux-kernel, linux-mmc, linux-gpio,
linux-arm-kernel, robimarko, krzysztof.kozlowski,
andy.shevchenko
On 8.06.2023 14:21, Sricharan Ramabadhran wrote:
> Add support for the global clock controller found on IPQ5018
> based devices.
>
> Co-developed-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> Co-developed-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
> Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> ---
> [v9] Sorted the headers and cleaned the unwanted ones
> Added trailing comma for .parent_hws member
> Removed the hunk touching ipq5332 kconfig (unintentionally)
>
You did not address the comments I made in v4.
https://lore.kernel.org/linux-arm-msm/21a5642c-e6e5-9323-7db1-383a18616ac0@linaro.org/
Konrad
> drivers/clk/qcom/Kconfig | 8 +
> drivers/clk/qcom/Makefile | 1 +
> drivers/clk/qcom/gcc-ipq5018.c | 3724 ++++++++++++++++++++++++++++++++
> 3 files changed, 3733 insertions(+)
> create mode 100644 drivers/clk/qcom/gcc-ipq5018.c
>
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 9cd1f05d436b..8ed74fa007e5 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -145,6 +145,14 @@ config IPQ_GCC_4019
> Say Y if you want to use peripheral devices such as UART, SPI,
> i2c, USB, SD/eMMC, etc.
>
> +config IPQ_GCC_5018
> + tristate "IPQ5018 Global Clock Controller"
> + depends on ARM64 || COMPILE_TEST
> + help
> + Support for global clock controller on ipq5018 devices.
> + Say Y if you want to use peripheral devices such as UART, SPI,
> + i2c, USB, SD/eMMC, etc.
> +
> config IPQ_GCC_5332
> tristate "IPQ5332 Global Clock Controller"
> depends on ARM64 || COMPILE_TEST
> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> index 75d035150118..1393ee62d8cf 100644
> --- a/drivers/clk/qcom/Makefile
> +++ b/drivers/clk/qcom/Makefile
> @@ -24,6 +24,7 @@ obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o
> obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o
> obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o
> obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
> +obj-$(CONFIG_IPQ_GCC_5018) += gcc-ipq5018.o
> obj-$(CONFIG_IPQ_GCC_5332) += gcc-ipq5332.o
> obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
> obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
> diff --git a/drivers/clk/qcom/gcc-ipq5018.c b/drivers/clk/qcom/gcc-ipq5018.c
> new file mode 100644
> index 000000000000..96f5cac180cb
> --- /dev/null
> +++ b/drivers/clk/qcom/gcc-ipq5018.c
> @@ -0,0 +1,3724 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Copyright (c) 2023, The Linux Foundation. All rights reserved.
> + */
> +#include <linux/clk-provider.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/regmap.h>
> +
> +#include <dt-bindings/clock/qcom,gcc-ipq5018.h>
> +#include <dt-bindings/reset/qcom,gcc-ipq5018.h>
> +
> +#include "clk-alpha-pll.h"
> +#include "clk-branch.h"
> +#include "clk-rcg.h"
> +#include "clk-regmap.h"
> +#include "clk-regmap-divider.h"
> +#include "clk-regmap-mux.h"
> +#include "clk-regmap-phy-mux.h"
> +#include "reset.h"
> +
> +/* Need to match the order of clocks in DT binding */
> +enum {
> + DT_XO,
> + DT_SLEEP_CLK,
> + DT_PCIE20_PHY0_PIPE_CLK,
> + DT_PCIE20_PHY1_PIPE_CLK,
> + DT_USB3_PHY0_CC_PIPE_CLK,
> + DT_GEPHY_RX_CLK,
> + DT_GEPHY_TX_CLK,
> + DT_UNIPHY_RX_CLK,
> + DT_UNIPHY_TX_CLK,
> +};
> +
> +enum {
> + P_XO,
> + P_CORE_PI_SLEEP_CLK,
> + P_PCIE20_PHY0_PIPE,
> + P_PCIE20_PHY1_PIPE,
> + P_USB3PHY_0_PIPE,
> + P_GEPHY_RX,
> + P_GEPHY_TX,
> + P_UNIPHY_RX,
> + P_UNIPHY_TX,
> + P_GPLL0,
> + P_GPLL0_DIV2,
> + P_GPLL2,
> + P_GPLL4,
> + P_UBI32_PLL,
> +};
> +
> +static const struct clk_parent_data gcc_xo_data[] = {
> + { .index = DT_XO },
> +};
> +
> +static const struct clk_parent_data gcc_sleep_clk_data[] = {
> + { .index = DT_SLEEP_CLK },
> +};
> +
> +static struct clk_alpha_pll gpll0_main = {
> + .offset = 0x21000,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> + .clkr = {
> + .enable_reg = 0x0b000,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gpll0_main",
> + .parent_data = gcc_xo_data,
> + .num_parents = ARRAY_SIZE(gcc_xo_data),
> + .ops = &clk_alpha_pll_stromer_ops,
> + },
> + },
> +};
> +
> +static struct clk_alpha_pll gpll2_main = {
> + .offset = 0x4a000,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> + .clkr = {
> + .enable_reg = 0x0b000,
> + .enable_mask = BIT(2),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gpll2_main",
> + .parent_data = gcc_xo_data,
> + .num_parents = ARRAY_SIZE(gcc_xo_data),
> + .ops = &clk_alpha_pll_stromer_ops,
> + },
> + },
> +};
> +
> +static struct clk_alpha_pll gpll4_main = {
> + .offset = 0x24000,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> + .clkr = {
> + .enable_reg = 0x0b000,
> + .enable_mask = BIT(5),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gpll4_main",
> + .parent_data = gcc_xo_data,
> + .num_parents = ARRAY_SIZE(gcc_xo_data),
> + .ops = &clk_alpha_pll_stromer_ops,
> + },
> + },
> +};
> +
> +static struct clk_alpha_pll ubi32_pll_main = {
> + .offset = 0x25000,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> + .clkr = {
> + .enable_reg = 0x0b000,
> + .enable_mask = BIT(6),
> + .hw.init = &(struct clk_init_data) {
> + .name = "ubi32_pll_main",
> + .parent_data = gcc_xo_data,
> + .num_parents = ARRAY_SIZE(gcc_xo_data),
> + .ops = &clk_alpha_pll_stromer_ops,
> + },
> + },
> +};
> +
> +static struct clk_alpha_pll_postdiv gpll0 = {
> + .offset = 0x21000,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> + .width = 4,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "gpll0",
> + .parent_hws = (const struct clk_hw *[]) {
> + &gpll0_main.clkr.hw,
> + },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_postdiv_ro_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_alpha_pll_postdiv gpll2 = {
> + .offset = 0x4a000,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> + .width = 4,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "gpll2",
> + .parent_hws = (const struct clk_hw *[]) {
> + &gpll2_main.clkr.hw,
> + },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_postdiv_ro_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_alpha_pll_postdiv gpll4 = {
> + .offset = 0x24000,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> + .width = 4,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "gpll4",
> + .parent_hws = (const struct clk_hw *[]) {
> + &gpll4_main.clkr.hw,
> + },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_postdiv_ro_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_alpha_pll_postdiv ubi32_pll = {
> + .offset = 0x25000,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> + .width = 4,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "ubi32_pll",
> + .parent_hws = (const struct clk_hw *[]) {
> + &ubi32_pll_main.clkr.hw,
> + },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_postdiv_ro_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_fixed_factor gpll0_out_main_div2 = {
> + .mult = 1,
> + .div = 2,
> + .hw.init = &(struct clk_init_data) {
> + .name = "gpll0_out_main_div2",
> + .parent_hws = (const struct clk_hw *[]) {
> + &gpll0_main.clkr.hw,
> + },
> + .num_parents = 1,
> + .ops = &clk_fixed_factor_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = {
> + { .index = DT_XO },
> + { .hw = &gpll0.clkr.hw },
> + { .hw = &gpll0_out_main_div2.hw },
> +};
> +
> +static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
> + { P_XO, 0 },
> + { P_GPLL0, 1 },
> + { P_GPLL0_DIV2, 4 },
> +};
> +
> +static const struct clk_parent_data gcc_xo_gpll0[] = {
> + { .index = DT_XO },
> + { .hw = &gpll0.clkr.hw },
> +};
> +
> +static const struct parent_map gcc_xo_gpll0_map[] = {
> + { P_XO, 0 },
> + { P_GPLL0, 1 },
> +};
> +
> +static const struct clk_parent_data gcc_xo_gpll0_out_main_div2_gpll0[] = {
> + { .index = DT_XO },
> + { .hw = &gpll0_out_main_div2.hw },
> + { .hw = &gpll0.clkr.hw },
> +};
> +
> +static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
> + { P_XO, 0 },
> + { P_GPLL0_DIV2, 2 },
> + { P_GPLL0, 1 },
> +};
> +
> +static const struct clk_parent_data gcc_xo_ubi32_gpll0[] = {
> + { .index = DT_XO },
> + { .hw = &ubi32_pll.clkr.hw },
> + { .hw = &gpll0.clkr.hw },
> +};
> +
> +static const struct parent_map gcc_xo_ubi32_gpll0_map[] = {
> + { P_XO, 0 },
> + { P_UBI32_PLL, 1 },
> + { P_GPLL0, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_xo_gpll0_gpll2[] = {
> + { .index = DT_XO },
> + { .hw = &gpll0.clkr.hw },
> + { .hw = &gpll2.clkr.hw },
> +};
> +
> +static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {
> + { P_XO, 0 },
> + { P_GPLL0, 1 },
> + { P_GPLL2, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll4[] = {
> + { .index = DT_XO },
> + { .hw = &gpll0.clkr.hw },
> + { .hw = &gpll2.clkr.hw },
> + { .hw = &gpll4.clkr.hw },
> +};
> +
> +static const struct parent_map gcc_xo_gpll0_gpll2_gpll4_map[] = {
> + { P_XO, 0 },
> + { P_GPLL0, 1 },
> + { P_GPLL2, 2 },
> + { P_GPLL4, 3 },
> +};
> +
> +static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
> + { .index = DT_XO },
> + { .hw = &gpll0.clkr.hw },
> + { .hw = &gpll4.clkr.hw },
> +};
> +
> +static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
> + { P_XO, 0 },
> + { P_GPLL0, 1 },
> + { P_GPLL4, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_xo_gpll0_core_pi_sleep_clk[] = {
> + { .index = DT_XO },
> + { .hw = &gpll0.clkr.hw },
> + { .index = DT_SLEEP_CLK },
> +};
> +
> +static const struct parent_map gcc_xo_gpll0_core_pi_sleep_clk_map[] = {
> + { P_XO, 0 },
> + { P_GPLL0, 2 },
> + { P_CORE_PI_SLEEP_CLK, 6 },
> +};
> +
> +static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk[] = {
> + { .index = DT_XO },
> + { .hw = &gpll0.clkr.hw },
> + { .hw = &gpll0_out_main_div2.hw },
> + { .index = DT_SLEEP_CLK },
> +};
> +
> +static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map[] = {
> + { P_XO, 0 },
> + { P_GPLL0, 1 },
> + { P_GPLL0_DIV2, 4 },
> + { P_CORE_PI_SLEEP_CLK, 6 },
> +};
> +
> +static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
> + { .index = DT_XO },
> + { .hw = &gpll0.clkr.hw },
> + { .hw = &gpll2.clkr.hw },
> + { .hw = &gpll0_out_main_div2.hw },
> +};
> +
> +static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
> + { P_XO, 0 },
> + { P_GPLL0, 1 },
> + { P_GPLL2, 2 },
> + { P_GPLL0_DIV2, 4 },
> +};
> +
> +static const struct clk_parent_data gcc_xo_gpll4_gpll0_gpll0_out_main_div2[] = {
> + { .index = DT_XO },
> + { .hw = &gpll4.clkr.hw },
> + { .hw = &gpll0.clkr.hw },
> + { .hw = &gpll0_out_main_div2.hw },
> +};
> +
> +static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1[] = {
> + { P_XO, 0 },
> + { P_GPLL4, 1 },
> + { P_GPLL0, 2 },
> + { P_GPLL0_DIV2, 4 },
> +};
> +
> +static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map2[] = {
> + { P_XO, 0 },
> + { P_GPLL4, 1 },
> + { P_GPLL0, 3 },
> + { P_GPLL0_DIV2, 4 },
> +};
> +
> +static const struct clk_parent_data gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0[] = {
> + { .index = DT_XO },
> + { .index = DT_GEPHY_RX_CLK },
> + { .index = DT_GEPHY_TX_CLK },
> + { .hw = &ubi32_pll.clkr.hw },
> + { .hw = &gpll0.clkr.hw },
> +};
> +
> +static const struct parent_map gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0_map[] = {
> + { P_XO, 0 },
> + { P_GEPHY_RX, 1 },
> + { P_GEPHY_TX, 2 },
> + { P_UBI32_PLL, 3 },
> + { P_GPLL0, 4 },
> +};
> +
> +static const struct clk_parent_data gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0[] = {
> + { .index = DT_XO },
> + { .index = DT_GEPHY_TX_CLK },
> + { .index = DT_GEPHY_RX_CLK },
> + { .hw = &ubi32_pll.clkr.hw },
> + { .hw = &gpll0.clkr.hw },
> +};
> +
> +static const struct parent_map gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0_map[] = {
> + { P_XO, 0 },
> + { P_GEPHY_TX, 1 },
> + { P_GEPHY_RX, 2 },
> + { P_UBI32_PLL, 3 },
> + { P_GPLL0, 4 },
> +};
> +
> +static const struct clk_parent_data gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0[] = {
> + { .index = DT_XO },
> + { .index = DT_UNIPHY_RX_CLK },
> + { .index = DT_UNIPHY_TX_CLK },
> + { .hw = &ubi32_pll.clkr.hw },
> + { .hw = &gpll0.clkr.hw },
> +};
> +
> +static const struct parent_map gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0_map[] = {
> + { P_XO, 0 },
> + { P_UNIPHY_RX, 1 },
> + { P_UNIPHY_TX, 2 },
> + { P_UBI32_PLL, 3 },
> + { P_GPLL0, 4 },
> +};
> +
> +static const struct clk_parent_data gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0[] = {
> + { .index = DT_XO },
> + { .index = DT_UNIPHY_TX_CLK },
> + { .index = DT_UNIPHY_RX_CLK },
> + { .hw = &ubi32_pll.clkr.hw },
> + { .hw = &gpll0.clkr.hw },
> +};
> +
> +static const struct parent_map gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0_map[] = {
> + { P_XO, 0 },
> + { P_UNIPHY_TX, 1 },
> + { P_UNIPHY_RX, 2 },
> + { P_UBI32_PLL, 3 },
> + { P_GPLL0, 4 },
> +};
> +
> +static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = {
> + { .index = DT_PCIE20_PHY0_PIPE_CLK },
> + { .index = DT_XO },
> +};
> +
> +static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = {
> + { P_PCIE20_PHY0_PIPE, 0 },
> + { P_XO, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_pcie20_phy1_pipe_clk_xo[] = {
> + { .index = DT_PCIE20_PHY1_PIPE_CLK },
> + { .index = DT_XO },
> +};
> +
> +static const struct parent_map gcc_pcie20_phy1_pipe_clk_xo_map[] = {
> + { P_PCIE20_PHY1_PIPE, 0 },
> + { P_XO, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {
> + { .index = DT_USB3_PHY0_CC_PIPE_CLK },
> + { .index = DT_XO },
> +};
> +
> +static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
> + { P_USB3PHY_0_PIPE, 0 },
> + { P_XO, 2 },
> +};
> +
> +static const struct freq_tbl ftbl_adss_pwm_clk_src[] = {
> + F(24000000, P_XO, 1, 0, 0),
> + F(100000000, P_GPLL0, 8, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 adss_pwm_clk_src = {
> + .cmd_rcgr = 0x1f008,
> + .freq_tbl = ftbl_adss_pwm_clk_src,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "adss_pwm_clk_src",
> + .parent_data = gcc_xo_gpll0,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_apss_axi_clk_src[] = {
> + F(400000000, P_GPLL0, 2, 0, 0),
> + { }
> +};
> +
> +static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = {
> + F(50000000, P_GPLL0, 16, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
> + .cmd_rcgr = 0x0200c,
> + .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "blsp1_qup1_i2c_apps_clk_src",
> + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
> + .cmd_rcgr = 0x03000,
> + .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "blsp1_qup2_i2c_apps_clk_src",
> + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
> + .cmd_rcgr = 0x04000,
> + .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "blsp1_qup3_i2c_apps_clk_src",
> + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = {
> + F(960000, P_XO, 10, 2, 5),
> + F(4800000, P_XO, 5, 0, 0),
> + F(9600000, P_XO, 2, 4, 5),
> + F(16000000, P_GPLL0, 10, 1, 5),
> + F(24000000, P_XO, 1, 0, 0),
> + F(50000000, P_GPLL0, 16, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
> + .cmd_rcgr = 0x02024,
> + .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "blsp1_qup1_spi_apps_clk_src",
> + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
> + .cmd_rcgr = 0x03014,
> + .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "blsp1_qup2_spi_apps_clk_src",
> + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
> + .cmd_rcgr = 0x04014,
> + .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "blsp1_qup3_spi_apps_clk_src",
> + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = {
> + F(3686400, P_GPLL0_DIV2, 1, 144, 15625),
> + F(7372800, P_GPLL0_DIV2, 1, 288, 15625),
> + F(14745600, P_GPLL0_DIV2, 1, 576, 15625),
> + F(24000000, P_XO, 1, 0, 0),
> + F(25000000, P_GPLL0, 16, 1, 2),
> + F(40000000, P_GPLL0, 1, 1, 20),
> + F(46400000, P_GPLL0, 1, 29, 500),
> + F(48000000, P_GPLL0, 1, 3, 50),
> + F(51200000, P_GPLL0, 1, 8, 125),
> + F(56000000, P_GPLL0, 1, 7, 100),
> + F(58982400, P_GPLL0, 1, 1152, 15625),
> + F(60000000, P_GPLL0, 1, 3, 40),
> + F(64000000, P_GPLL0, 10, 4, 5),
> + { }
> +};
> +
> +static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
> + .cmd_rcgr = 0x02044,
> + .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "blsp1_uart1_apps_clk_src",
> + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
> + .cmd_rcgr = 0x03034,
> + .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "blsp1_uart2_apps_clk_src",
> + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_crypto_clk_src[] = {
> + F(160000000, P_GPLL0, 5, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 crypto_clk_src = {
> + .cmd_rcgr = 0x16004,
> + .freq_tbl = ftbl_crypto_clk_src,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "crypto_clk_src",
> + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gmac0_tx_clk_src[] = {
> + F(2500000, P_GEPHY_TX, 5, 0, 0),
> + F(24000000, P_XO, 1, 0, 0),
> + F(25000000, P_GEPHY_TX, 5, 0, 0),
> + F(125000000, P_GEPHY_TX, 1, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gmac0_rx_clk_src = {
> + .cmd_rcgr = 0x68020,
> + .parent_map = gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0_map,
> + .hid_width = 5,
> + .freq_tbl = ftbl_gmac0_tx_clk_src,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "gmac0_rx_clk_src",
> + .parent_data = gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0,
> + .num_parents = ARRAY_SIZE(gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_regmap_div gmac0_rx_div_clk_src = {
> + .reg = 0x68420,
> + .shift = 0,
> + .width = 4,
> + .clkr = {
> + .hw.init = &(struct clk_init_data) {
> + .name = "gmac0_rx_div_clk_src",
> + .parent_hws = (const struct clk_hw *[]) {
> + &gmac0_rx_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .ops = &clk_regmap_div_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> + },
> +};
> +
> +static struct clk_rcg2 gmac0_tx_clk_src = {
> + .cmd_rcgr = 0x68028,
> + .parent_map = gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0_map,
> + .hid_width = 5,
> + .freq_tbl = ftbl_gmac0_tx_clk_src,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "gmac0_tx_clk_src",
> + .parent_data = gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0,
> + .num_parents = ARRAY_SIZE(gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_regmap_div gmac0_tx_div_clk_src = {
> + .reg = 0x68424,
> + .shift = 0,
> + .width = 4,
> + .clkr = {
> + .hw.init = &(struct clk_init_data) {
> + .name = "gmac0_tx_div_clk_src",
> + .parent_hws = (const struct clk_hw *[]) {
> + &gmac0_tx_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .ops = &clk_regmap_div_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gmac1_rx_clk_src[] = {
> + F(2500000, P_UNIPHY_RX, 12.5, 0, 0),
> + F(24000000, P_XO, 1, 0, 0),
> + F(25000000, P_UNIPHY_RX, 2.5, 0, 0),
> + F(125000000, P_UNIPHY_RX, 2.5, 0, 0),
> + F(125000000, P_UNIPHY_RX, 1, 0, 0),
> + F(312500000, P_UNIPHY_RX, 1, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gmac1_rx_clk_src = {
> + .cmd_rcgr = 0x68030,
> + .parent_map = gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0_map,
> + .hid_width = 5,
> + .freq_tbl = ftbl_gmac1_rx_clk_src,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "gmac1_rx_clk_src",
> + .parent_data = gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0,
> + .num_parents = ARRAY_SIZE(gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_regmap_div gmac1_rx_div_clk_src = {
> + .reg = 0x68430,
> + .shift = 0,
> + .width = 4,
> + .clkr = {
> + .hw.init = &(struct clk_init_data) {
> + .name = "gmac1_rx_div_clk_src",
> + .parent_hws = (const struct clk_hw *[]) {
> + &gmac1_rx_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .ops = &clk_regmap_div_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gmac1_tx_clk_src[] = {
> + F(2500000, P_UNIPHY_TX, 12.5, 0, 0),
> + F(24000000, P_XO, 1, 0, 0),
> + F(25000000, P_UNIPHY_TX, 2.5, 0, 0),
> + F(125000000, P_UNIPHY_TX, 2.5, 0, 0),
> + F(125000000, P_UNIPHY_TX, 1, 0, 0),
> + F(312500000, P_UNIPHY_TX, 1, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gmac1_tx_clk_src = {
> + .cmd_rcgr = 0x68038,
> + .parent_map = gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0_map,
> + .hid_width = 5,
> + .freq_tbl = ftbl_gmac1_tx_clk_src,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "gmac1_tx_clk_src",
> + .parent_data = gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0,
> + .num_parents = ARRAY_SIZE(gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_regmap_div gmac1_tx_div_clk_src = {
> + .reg = 0x68434,
> + .shift = 0,
> + .width = 4,
> + .clkr = {
> + .hw.init = &(struct clk_init_data) {
> + .name = "gmac1_tx_div_clk_src",
> + .parent_hws = (const struct clk_hw *[]) {
> + &gmac1_tx_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .ops = &clk_regmap_div_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gmac_clk_src[] = {
> + F(240000000, P_GPLL4, 5, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gmac_clk_src = {
> + .cmd_rcgr = 0x68080,
> + .parent_map = gcc_xo_gpll0_gpll4_map,
> + .hid_width = 5,
> + .freq_tbl = ftbl_gmac_clk_src,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "gmac_clk_src",
> + .parent_data = gcc_xo_gpll0_gpll4,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gp_clk_src[] = {
> + F(200000000, P_GPLL0, 4, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gp1_clk_src = {
> + .cmd_rcgr = 0x08004,
> + .freq_tbl = ftbl_gp_clk_src,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "gp1_clk_src",
> + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 gp2_clk_src = {
> + .cmd_rcgr = 0x09004,
> + .freq_tbl = ftbl_gp_clk_src,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "gp2_clk_src",
> + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 gp3_clk_src = {
> + .cmd_rcgr = 0x0a004,
> + .freq_tbl = ftbl_gp_clk_src,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "gp3_clk_src",
> + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_lpass_axim_clk_src[] = {
> + F(133333334, P_GPLL0, 6, 0, 0),
> + { }
> +};
> +
> +struct clk_rcg2 lpass_axim_clk_src = {
> + .cmd_rcgr = 0x2E028,
> + .freq_tbl = ftbl_lpass_axim_clk_src,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "lpass_axim_clk_src",
> + .parent_data = gcc_xo_gpll0,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_lpass_sway_clk_src[] = {
> + F(66666667, P_GPLL0, 12, 0, 0),
> + { }
> +};
> +
> +struct clk_rcg2 lpass_sway_clk_src = {
> + .cmd_rcgr = 0x2E040,
> + .freq_tbl = ftbl_lpass_sway_clk_src,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "lpass_sway_clk_src",
> + .parent_data = gcc_xo_gpll0,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_pcie0_aux_clk_src[] = {
> + F(2000000, P_XO, 12, 0, 0),
> +};
> +
> +static struct clk_rcg2 pcie0_aux_clk_src = {
> + .cmd_rcgr = 0x75020,
> + .freq_tbl = ftbl_pcie0_aux_clk_src,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "pcie0_aux_clk_src",
> + .parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_pcie0_axi_clk_src[] = {
> + F(240000000, P_GPLL4, 5, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 pcie0_axi_clk_src = {
> + .cmd_rcgr = 0x75050,
> + .freq_tbl = ftbl_pcie0_axi_clk_src,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_gpll4_map,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "pcie0_axi_clk_src",
> + .parent_data = gcc_xo_gpll0_gpll4,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 pcie1_aux_clk_src = {
> + .cmd_rcgr = 0x76020,
> + .freq_tbl = ftbl_pcie0_aux_clk_src,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "pcie1_aux_clk_src",
> + .parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 pcie1_axi_clk_src = {
> + .cmd_rcgr = 0x76050,
> + .freq_tbl = ftbl_gp_clk_src,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "pcie1_axi_clk_src",
> + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_regmap_mux pcie0_pipe_clk_src = {
> + .reg = 0x7501c,
> + .shift = 8,
> + .width = 2,
> + .parent_map = gcc_pcie20_phy0_pipe_clk_xo_map,
> + .clkr = {
> + .hw.init = &(struct clk_init_data) {
> + .name = "pcie0_pipe_clk_src",
> + .parent_data = gcc_pcie20_phy0_pipe_clk_xo,
> + .num_parents = ARRAY_SIZE(gcc_pcie20_phy0_pipe_clk_xo),
> + .ops = &clk_regmap_mux_closest_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> + },
> +};
> +
> +static struct clk_regmap_mux pcie1_pipe_clk_src = {
> + .reg = 0x7601c,
> + .shift = 8,
> + .width = 2,
> + .parent_map = gcc_pcie20_phy1_pipe_clk_xo_map, .clkr = {
> + .hw.init = &(struct clk_init_data) {
> + .name = "pcie1_pipe_clk_src",
> + .parent_data = gcc_pcie20_phy1_pipe_clk_xo,
> + .num_parents = ARRAY_SIZE(gcc_pcie20_phy1_pipe_clk_xo),
> + .ops = &clk_regmap_mux_closest_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> + },
> +};
> +
> +static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = {
> + F(100000000, P_GPLL0, 8, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
> + .cmd_rcgr = 0x27000,
> + .freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "pcnoc_bfdcd_clk_src",
> + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_fixed_factor pcnoc_clk_src = {
> + .mult = 1,
> + .div = 1,
> + .hw.init = &(struct clk_init_data) {
> + .name = "pcnoc_clk_src",
> + .parent_hws = (const struct clk_hw *[]) {
> + &pcnoc_bfdcd_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .ops = &clk_fixed_factor_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_qdss_at_clk_src[] = {
> + F(240000000, P_GPLL4, 5, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 qdss_at_clk_src = {
> + .cmd_rcgr = 0x2900c,
> + .freq_tbl = ftbl_qdss_at_clk_src,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "qdss_at_clk_src",
> + .parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_qdss_stm_clk_src[] = {
> + F(200000000, P_GPLL0, 4, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 qdss_stm_clk_src = {
> + .cmd_rcgr = 0x2902C,
> + .freq_tbl = ftbl_qdss_stm_clk_src,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "qdss_stm_clk_src",
> + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_qdss_traceclkin_clk_src[] = {
> + F(266666667, P_GPLL0, 3, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 qdss_traceclkin_clk_src = {
> + .cmd_rcgr = 0x29048,
> + .freq_tbl = ftbl_qdss_traceclkin_clk_src,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "qdss_traceclkin_clk_src",
> + .parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_qdss_tsctr_clk_src[] = {
> + F(600000000, P_GPLL4, 2, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 qdss_tsctr_clk_src = {
> + .cmd_rcgr = 0x29064,
> + .freq_tbl = ftbl_qdss_tsctr_clk_src,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "qdss_tsctr_clk_src",
> + .parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_fixed_factor qdss_tsctr_div2_clk_src = {
> + .mult = 1,
> + .div = 2,
> + .hw.init = &(struct clk_init_data) {
> + .name = "qdss_tsctr_div2_clk_src",
> + .parent_hws = (const struct clk_hw *[]) {
> + &qdss_tsctr_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_fixed_factor_ops,
> + },
> +};
> +
> +static struct clk_fixed_factor qdss_dap_sync_clk_src = {
> + .mult = 1,
> + .div = 4,
> + .hw.init = &(struct clk_init_data) {
> + .name = "qdss_dap_sync_clk_src",
> + .parent_hws = (const struct clk_hw *[]) {
> + &qdss_tsctr_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .ops = &clk_fixed_factor_ops,
> + },
> +};
> +
> +static struct clk_fixed_factor eud_at_clk_src = {
> + .mult = 1,
> + .div = 6,
> + .hw.init = &(struct clk_init_data) {
> + .name = "eud_at_clk_src",
> + .parent_hws = (const struct clk_hw *[]) {
> + &qdss_at_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .ops = &clk_fixed_factor_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_qpic_io_macro_clk_src[] = {
> + F(24000000, P_XO, 1, 0, 0),
> + F(100000000, P_GPLL0, 8, 0, 0),
> + F(200000000, P_GPLL0, 4, 0, 0),
> + F(320000000, P_GPLL0, 2.5, 0, 0),
> +};
> +
> +static struct clk_rcg2 qpic_io_macro_clk_src = {
> + .cmd_rcgr = 0x57010,
> + .freq_tbl = ftbl_qpic_io_macro_clk_src,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_gpll2_map,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "qpic_io_macro_clk_src",
> + .parent_data = gcc_xo_gpll0_gpll2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
> + F(143713, P_XO, 1, 1, 167),
> + F(400000, P_XO, 1, 1, 60),
> + F(24000000, P_XO, 1, 0, 0),
> + F(48000000, P_GPLL2, 12, 1, 2),
> + F(96000000, P_GPLL2, 12, 0, 0),
> + F(177777778, P_GPLL0, 1, 2, 9),
> + F(192000000, P_GPLL2, 6, 0, 0),
> + F(200000000, P_GPLL0, 4, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 sdcc1_apps_clk_src = {
> + .cmd_rcgr = 0x42004,
> + .freq_tbl = ftbl_sdcc1_apps_clk_src,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "sdcc1_apps_clk_src",
> + .parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
> + .ops = &clk_rcg2_floor_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = {
> + F(266666667, P_GPLL0, 3, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 system_noc_bfdcd_clk_src = {
> + .cmd_rcgr = 0x26004,
> + .freq_tbl = ftbl_system_noc_bfdcd_clk_src,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "system_noc_bfdcd_clk_src",
> + .parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_fixed_factor system_noc_clk_src = {
> + .mult = 1,
> + .div = 1,
> + .hw.init = &(struct clk_init_data) {
> + .name = "system_noc_clk_src",
> + .parent_hws = (const struct clk_hw *[]) {
> + &system_noc_bfdcd_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .ops = &clk_fixed_factor_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_rcg2 ubi0_axi_clk_src = {
> + .cmd_rcgr = 0x68088,
> + .freq_tbl = ftbl_apss_axi_clk_src,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_gpll2_map,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "ubi0_axi_clk_src",
> + .parent_data = gcc_xo_gpll0_gpll2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
> + .ops = &clk_rcg2_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_ubi0_core_clk_src[] = {
> + F(850000000, P_UBI32_PLL, 1, 0, 0),
> + F(1000000000, P_UBI32_PLL, 1, 0, 0),
> +};
> +
> +static struct clk_rcg2 ubi0_core_clk_src = {
> + .cmd_rcgr = 0x68100,
> + .freq_tbl = ftbl_ubi0_core_clk_src,
> + .hid_width = 5,
> + .parent_map = gcc_xo_ubi32_gpll0_map,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "ubi0_core_clk_src",
> + .parent_data = gcc_xo_ubi32_gpll0,
> + .num_parents = ARRAY_SIZE(gcc_xo_ubi32_gpll0),
> + .ops = &clk_rcg2_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_rcg2 usb0_aux_clk_src = {
> + .cmd_rcgr = 0x3e05c,
> + .freq_tbl = ftbl_pcie0_aux_clk_src,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "usb0_aux_clk_src",
> + .parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_usb0_lfps_clk_src[] = {
> + F(25000000, P_GPLL0, 16, 1, 2),
> + { }
> +};
> +
> +static struct clk_rcg2 usb0_lfps_clk_src = {
> + .cmd_rcgr = 0x3e090,
> + .freq_tbl = ftbl_usb0_lfps_clk_src,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "usb0_lfps_clk_src",
> + .parent_data = gcc_xo_gpll0,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 usb0_master_clk_src = {
> + .cmd_rcgr = 0x3e00c,
> + .freq_tbl = ftbl_gp_clk_src,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "usb0_master_clk_src",
> + .parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_usb0_mock_utmi_clk_src[] = {
> + F(60000000, P_GPLL4, 10, 1, 2),
> + { }
> +};
> +
> +static struct clk_rcg2 usb0_mock_utmi_clk_src = {
> + .cmd_rcgr = 0x3e020,
> + .freq_tbl = ftbl_usb0_mock_utmi_clk_src,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map2,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "usb0_mock_utmi_clk_src",
> + .parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_regmap_mux usb0_pipe_clk_src = {
> + .reg = 0x3e048,
> + .shift = 8,
> + .width = 2,
> + .parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map,
> + .clkr = {
> + .hw.init = &(struct clk_init_data) {
> + .name = "usb0_pipe_clk_src",
> + .parent_data = gcc_usb3phy_0_cc_pipe_clk_xo,
> + .num_parents = ARRAY_SIZE(gcc_usb3phy_0_cc_pipe_clk_xo),
> + .ops = &clk_regmap_mux_closest_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> + },
> +};
> +
> +static const struct freq_tbl ftbl_q6_axi_clk_src[] = {
> + F(400000000, P_GPLL0, 2, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 q6_axi_clk_src = {
> + .cmd_rcgr = 0x59120,
> + .freq_tbl = ftbl_q6_axi_clk_src,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_gpll2_gpll4_map,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "q6_axi_clk_src",
> + .parent_data = gcc_xo_gpll0_gpll2_gpll4,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll4),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_wcss_ahb_clk_src[] = {
> + F(133333333, P_GPLL0, 6, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 wcss_ahb_clk_src = {
> + .cmd_rcgr = 0x59020,
> + .freq_tbl = ftbl_wcss_ahb_clk_src,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "wcss_ahb_clk_src",
> + .parent_data = gcc_xo_gpll0,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_branch gcc_sleep_clk_src = {
> + .halt_reg = 0x30000,
> + .clkr = {
> + .enable_reg = 0x30000,
> + .enable_mask = BIT(1),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_sleep_clk_src",
> + .parent_data = gcc_sleep_clk_data,
> + .num_parents = ARRAY_SIZE(gcc_sleep_clk_data),
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_xo_clk_src = {
> + .halt_reg = 0x30018,
> + .clkr = {
> + .enable_reg = 0x30018,
> + .enable_mask = BIT(1),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_xo_clk_src",
> + .parent_data = gcc_xo_data,
> + .num_parents = ARRAY_SIZE(gcc_xo_data),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_xo_clk = {
> + .halt_reg = 0x30030,
> + .clkr = {
> + .enable_reg = 0x30030,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_xo_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &gcc_xo_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_adss_pwm_clk = {
> + .halt_reg = 0x1f020,
> + .clkr = {
> + .enable_reg = 0x1f020,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_adss_pwm_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &adss_pwm_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_ahb_clk = {
> + .halt_reg = 0x01008,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x0b004,
> + .enable_mask = BIT(10),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_blsp1_ahb_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &pcnoc_clk_src.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
> + .halt_reg = 0x02008,
> + .clkr = {
> + .enable_reg = 0x02008,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_blsp1_qup1_i2c_apps_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &blsp1_qup1_i2c_apps_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
> + .halt_reg = 0x02004,
> + .clkr = {
> + .enable_reg = 0x02004,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_blsp1_qup1_spi_apps_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &blsp1_qup1_spi_apps_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
> + .halt_reg = 0x03010,
> + .clkr = {
> + .enable_reg = 0x03010,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_blsp1_qup2_i2c_apps_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &blsp1_qup2_i2c_apps_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
> + .halt_reg = 0x0300c,
> + .clkr = {
> + .enable_reg = 0x0300c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_blsp1_qup2_spi_apps_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &blsp1_qup2_spi_apps_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
> + .halt_reg = 0x04010,
> + .clkr = {
> + .enable_reg = 0x04010,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_blsp1_qup3_i2c_apps_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &blsp1_qup3_i2c_apps_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
> + .halt_reg = 0x0400c,
> + .clkr = {
> + .enable_reg = 0x0400c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_blsp1_qup3_spi_apps_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &blsp1_qup3_spi_apps_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_uart1_apps_clk = {
> + .halt_reg = 0x0203c,
> + .clkr = {
> + .enable_reg = 0x0203c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_blsp1_uart1_apps_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &blsp1_uart1_apps_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_uart2_apps_clk = {
> + .halt_reg = 0x0302c,
> + .clkr = {
> + .enable_reg = 0x0302c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_blsp1_uart2_apps_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &blsp1_uart2_apps_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_btss_lpo_clk = {
> + .halt_reg = 0x1c004,
> + .clkr = {
> + .enable_reg = 0x1c004,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_btss_lpo_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_cmn_blk_ahb_clk = {
> + .halt_reg = 0x56308,
> + .clkr = {
> + .enable_reg = 0x56308,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_cmn_blk_ahb_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &pcnoc_clk_src.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_cmn_blk_sys_clk = {
> + .halt_reg = 0x5630c,
> + .clkr = {
> + .enable_reg = 0x5630c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_cmn_blk_sys_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &gcc_xo_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_crypto_ahb_clk = {
> + .halt_reg = 0x16024,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x0b004,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_crypto_ahb_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &pcnoc_clk_src.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_crypto_axi_clk = {
> + .halt_reg = 0x16020,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x0b004,
> + .enable_mask = BIT(1),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_crypto_axi_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &pcnoc_clk_src.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_crypto_clk = {
> + .halt_reg = 0x1601c,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x0b004,
> + .enable_mask = BIT(2),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_crypto_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &crypto_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_dcc_clk = {
> + .halt_reg = 0x77004,
> + .clkr = {
> + .enable_reg = 0x77004,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_dcc_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &pcnoc_clk_src.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_gephy_rx_clk = {
> + .halt_reg = 0x56010,
> + .halt_check = BRANCH_HALT_DELAY,
> + .clkr = {
> + .enable_reg = 0x56010,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_gephy_rx_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &gmac0_rx_div_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .ops = &clk_branch2_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_gephy_tx_clk = {
> + .halt_reg = 0x56014,
> + .halt_check = BRANCH_HALT_DELAY,
> + .clkr = {
> + .enable_reg = 0x56014,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_gephy_tx_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &gmac0_tx_div_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .ops = &clk_branch2_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_gmac0_cfg_clk = {
> + .halt_reg = 0x68304,
> + .clkr = {
> + .enable_reg = 0x68304,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_gmac0_cfg_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &gmac_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_gmac0_ptp_clk = {
> + .halt_reg = 0x68300,
> + .clkr = {
> + .enable_reg = 0x68300,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_gmac0_ptp_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &gmac_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_gmac0_rx_clk = {
> + .halt_reg = 0x68240,
> + .clkr = {
> + .enable_reg = 0x68240,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_gmac0_rx_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &gmac0_rx_div_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .ops = &clk_branch2_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_gmac0_sys_clk = {
> + .halt_reg = 0x68190,
> + .halt_check = BRANCH_HALT_DELAY,
> + .halt_bit = 31,
> + .clkr = {
> + .enable_reg = 0x683190,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_gmac0_sys_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &gmac_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_gmac0_tx_clk = {
> + .halt_reg = 0x68244,
> + .clkr = {
> + .enable_reg = 0x68244,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_gmac0_tx_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &gmac0_tx_div_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .ops = &clk_branch2_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_gmac1_cfg_clk = {
> + .halt_reg = 0x68324,
> + .clkr = {
> + .enable_reg = 0x68324,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_gmac1_cfg_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &gmac_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_gmac1_ptp_clk = {
> + .halt_reg = 0x68320,
> + .clkr = {
> + .enable_reg = 0x68320,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_gmac1_ptp_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &gmac_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_gmac1_rx_clk = {
> + .halt_reg = 0x68248,
> + .clkr = {
> + .enable_reg = 0x68248,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_gmac1_rx_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &gmac1_rx_div_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .ops = &clk_branch2_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_gmac1_sys_clk = {
> + .halt_reg = 0x68310,
> + .clkr = {
> + .enable_reg = 0x68310,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_gmac1_sys_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &gmac_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_gmac1_tx_clk = {
> + .halt_reg = 0x6824c,
> + .clkr = {
> + .enable_reg = 0x6824c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_gmac1_tx_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &gmac1_tx_div_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .ops = &clk_branch2_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_gp1_clk = {
> + .halt_reg = 0x08000,
> + .clkr = {
> + .enable_reg = 0x08000,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_gp1_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &gp1_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_gp2_clk = {
> + .halt_reg = 0x09000,
> + .clkr = {
> + .enable_reg = 0x09000,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_gp2_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &gp2_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_gp3_clk = {
> + .halt_reg = 0x0a000,
> + .clkr = {
> + .enable_reg = 0x0a000,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_gp3_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &gp3_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_lpass_core_axim_clk = {
> + .halt_reg = 0x2E048,
> + .halt_check = BRANCH_VOTED,
> + .clkr = {
> + .enable_reg = 0x2E048,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_lpass_core_axim_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &lpass_axim_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_lpass_sway_clk = {
> + .halt_reg = 0x2E04C,
> + .clkr = {
> + .enable_reg = 0x2E04C,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_lpass_sway_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &lpass_sway_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_mdio0_ahb_clk = {
> + .halt_reg = 0x58004,
> + .clkr = {
> + .enable_reg = 0x58004,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_mdioi0_ahb_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &pcnoc_clk_src.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_mdio1_ahb_clk = {
> + .halt_reg = 0x58014,
> + .clkr = {
> + .enable_reg = 0x58014,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_mdio1_ahb_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &pcnoc_clk_src.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie0_ahb_clk = {
> + .halt_reg = 0x75010,
> + .clkr = {
> + .enable_reg = 0x75010,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_pcie0_ahb_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &pcnoc_clk_src.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie0_aux_clk = {
> + .halt_reg = 0x75014,
> + .clkr = {
> + .enable_reg = 0x75014,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_pcie0_aux_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &pcie0_aux_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie0_axi_m_clk = {
> + .halt_reg = 0x75008,
> + .clkr = {
> + .enable_reg = 0x75008,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_pcie0_axi_m_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &pcie0_axi_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie0_axi_s_bridge_clk = {
> + .halt_reg = 0x75048,
> + .clkr = {
> + .enable_reg = 0x75048,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_pcie0_axi_s_bridge_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &pcie0_axi_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie0_axi_s_clk = {
> + .halt_reg = 0x7500c,
> + .clkr = {
> + .enable_reg = 0x7500c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_pcie0_axi_s_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &pcie0_axi_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie0_pipe_clk = {
> + .halt_reg = 0x75018,
> + .halt_check = BRANCH_HALT_DELAY,
> + .halt_bit = 31,
> + .clkr = {
> + .enable_reg = 0x75018,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_pcie0_pipe_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &pcie0_pipe_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie1_ahb_clk = {
> + .halt_reg = 0x76010,
> + .clkr = {
> + .enable_reg = 0x76010,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_pcie1_ahb_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &pcnoc_clk_src.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie1_aux_clk = {
> + .halt_reg = 0x76014,
> + .clkr = {
> + .enable_reg = 0x76014,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_pcie1_aux_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &pcie1_aux_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie1_axi_m_clk = {
> + .halt_reg = 0x76008,
> + .clkr = {
> + .enable_reg = 0x76008,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_pcie1_axi_m_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &pcie1_axi_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie1_axi_s_bridge_clk = {
> + .halt_reg = 0x76048,
> + .clkr = {
> + .enable_reg = 0x76048,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_pcie1_axi_s_bridge_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &pcie1_axi_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie1_axi_s_clk = {
> + .halt_reg = 0x7600c,
> + .clkr = {
> + .enable_reg = 0x7600c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_pcie1_axi_s_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &pcie1_axi_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie1_pipe_clk = {
> + .halt_reg = 8,
> + .halt_check = BRANCH_HALT_DELAY,
> + .halt_bit = 31,
> + .clkr = {
> + .enable_reg = 0x76018,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_pcie1_pipe_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &pcie1_pipe_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_prng_ahb_clk = {
> + .halt_reg = 0x13004,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x0b004,
> + .enable_mask = BIT(8),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_prng_ahb_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &pcnoc_clk_src.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_q6_ahb_clk = {
> + .halt_reg = 0x59138,
> + .clkr = {
> + .enable_reg = 0x59138,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_q6_ahb_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &wcss_ahb_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_q6_ahb_s_clk = {
> + .halt_reg = 0x5914C,
> + .clkr = {
> + .enable_reg = 0x5914C,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_q6_ahb_s_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &wcss_ahb_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_q6_axim_clk = {
> + .halt_reg = 0x5913C,
> + .clkr = {
> + .enable_reg = 0x5913C,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_q6_axim_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &q6_axi_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_q6_axim2_clk = {
> + .halt_reg = 0x59150,
> + .clkr = {
> + .enable_reg = 0x59150,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_q6_axim2_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &q6_axi_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_q6_axis_clk = {
> + .halt_reg = 0x59154,
> + .clkr = {
> + .enable_reg = 0x59154,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_q6_axis_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &system_noc_clk_src.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_q6_tsctr_1to2_clk = {
> + .halt_reg = 0x59148,
> + .clkr = {
> + .enable_reg = 0x59148,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_q6_tsctr_1to2_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &qdss_tsctr_div2_clk_src.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_q6ss_atbm_clk = {
> + .halt_reg = 0x59144,
> + .clkr = {
> + .enable_reg = 0x59144,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_q6ss_atbm_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &qdss_at_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_q6ss_pclkdbg_clk = {
> + .halt_reg = 0x59140,
> + .clkr = {
> + .enable_reg = 0x59140,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_q6ss_pclkdbg_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &qdss_dap_sync_clk_src.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_q6ss_trig_clk = {
> + .halt_reg = 0x59128,
> + .clkr = {
> + .enable_reg = 0x59128,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_q6ss_trig_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &qdss_dap_sync_clk_src.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qdss_at_clk = {
> + .halt_reg = 0x29024,
> + .clkr = {
> + .enable_reg = 0x29024,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_qdss_at_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &qdss_at_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qdss_dap_clk = {
> + .halt_reg = 0x29084,
> + .clkr = {
> + .enable_reg = 0x29084,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_qdss_dap_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &qdss_tsctr_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qdss_cfg_ahb_clk = {
> + .halt_reg = 0x29008,
> + .clkr = {
> + .enable_reg = 0x29008,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_qdss_cfg_ahb_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &pcnoc_clk_src.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qdss_dap_ahb_clk = {
> + .halt_reg = 0x29004,
> + .clkr = {
> + .enable_reg = 0x29004,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_qdss_dap_ahb_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &pcnoc_clk_src.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qdss_etr_usb_clk = {
> + .halt_reg = 0x29028,
> + .clkr = {
> + .enable_reg = 0x29028,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_qdss_etr_usb_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &system_noc_clk_src.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qdss_eud_at_clk = {
> + .halt_reg = 0x29020,
> + .clkr = {
> + .enable_reg = 0x29020,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_qdss_eud_at_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &eud_at_clk_src.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qdss_stm_clk = {
> + .halt_reg = 0x29044,
> + .clkr = {
> + .enable_reg = 0x29044,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_qdss_stm_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &qdss_stm_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qdss_traceclkin_clk = {
> + .halt_reg = 0x29060,
> + .clkr = {
> + .enable_reg = 0x29060,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_qdss_traceclkin_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &qdss_traceclkin_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qdss_tsctr_div8_clk = {
> + .halt_reg = 0x2908c,
> + .clkr = {
> + .enable_reg = 0x2908c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_qdss_tsctr_div8_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &qdss_tsctr_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qpic_ahb_clk = {
> + .halt_reg = 0x57024,
> + .clkr = {
> + .enable_reg = 0x57024,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_qpic_ahb_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &pcnoc_clk_src.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qpic_clk = {
> + .halt_reg = 0x57020,
> + .clkr = {
> + .enable_reg = 0x57020,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_qpic_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &pcnoc_clk_src.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qpic_io_macro_clk = {
> + .halt_reg = 0x5701c,
> + .clkr = {
> + .enable_reg = 0x5701c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_qpic_io_macro_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &qpic_io_macro_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_sdcc1_ahb_clk = {
> + .halt_reg = 0x4201c,
> + .clkr = {
> + .enable_reg = 0x4201c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_sdcc1_ahb_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &pcnoc_clk_src.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_sdcc1_apps_clk = {
> + .halt_reg = 0x42018,
> + .clkr = {
> + .enable_reg = 0x42018,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_sdcc1_apps_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &sdcc1_apps_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_snoc_gmac0_ahb_clk = {
> + .halt_reg = 0x260a0,
> + .clkr = {
> + .enable_reg = 0x260a0,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_snoc_gmac0_ahb_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &gmac_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_snoc_gmac0_axi_clk = {
> + .halt_reg = 0x26084,
> + .clkr = {
> + .enable_reg = 0x26084,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_snoc_gmac0_axi_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &gmac_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_snoc_gmac1_ahb_clk = {
> + .halt_reg = 0x260a4,
> + .clkr = {
> + .enable_reg = 0x260a4,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_snoc_gmac1_ahb_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &gmac_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_snoc_gmac1_axi_clk = {
> + .halt_reg = 0x26088,
> + .clkr = {
> + .enable_reg = 0x26088,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_snoc_gmac1_axi_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &gmac_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_snoc_lpass_axim_clk = {
> + .halt_reg = 0x26074,
> + .clkr = {
> + .enable_reg = 0x26074,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_snoc_lpass_axim_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &lpass_axim_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_snoc_lpass_sway_clk = {
> + .halt_reg = 0x26078,
> + .clkr = {
> + .enable_reg = 0x26078,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_snoc_lpass_sway_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &lpass_sway_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_snoc_ubi0_axi_clk = {
> + .halt_reg = 0x26094,
> + .clkr = {
> + .enable_reg = 0x26094,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_snoc_ubi0_axi_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &ubi0_axi_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_sys_noc_pcie0_axi_clk = {
> + .halt_reg = 0x26048,
> + .clkr = {
> + .enable_reg = 0x26048,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_sys_noc_pcie0_axi_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &pcie0_axi_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_sys_noc_pcie1_axi_clk = {
> + .halt_reg = 0x2604c,
> + .clkr = {
> + .enable_reg = 0x2604c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_sys_noc_pcie1_axi_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &pcie1_axi_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_sys_noc_qdss_stm_axi_clk = {
> + .halt_reg = 0x26024,
> + .clkr = {
> + .enable_reg = 0x26024,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_sys_noc_qdss_stm_axi_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &qdss_stm_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_sys_noc_usb0_axi_clk = {
> + .halt_reg = 0x26040,
> + .clkr = {
> + .enable_reg = 0x26040,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_sys_noc_usb0_axi_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &usb0_master_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_sys_noc_wcss_ahb_clk = {
> + .halt_reg = 0x26034,
> + .clkr = {
> + .enable_reg = 0x26034,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_sys_noc_wcss_ahb_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &wcss_ahb_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_ubi0_axi_clk = {
> + .halt_reg = 0x68200,
> + .halt_check = BRANCH_HALT_DELAY,
> + .clkr = {
> + .enable_reg = 0x68200,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_ubi0_axi_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &ubi0_axi_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_ubi0_cfg_clk = {
> + .halt_reg = 0x68160,
> + .halt_check = BRANCH_HALT_DELAY,
> + .clkr = {
> + .enable_reg = 0x68160,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_ubi0_cfg_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &pcnoc_clk_src.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_ubi0_dbg_clk = {
> + .halt_reg = 0x68214,
> + .halt_check = BRANCH_HALT_DELAY,
> + .clkr = {
> + .enable_reg = 0x68214,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_ubi0_dbg_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &qdss_tsctr_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_ubi0_core_clk = {
> + .halt_reg = 0x68210,
> + .halt_check = BRANCH_HALT_DELAY,
> + .clkr = {
> + .enable_reg = 0x68210,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_ubi0_core_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &ubi0_core_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_ubi0_nc_axi_clk = {
> + .halt_reg = 0x68204,
> + .halt_check = BRANCH_HALT_DELAY,
> + .clkr = {
> + .enable_reg = 0x68204,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_ubi0_nc_axi_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &system_noc_clk_src.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_ubi0_utcm_clk = {
> + .halt_reg = 0x68208,
> + .halt_check = BRANCH_HALT_DELAY,
> + .clkr = {
> + .enable_reg = 0x68208,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_ubi0_utcm_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &system_noc_clk_src.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_uniphy_ahb_clk = {
> + .halt_reg = 0x56108,
> + .clkr = {
> + .enable_reg = 0x56108,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_uniphy_ahb_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &pcnoc_clk_src.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_uniphy_rx_clk = {
> + .halt_reg = 0x56110,
> + .clkr = {
> + .enable_reg = 0x56110,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_uniphy_rx_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &gmac1_rx_div_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .ops = &clk_branch2_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_uniphy_tx_clk = {
> + .halt_reg = 0x56114,
> + .clkr = {
> + .enable_reg = 0x56114,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_uniphy_tx_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &gmac1_tx_div_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .ops = &clk_branch2_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_uniphy_sys_clk = {
> + .halt_reg = 0x5610C,
> + .clkr = {
> + .enable_reg = 0x5610C,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_uniphy_sys_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &gcc_xo_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_usb0_aux_clk = {
> + .halt_reg = 0x3e044,
> + .clkr = {
> + .enable_reg = 0x3e044,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_usb0_aux_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &usb0_aux_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_usb0_eud_at_clk = {
> + .halt_reg = 0x3e04c,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x3e04c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_usb0_eud_at_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &eud_at_clk_src.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_usb0_lfps_clk = {
> + .halt_reg = 0x3e050,
> + .clkr = {
> + .enable_reg = 0x3e050,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_usb0_lfps_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &usb0_lfps_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_usb0_master_clk = {
> + .halt_reg = 0x3e000,
> + .clkr = {
> + .enable_reg = 0x3e000,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_usb0_master_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &usb0_master_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_usb0_mock_utmi_clk = {
> + .halt_reg = 0x3e008,
> + .clkr = {
> + .enable_reg = 0x3e008,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_usb0_mock_utmi_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &usb0_mock_utmi_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
> + .halt_reg = 0x3e080,
> + .clkr = {
> + .enable_reg = 0x3e080,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_usb0_phy_cfg_ahb_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &pcnoc_clk_src.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_usb0_sleep_clk = {
> + .halt_reg = 0x3e004,
> + .clkr = {
> + .enable_reg = 0x3e004,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_usb0_sleep_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &gcc_sleep_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_usb0_pipe_clk = {
> + .halt_reg = 0x3e040,
> + .halt_check = BRANCH_HALT_DELAY,
> + .clkr = {
> + .enable_reg = 0x3e040,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_usb0_pipe_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &usb0_pipe_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_wcss_acmt_clk = {
> + .halt_reg = 0x59064,
> + .clkr = {
> + .enable_reg = 0x59064,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_wcss_acmt_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &wcss_ahb_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_wcss_ahb_s_clk = {
> + .halt_reg = 0x59034,
> + .clkr = {
> + .enable_reg = 0x59034,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_wcss_ahb_s_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &wcss_ahb_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_wcss_axi_m_clk = {
> + .halt_reg = 0x5903C,
> + .clkr = {
> + .enable_reg = 0x5903C,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_wcss_axi_m_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &system_noc_clk_src.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_wcss_axi_s_clk = {
> + .halt_reg = 0x59068,
> + .clkr = {
> + .enable_reg = 0x59068,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_wi_s_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &system_noc_clk_src.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_wcss_dbg_ifc_apb_bdg_clk = {
> + .halt_reg = 0x59050,
> + .clkr = {
> + .enable_reg = 0x59050,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_wcss_dbg_ifc_apb_bdg_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &qdss_dap_sync_clk_src.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_wcss_dbg_ifc_apb_clk = {
> + .halt_reg = 0x59040,
> + .clkr = {
> + .enable_reg = 0x59040,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_wcss_dbg_ifc_apb_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &qdss_dap_sync_clk_src.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_wcss_dbg_ifc_atb_bdg_clk = {
> + .halt_reg = 0x59054,
> + .clkr = {
> + .enable_reg = 0x59054,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_wcss_dbg_ifc_atb_bdg_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &qdss_at_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_wcss_dbg_ifc_atb_clk = {
> + .halt_reg = 0x59044,
> + .clkr = {
> + .enable_reg = 0x59044,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_wcss_dbg_ifc_atb_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &qdss_at_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_wcss_dbg_ifc_dapbus_bdg_clk = {
> + .halt_reg = 0x59060,
> + .clkr = {
> + .enable_reg = 0x59060,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_wcss_dbg_ifc_dapbus_bdg_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &qdss_dap_sync_clk_src.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_wcss_dbg_ifc_dapbus_clk = {
> + .halt_reg = 0x5905C,
> + .clkr = {
> + .enable_reg = 0x5905C,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_wcss_dbg_ifc_dapbus_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &qdss_dap_sync_clk_src.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_wcss_dbg_ifc_nts_bdg_clk = {
> + .halt_reg = 0x59058,
> + .clkr = {
> + .enable_reg = 0x59058,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_wcss_dbg_ifc_nts_bdg_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &qdss_tsctr_div2_clk_src.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_wcss_dbg_ifc_nts_clk = {
> + .halt_reg = 0x59048,
> + .clkr = {
> + .enable_reg = 0x59048,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_wcss_dbg_ifc_nts_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &qdss_tsctr_div2_clk_src.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_wcss_ecahb_clk = {
> + .halt_reg = 0x59038,
> + .clkr = {
> + .enable_reg = 0x59038,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "gcc_wcss_ecahb_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &wcss_ahb_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_hw *gcc_ipq5018_hws[] = {
> + &gpll0_out_main_div2.hw,
> + &pcnoc_clk_src.hw,
> + &system_noc_clk_src.hw,
> + &qdss_dap_sync_clk_src.hw,
> + &qdss_tsctr_div2_clk_src.hw,
> + &eud_at_clk_src.hw,
> +};
> +
> +static const struct alpha_pll_config ubi32_pll_config = {
> + .l = 0x29,
> + .alpha = 0xAAAAAAAA,
> + .alpha_hi = 0xAA,
> + .config_ctl_val = 0x4001075b,
> + .main_output_mask = BIT(0),
> + .aux_output_mask = BIT(1),
> + .alpha_en_mask = BIT(24),
> + .vco_val = 0x1,
> + .vco_mask = GENMASK(21, 20),
> + .test_ctl_val = 0x0,
> + .test_ctl_hi_val = 0x0,
> +};
> +
> +static struct clk_regmap *gcc_ipq5018_clks[] = {
> + [GPLL0_MAIN] = &gpll0_main.clkr,
> + [GPLL0] = &gpll0.clkr,
> + [GPLL2_MAIN] = &gpll2_main.clkr,
> + [GPLL2] = &gpll2.clkr,
> + [GPLL4_MAIN] = &gpll4_main.clkr,
> + [GPLL4] = &gpll4.clkr,
> + [UBI32_PLL_MAIN] = &ubi32_pll_main.clkr,
> + [UBI32_PLL] = &ubi32_pll.clkr,
> + [ADSS_PWM_CLK_SRC] = &adss_pwm_clk_src.clkr,
> + [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
> + [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
> + [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
> + [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
> + [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
> + [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
> + [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
> + [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
> + [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
> + [GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,
> + [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
> + [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
> + [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
> + [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
> + [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
> + [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
> + [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
> + [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
> + [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
> + [GCC_BTSS_LPO_CLK] = &gcc_btss_lpo_clk.clkr,
> + [GCC_CMN_BLK_AHB_CLK] = &gcc_cmn_blk_ahb_clk.clkr,
> + [GCC_CMN_BLK_SYS_CLK] = &gcc_cmn_blk_sys_clk.clkr,
> + [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
> + [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
> + [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
> + [GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
> + [GCC_GEPHY_RX_CLK] = &gcc_gephy_rx_clk.clkr,
> + [GCC_GEPHY_TX_CLK] = &gcc_gephy_tx_clk.clkr,
> + [GCC_GMAC0_CFG_CLK] = &gcc_gmac0_cfg_clk.clkr,
> + [GCC_GMAC0_PTP_CLK] = &gcc_gmac0_ptp_clk.clkr,
> + [GCC_GMAC0_RX_CLK] = &gcc_gmac0_rx_clk.clkr,
> + [GCC_GMAC0_SYS_CLK] = &gcc_gmac0_sys_clk.clkr,
> + [GCC_GMAC0_TX_CLK] = &gcc_gmac0_tx_clk.clkr,
> + [GCC_GMAC1_CFG_CLK] = &gcc_gmac1_cfg_clk.clkr,
> + [GCC_GMAC1_PTP_CLK] = &gcc_gmac1_ptp_clk.clkr,
> + [GCC_GMAC1_RX_CLK] = &gcc_gmac1_rx_clk.clkr,
> + [GCC_GMAC1_SYS_CLK] = &gcc_gmac1_sys_clk.clkr,
> + [GCC_GMAC1_TX_CLK] = &gcc_gmac1_tx_clk.clkr,
> + [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
> + [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
> + [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
> + [GCC_LPASS_CORE_AXIM_CLK] = &gcc_lpass_core_axim_clk.clkr,
> + [GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr,
> + [GCC_MDIO0_AHB_CLK] = &gcc_mdio0_ahb_clk.clkr,
> + [GCC_MDIO1_AHB_CLK] = &gcc_mdio1_ahb_clk.clkr,
> + [GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
> + [GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
> + [GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
> + [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
> + [GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
> + [GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr,
> + [GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr,
> + [GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr,
> + [GCC_PCIE1_AXI_S_BRIDGE_CLK] = &gcc_pcie1_axi_s_bridge_clk.clkr,
> + [GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr,
> + [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
> + [GCC_Q6_AXIM_CLK] = &gcc_q6_axim_clk.clkr,
> + [GCC_Q6_AXIM2_CLK] = &gcc_q6_axim2_clk.clkr,
> + [GCC_Q6_AXIS_CLK] = &gcc_q6_axis_clk.clkr,
> + [GCC_Q6_AHB_CLK] = &gcc_q6_ahb_clk.clkr,
> + [GCC_Q6_AHB_S_CLK] = &gcc_q6_ahb_s_clk.clkr,
> + [GCC_Q6_TSCTR_1TO2_CLK] = &gcc_q6_tsctr_1to2_clk.clkr,
> + [GCC_Q6SS_ATBM_CLK] = &gcc_q6ss_atbm_clk.clkr,
> + [GCC_Q6SS_PCLKDBG_CLK] = &gcc_q6ss_pclkdbg_clk.clkr,
> + [GCC_Q6SS_TRIG_CLK] = &gcc_q6ss_trig_clk.clkr,
> + [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr,
> + [GCC_QDSS_CFG_AHB_CLK] = &gcc_qdss_cfg_ahb_clk.clkr,
> + [GCC_QDSS_DAP_AHB_CLK] = &gcc_qdss_dap_ahb_clk.clkr,
> + [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
> + [GCC_QDSS_ETR_USB_CLK] = &gcc_qdss_etr_usb_clk.clkr,
> + [GCC_QDSS_EUD_AT_CLK] = &gcc_qdss_eud_at_clk.clkr,
> + [GCC_QDSS_STM_CLK] = &gcc_qdss_stm_clk.clkr,
> + [GCC_QDSS_TRACECLKIN_CLK] = &gcc_qdss_traceclkin_clk.clkr,
> + [GCC_QDSS_TSCTR_DIV8_CLK] = &gcc_qdss_tsctr_div8_clk.clkr,
> + [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
> + [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
> + [GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr,
> + [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
> + [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
> + [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
> + [GCC_SNOC_GMAC0_AHB_CLK] = &gcc_snoc_gmac0_ahb_clk.clkr,
> + [GCC_SNOC_GMAC0_AXI_CLK] = &gcc_snoc_gmac0_axi_clk.clkr,
> + [GCC_SNOC_GMAC1_AHB_CLK] = &gcc_snoc_gmac1_ahb_clk.clkr,
> + [GCC_SNOC_GMAC1_AXI_CLK] = &gcc_snoc_gmac1_axi_clk.clkr,
> + [GCC_SNOC_LPASS_AXIM_CLK] = &gcc_snoc_lpass_axim_clk.clkr,
> + [GCC_SNOC_LPASS_SWAY_CLK] = &gcc_snoc_lpass_sway_clk.clkr,
> + [GCC_SNOC_UBI0_AXI_CLK] = &gcc_snoc_ubi0_axi_clk.clkr,
> + [GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr,
> + [GCC_SYS_NOC_PCIE1_AXI_CLK] = &gcc_sys_noc_pcie1_axi_clk.clkr,
> + [GCC_SYS_NOC_QDSS_STM_AXI_CLK] = &gcc_sys_noc_qdss_stm_axi_clk.clkr,
> + [GCC_SYS_NOC_USB0_AXI_CLK] = &gcc_sys_noc_usb0_axi_clk.clkr,
> + [GCC_SYS_NOC_WCSS_AHB_CLK] = &gcc_sys_noc_wcss_ahb_clk.clkr,
> + [GCC_UBI0_AXI_CLK] = &gcc_ubi0_axi_clk.clkr,
> + [GCC_UBI0_CFG_CLK] = &gcc_ubi0_cfg_clk.clkr,
> + [GCC_UBI0_CORE_CLK] = &gcc_ubi0_core_clk.clkr,
> + [GCC_UBI0_DBG_CLK] = &gcc_ubi0_dbg_clk.clkr,
> + [GCC_UBI0_NC_AXI_CLK] = &gcc_ubi0_nc_axi_clk.clkr,
> + [GCC_UBI0_UTCM_CLK] = &gcc_ubi0_utcm_clk.clkr,
> + [GCC_UNIPHY_AHB_CLK] = &gcc_uniphy_ahb_clk.clkr,
> + [GCC_UNIPHY_RX_CLK] = &gcc_uniphy_rx_clk.clkr,
> + [GCC_UNIPHY_SYS_CLK] = &gcc_uniphy_sys_clk.clkr,
> + [GCC_UNIPHY_TX_CLK] = &gcc_uniphy_tx_clk.clkr,
> + [GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
> + [GCC_USB0_EUD_AT_CLK] = &gcc_usb0_eud_at_clk.clkr,
> + [GCC_USB0_LFPS_CLK] = &gcc_usb0_lfps_clk.clkr,
> + [GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
> + [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
> + [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
> + [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
> + [GCC_WCSS_ACMT_CLK] = &gcc_wcss_acmt_clk.clkr,
> + [GCC_WCSS_AHB_S_CLK] = &gcc_wcss_ahb_s_clk.clkr,
> + [GCC_WCSS_AXI_M_CLK] = &gcc_wcss_axi_m_clk.clkr,
> + [GCC_WCSS_AXI_S_CLK] = &gcc_wcss_axi_s_clk.clkr,
> + [GCC_WCSS_DBG_IFC_APB_BDG_CLK] = &gcc_wcss_dbg_ifc_apb_bdg_clk.clkr,
> + [GCC_WCSS_DBG_IFC_APB_CLK] = &gcc_wcss_dbg_ifc_apb_clk.clkr,
> + [GCC_WCSS_DBG_IFC_ATB_BDG_CLK] = &gcc_wcss_dbg_ifc_atb_bdg_clk.clkr,
> + [GCC_WCSS_DBG_IFC_ATB_CLK] = &gcc_wcss_dbg_ifc_atb_clk.clkr,
> + [GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK] = &gcc_wcss_dbg_ifc_dapbus_bdg_clk.clkr,
> + [GCC_WCSS_DBG_IFC_DAPBUS_CLK] = &gcc_wcss_dbg_ifc_dapbus_clk.clkr,
> + [GCC_WCSS_DBG_IFC_NTS_BDG_CLK] = &gcc_wcss_dbg_ifc_nts_bdg_clk.clkr,
> + [GCC_WCSS_DBG_IFC_NTS_CLK] = &gcc_wcss_dbg_ifc_nts_clk.clkr,
> + [GCC_WCSS_ECAHB_CLK] = &gcc_wcss_ecahb_clk.clkr,
> + [GCC_XO_CLK] = &gcc_xo_clk.clkr,
> + [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
> + [GMAC0_RX_CLK_SRC] = &gmac0_rx_clk_src.clkr,
> + [GMAC0_RX_DIV_CLK_SRC] = &gmac0_rx_div_clk_src.clkr,
> + [GMAC0_TX_CLK_SRC] = &gmac0_tx_clk_src.clkr,
> + [GMAC0_TX_DIV_CLK_SRC] = &gmac0_tx_div_clk_src.clkr,
> + [GMAC1_RX_CLK_SRC] = &gmac1_rx_clk_src.clkr,
> + [GMAC1_RX_DIV_CLK_SRC] = &gmac1_rx_div_clk_src.clkr,
> + [GMAC1_TX_CLK_SRC] = &gmac1_tx_clk_src.clkr,
> + [GMAC1_TX_DIV_CLK_SRC] = &gmac1_tx_div_clk_src.clkr,
> + [GMAC_CLK_SRC] = &gmac_clk_src.clkr,
> + [GP1_CLK_SRC] = &gp1_clk_src.clkr,
> + [GP2_CLK_SRC] = &gp2_clk_src.clkr,
> + [GP3_CLK_SRC] = &gp3_clk_src.clkr,
> + [LPASS_AXIM_CLK_SRC] = &lpass_axim_clk_src.clkr,
> + [LPASS_SWAY_CLK_SRC] = &lpass_sway_clk_src.clkr,
> + [PCIE0_AUX_CLK_SRC] = &pcie0_aux_clk_src.clkr,
> + [PCIE0_AXI_CLK_SRC] = &pcie0_axi_clk_src.clkr,
> + [PCIE1_AUX_CLK_SRC] = &pcie1_aux_clk_src.clkr,
> + [PCIE1_AXI_CLK_SRC] = &pcie1_axi_clk_src.clkr,
> + [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
> + [Q6_AXI_CLK_SRC] = &q6_axi_clk_src.clkr,
> + [QDSS_AT_CLK_SRC] = &qdss_at_clk_src.clkr,
> + [QDSS_STM_CLK_SRC] = &qdss_stm_clk_src.clkr,
> + [QDSS_TSCTR_CLK_SRC] = &qdss_tsctr_clk_src.clkr,
> + [QDSS_TRACECLKIN_CLK_SRC] = &qdss_traceclkin_clk_src.clkr,
> + [QPIC_IO_MACRO_CLK_SRC] = &qpic_io_macro_clk_src.clkr,
> + [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
> + [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
> + [UBI0_AXI_CLK_SRC] = &ubi0_axi_clk_src.clkr,
> + [UBI0_CORE_CLK_SRC] = &ubi0_core_clk_src.clkr,
> + [USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr,
> + [USB0_LFPS_CLK_SRC] = &usb0_lfps_clk_src.clkr,
> + [USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr,
> + [USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr,
> + [WCSS_AHB_CLK_SRC] = &wcss_ahb_clk_src.clkr,
> + [PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,
> + [PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr,
> + [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
> + [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,
> + [USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
> + [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
> +};
> +
> +static const struct qcom_reset_map gcc_ipq5018_resets[] = {
> + [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 },
> + [GCC_BLSP1_BCR] = { 0x01000, 0 },
> + [GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
> + [GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 },
> + [GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 },
> + [GCC_BLSP1_UART1_BCR] = { 0x02038, 0 },
> + [GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
> + [GCC_BOOT_ROM_BCR] = { 0x13008, 0 },
> + [GCC_BTSS_BCR] = { 0x1c000, 0 },
> + [GCC_CMN_BLK_BCR] = { 0x56300, 0 },
> + [GCC_CMN_LDO_BCR] = { 0x33000, 0 },
> + [GCC_CE_BCR] = { 0x33014, 0 },
> + [GCC_CRYPTO_BCR] = { 0x16000, 0 },
> + [GCC_DCC_BCR] = { 0x77000, 0 },
> + [GCC_DCD_BCR] = { 0x2a000, 0 },
> + [GCC_DDRSS_BCR] = { 0x1e000, 0 },
> + [GCC_EDPD_BCR] = { 0x3a000, 0 },
> + [GCC_GEPHY_BCR] = { 0x56000, 0 },
> + [GCC_GEPHY_MDC_SW_ARES] = { 0x56004, 0 },
> + [GCC_GEPHY_DSP_HW_ARES] = { 0x56004, 1 },
> + [GCC_GEPHY_RX_ARES] = { 0x56004, 2 },
> + [GCC_GEPHY_TX_ARES] = { 0x56004, 3 },
> + [GCC_GMAC0_BCR] = { 0x19000, 0 },
> + [GCC_GMAC0_CFG_ARES] = { 0x68428, 0 },
> + [GCC_GMAC0_SYS_ARES] = { 0x68428, 1 },
> + [GCC_GMAC1_BCR] = { 0x19100, 0 },
> + [GCC_GMAC1_CFG_ARES] = { 0x68438, 0 },
> + [GCC_GMAC1_SYS_ARES] = { 0x68438, 1 },
> + [GCC_IMEM_BCR] = { 0x0e000, 0 },
> + [GCC_LPASS_BCR] = { 0x2e000, 0 },
> + [GCC_MDIO0_BCR] = { 0x58000, 0 },
> + [GCC_MDIO1_BCR] = { 0x58010, 0 },
> + [GCC_MPM_BCR] = { 0x2c000, 0 },
> + [GCC_PCIE0_BCR] = { 0x75004, 0 },
> + [GCC_PCIE0_LINK_DOWN_BCR] = { 0x750a8, 0 },
> + [GCC_PCIE0_PHY_BCR] = { 0x75038, 0 },
> + [GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 },
> + [GCC_PCIE0_PIPE_ARES] = { 0x75040, 0 },
> + [GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 },
> + [GCC_PCIE0_CORE_STICKY_ARES] = { 0x75040, 2 },
> + [GCC_PCIE0_AXI_MASTER_ARES] = { 0x75040, 3 },
> + [GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 },
> + [GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
> + [GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
> + [GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 },
> + [GCC_PCIE1_BCR] = { 0x76004, 0 },
> + [GCC_PCIE1_LINK_DOWN_BCR] = { 0x76044, 0 },
> + [GCC_PCIE1_PHY_BCR] = { 0x76038, 0 },
> + [GCC_PCIE1PHY_PHY_BCR] = { 0x7603c, 0 },
> + [GCC_PCIE1_PIPE_ARES] = { 0x76040, 0 },
> + [GCC_PCIE1_SLEEP_ARES] = { 0x76040, 1 },
> + [GCC_PCIE1_CORE_STICKY_ARES] = { 0x76040, 2 },
> + [GCC_PCIE1_AXI_MASTER_ARES] = { 0x76040, 3 },
> + [GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 },
> + [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
> + [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
> + [GCC_PCIE1_AXI_SLAVE_STICKY_ARES] = { 0x76040, 7 },
> + [GCC_PCNOC_BCR] = { 0x27018, 0 },
> + [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 },
> + [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 },
> + [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 },
> + [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 },
> + [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 },
> + [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 },
> + [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 },
> + [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 },
> + [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 },
> + [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 },
> + [GCC_PCNOC_BUS_TIMEOUT10_BCR] = { 0x48050, 0 },
> + [GCC_PCNOC_BUS_TIMEOUT11_BCR] = { 0x48058, 0 },
> + [GCC_PRNG_BCR] = { 0x13000, 0 },
> + [GCC_Q6SS_DBG_ARES] = { 0x59110, 0 },
> + [GCC_Q6_AHB_S_ARES] = { 0x59110, 1 },
> + [GCC_Q6_AHB_ARES] = { 0x59110, 2 },
> + [GCC_Q6_AXIM2_ARES] = { 0x59110, 3 },
> + [GCC_Q6_AXIM_ARES] = { 0x59110, 4 },
> + [GCC_Q6_AXIS_ARES] = { 0x59158, 0 },
> + [GCC_QDSS_BCR] = { 0x29000, 0 },
> + [GCC_QPIC_BCR] = { 0x57018, 0 },
> + [GCC_QUSB2_0_PHY_BCR] = { 0x41030, 0 },
> + [GCC_SDCC1_BCR] = { 0x42000, 0 },
> + [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
> + [GCC_SPDM_BCR] = { 0x2f000, 0 },
> + [GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 },
> + [GCC_TCSR_BCR] = { 0x28000, 0 },
> + [GCC_TLMM_BCR] = { 0x34000, 0 },
> + [GCC_UBI0_AXI_ARES] = { 0x680},
> + [GCC_UBI0_AHB_ARES] = { 0x68010, 1 },
> + [GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 },
> + [GCC_UBI0_DBG_ARES] = { 0x68010, 3 },
> + [GCC_UBI0_UTCM_ARES] = { 0x68010, 6 },
> + [GCC_UBI0_CORE_ARES] = { 0x68010, 7 },
> + [GCC_UBI32_BCR] = { 0x19064, 0 },
> + [GCC_UNIPHY_BCR] = { 0x56100, 0 },
> + [GCC_UNIPHY_AHB_ARES] = { 0x56104, 0 },
> + [GCC_UNIPHY_SYS_ARES] = { 0x56104, 1 },
> + [GCC_UNIPHY_RX_ARES] = { 0x56104, 4 },
> + [GCC_UNIPHY_TX_ARES] = { 0x56104, 5 },
> + [GCC_UNIPHY_SOFT_RESET] = {0x56104, 0 },
> + [GCC_USB0_BCR] = { 0x3e070, 0 },
> + [GCC_USB0_PHY_BCR] = { 0x3e034, 0 },
> + [GCC_WCSS_BCR] = { 0x18000, 0 },
> + [GCC_WCSS_DBG_ARES] = { 0x59008, 0 },
> + [GCC_WCSS_ECAHB_ARES] = { 0x59008, 1 },
> + [GCC_WCSS_ACMT_ARES] = { 0x59008, 2 },
> + [GCC_WCSS_DBG_BDG_ARES] = { 0x59008, 3 },
> + [GCC_WCSS_AHB_S_ARES] = { 0x59008, 4 },
> + [GCC_WCSS_AXI_M_ARES] = { 0x59008, 5 },
> + [GCC_WCSS_AXI_S_ARES] = { 0x59008, 6 },
> + [GCC_WCSS_Q6_BCR] = { 0x18004, 0 },
> + [GCC_WCSSAON_RESET] = { 0x59010, 0},
> + [GCC_GEPHY_MISC_ARES] = { 0x56004, 0 },
> +};
> +
> +static const struct of_device_id gcc_ipq5018_match_table[] = {
> + { .compatible = "qcom,gcc-ipq5018" },
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, gcc_ipq5018_match_table);
> +
> +static const struct regmap_config gcc_ipq5018_regmap_config = {
> + .reg_bits = 32,
> + .reg_stride = 4,
> + .val_bits = 32,
> + .max_register = 0x7fffc,
> + .fast_io = true,
> +};
> +
> +static const struct qcom_cc_desc gcc_ipq5018_desc = {
> + .config = &gcc_ipq5018_regmap_config,
> + .clks = gcc_ipq5018_clks,
> + .num_clks = ARRAY_SIZE(gcc_ipq5018_clks),
> + .resets = gcc_ipq5018_resets,
> + .num_resets = ARRAY_SIZE(gcc_ipq5018_resets),
> + .clk_hws = gcc_ipq5018_hws,
> + .num_clk_hws = ARRAY_SIZE(gcc_ipq5018_hws),
> +};
> +
> +static int gcc_ipq5018_probe(struct platform_device *pdev)
> +{
> + struct regmap *regmap;
> + struct qcom_cc_desc ipq5018_desc = gcc_ipq5018_desc;
> +
> + regmap = qcom_cc_map(pdev, &ipq5018_desc);
> + if (IS_ERR(regmap))
> + return PTR_ERR(regmap);
> +
> + clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
> +
> + return qcom_cc_really_probe(pdev, &ipq5018_desc, regmap);
> +}
> +
> +static struct platform_driver gcc_ipq5018_driver = {
> + .probe = gcc_ipq5018_probe,
> + .driver = {
> + .name = "qcom,gcc-ipq5018",
> + .of_match_table = gcc_ipq5018_match_table,
> + },
> +};
> +
> +static int __init gcc_ipq5018_init(void)
> +{
> + return platform_driver_register(&gcc_ipq5018_driver);
> +}
> +core_initcall(gcc_ipq5018_init);
> +
> +static void __exit gcc_ipq5018_exit(void)
> +{
> + platform_driver_unregister(&gcc_ipq5018_driver);
> +}
> +module_exit(gcc_ipq5018_exit);
> +
> +MODULE_DESCRIPTION("Qualcomm Technologies, Inc. GCC IPQ5018 Driver");
> +MODULE_LICENSE("GPL");
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [v9 2/8] clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018
2023-06-09 13:52 ` Konrad Dybcio
@ 2023-06-11 4:49 ` Sricharan Ramabadhran
0 siblings, 0 replies; 13+ messages in thread
From: Sricharan Ramabadhran @ 2023-06-11 4:49 UTC (permalink / raw)
To: Konrad Dybcio, agross, andersson, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, ulf.hansson,
linus.walleij, catalin.marinas, will, p.zabel, linux-arm-msm,
devicetree, linux-kernel, linux-mmc, linux-gpio,
linux-arm-kernel, robimarko, krzysztof.kozlowski,
andy.shevchenko
On 6/9/2023 7:22 PM, Konrad Dybcio wrote:
>
>
> On 8.06.2023 14:21, Sricharan Ramabadhran wrote:
>> Add support for the global clock controller found on IPQ5018
>> based devices.
>>
>> Co-developed-by: Varadarajan Narayanan <quic_varada@quicinc.com>
>> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
>> Co-developed-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
>> Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
>> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
>> ---
>> [v9] Sorted the headers and cleaned the unwanted ones
>> Added trailing comma for .parent_hws member
>> Removed the hunk touching ipq5332 kconfig (unintentionally)
>>
> You did not address the comments I made in v4.
>
> https://lore.kernel.org/linux-arm-msm/21a5642c-e6e5-9323-7db1-383a18616ac0@linaro.org/
oops, sorry, i guess, missed it, will send with fixed.
Regards,
Sricharan
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2023-06-11 4:50 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-06-08 12:21 [v9 0/8] Add minimal boot support for IPQ5018 Sricharan Ramabadhran
2023-06-08 12:21 ` [v9 1/8] dt-bindings: arm64: Add IPQ5018 clock and reset Sricharan Ramabadhran
2023-06-08 12:21 ` [v9 2/8] clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018 Sricharan Ramabadhran
2023-06-09 13:52 ` Konrad Dybcio
2023-06-11 4:49 ` Sricharan Ramabadhran
2023-06-08 12:21 ` [v9 3/8] dt-bindings: pinctrl: qcom: Add support for ipq5018 Sricharan Ramabadhran
2023-06-09 7:00 ` Linus Walleij
2023-06-08 12:21 ` [v9 4/8] pinctrl: qcom: Add IPQ5018 pinctrl driver Sricharan Ramabadhran
2023-06-09 7:01 ` Linus Walleij
2023-06-08 12:21 ` [v9 5/8] dt-bindings: qcom: Add ipq5018 bindings Sricharan Ramabadhran
2023-06-08 12:21 ` [v9 6/8] dt-bindings: scm: Add compatible for IPQ5018 Sricharan Ramabadhran
2023-06-08 12:21 ` [v9 7/8] arm64: dts: Add ipq5018 SoC and rdp432-c2 board support Sricharan Ramabadhran
2023-06-08 12:21 ` [v9 8/8] arm64: defconfig: Enable IPQ5018 SoC base configs Sricharan Ramabadhran
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).