From: Marc Kleine-Budde <mkl@pengutronix.de>
To: Srinivas Goud <srinivas.goud@amd.com>
Cc: wg@grandegger.com, davem@davemloft.net, edumazet@google.com,
kuba@kernel.org, pabeni@redhat.com, gcnu.goud@gmail.com,
git@amd.com, michal.simek@xilinx.com, linux-can@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/3] can: xilinx_can: Add ECC support
Date: Fri, 16 Jun 2023 13:06:43 +0200 [thread overview]
Message-ID: <20230616-expenses-regime-50bdd5f78eea-mkl@pengutronix.de> (raw)
In-Reply-To: <1686570177-2836108-3-git-send-email-srinivas.goud@amd.com>
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On 12.06.2023 17:12:56, Srinivas Goud wrote:
> Add ECC support for Xilinx CAN Controller, so this driver reports
> 1bit/2bit ECC errors for FIFO's based on ECC error interrupt.
> ECC feature for Xilinx CAN Controller selected through
> 'xlnx,has-ecc' DT property
>
> Signed-off-by: Srinivas Goud <srinivas.goud@amd.com>
> ---
> drivers/net/can/xilinx_can.c | 109 +++++++++++++++++++++++++++++++++++++++++--
> 1 file changed, 104 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/net/can/xilinx_can.c b/drivers/net/can/xilinx_can.c
> index 43c812e..311e435 100644
> --- a/drivers/net/can/xilinx_can.c
> +++ b/drivers/net/can/xilinx_can.c
> @@ -63,6 +63,12 @@ enum xcan_reg {
> XCAN_RXMSG_2_BASE_OFFSET = 0x2100, /* RX Message Space */
> XCAN_AFR_2_MASK_OFFSET = 0x0A00, /* Acceptance Filter MASK */
> XCAN_AFR_2_ID_OFFSET = 0x0A04, /* Acceptance Filter ID */
> +
> + /* only on AXI CAN cores */
> + XCAN_ECC_CFG_OFFSET = 0xC8, /* ECC Configuration */
> + XCAN_TXTLFIFO_ECC_OFFSET = 0xCC, /* TXTL FIFO ECC error counter */
> + XCAN_TXOLFIFO_ECC_OFFSET = 0xD0, /* TXOL FIFO ECC error counter */
> + XCAN_RXFIFO_ECC_OFFSET = 0xD4, /* RX FIFO ECC error counter */
Please keep the enum sorted by address.
> };
>
> #define XCAN_FRAME_ID_OFFSET(frame_base) ((frame_base) + 0x00)
> @@ -135,6 +141,17 @@ enum xcan_reg {
> #define XCAN_2_FSR_RI_MASK 0x0000003F /* RX Read Index */
> #define XCAN_DLCR_EDL_MASK 0x08000000 /* EDL Mask in DLC */
> #define XCAN_DLCR_BRS_MASK 0x04000000 /* BRS Mask in DLC */
> +#define XCAN_IXR_E2BERX_MASK BIT(23) /* RX FIFO two bit ECC error */
> +#define XCAN_IXR_E1BERX_MASK BIT(22) /* RX FIFO one bit ECC error */
> +#define XCAN_IXR_E2BETXOL_MASK BIT(21) /* TXOL FIFO two bit ECC error */
> +#define XCAN_IXR_E1BETXOL_MASK BIT(20) /* TXOL FIFO One bit ECC error */
> +#define XCAN_IXR_E2BETXTL_MASK BIT(19) /* TXTL FIFO Two bit ECC error */
> +#define XCAN_IXR_E1BETXTL_MASK BIT(18) /* TXTL FIFO One bit ECC error */
Please move the XCAN_IXR next to the other XCAN_IXR.
Marc
--
Pengutronix e.K. | Marc Kleine-Budde |
Embedded Linux | https://www.pengutronix.de |
Vertretung Nürnberg | Phone: +49-5121-206917-129 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-9 |
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next prev parent reply other threads:[~2023-06-16 11:09 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-12 11:42 [PATCH 0/3] can: xilinx_can: Add ECC feature support Srinivas Goud
2023-06-12 11:42 ` [PATCH 1/3] dt-bindings: can: xilinx_can: Add ECC property ‘xlnx,has-ecc’ Srinivas Goud
2023-06-13 7:52 ` Marc Kleine-Budde
2023-06-14 10:22 ` Goud, Srinivas
2023-06-14 11:11 ` Krzysztof Kozlowski
2023-06-16 10:13 ` Goud, Srinivas
2023-06-16 10:38 ` Krzysztof Kozlowski
2023-06-16 10:44 ` Michal Simek
2023-06-17 7:31 ` Krzysztof Kozlowski
2023-06-19 6:37 ` Michal Simek
2023-06-17 7:32 ` Krzysztof Kozlowski
2023-06-13 8:46 ` Krzysztof Kozlowski
2023-06-12 11:42 ` [PATCH 2/3] can: xilinx_can: Add ECC support Srinivas Goud
2023-06-13 11:30 ` Marc Kleine-Budde
2023-07-21 5:23 ` Goud, Srinivas
2023-07-24 8:54 ` Marc Kleine-Budde
2023-06-16 11:06 ` Marc Kleine-Budde [this message]
2023-06-12 11:42 ` [PATCH 3/3] can: xilinx_can: Add debugfs support for ECC Srinivas Goud
2023-06-13 7:51 ` Marc Kleine-Budde
2023-06-16 11:12 ` [PATCH 0/3] can: xilinx_can: Add ECC feature support Marc Kleine-Budde
2023-06-23 7:48 ` Michal Simek
2023-06-30 8:04 ` Marc Kleine-Budde
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