From: Krzysztof Kozlowski <krzk@kernel.org>
To: "Goud, Srinivas" <srinivas.goud@amd.com>,
Marc Kleine-Budde <mkl@pengutronix.de>
Cc: "wg@grandegger.com" <wg@grandegger.com>,
"davem@davemloft.net" <davem@davemloft.net>,
"edumazet@google.com" <edumazet@google.com>,
"kuba@kernel.org" <kuba@kernel.org>,
"pabeni@redhat.com" <pabeni@redhat.com>,
"gcnu.goud@gmail.com" <gcnu.goud@gmail.com>,
"git (AMD-Xilinx)" <git@amd.com>,
"michal.simek@xilinx.com" <michal.simek@xilinx.com>,
"linux-can@vger.kernel.org" <linux-can@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 1/3] dt-bindings: can: xilinx_can: Add ECC property ‘xlnx,has-ecc’
Date: Sat, 17 Jun 2023 09:32:58 +0200 [thread overview]
Message-ID: <aed1592f-927f-13ab-b692-7a0745ac5733@kernel.org> (raw)
In-Reply-To: <d12e3d8b-20e8-48bb-84d0-3fe7d3502c83@kernel.org>
On 14/06/2023 13:11, Krzysztof Kozlowski wrote:
> On 14/06/2023 12:22, Goud, Srinivas wrote:
>> Hi,
>>
>>> -----Original Message-----
>>> From: Marc Kleine-Budde <mkl@pengutronix.de>
>>> Sent: Tuesday, June 13, 2023 1:23 PM
>>> To: Goud, Srinivas <srinivas.goud@amd.com>
>>> Cc: wg@grandegger.com; davem@davemloft.net; edumazet@google.com;
>>> kuba@kernel.org; pabeni@redhat.com; gcnu.goud@gmail.com; git (AMD-
>>> Xilinx) <git@amd.com>; michal.simek@xilinx.com; linux-can@vger.kernel.org;
>>> linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org
>>> Subject: Re: [PATCH 1/3] dt-bindings: can: xilinx_can: Add ECC property
>>> ‘xlnx,has-ecc’
>>>
>>> On 12.06.2023 17:12:55, Srinivas Goud wrote:
>>>> ECC feature added to Tx and Rx FIFO’s for Xilinx CAN Controller.
>>>> Part of this feature configuration and counter registers added in IP
>>>> for 1bit/2bit ECC errors.
>>>> Please find more details in PG096 v5.1 document.
>>>>
>>>> xlnx,has-ecc is optional property and added to Xilinx CAN Controller
>>>> node if ECC block enabled in the HW.
>>>>
>>>> Signed-off-by: Srinivas Goud <srinivas.goud@amd.com>
>>>
>>> Is there a way to introspect the IP core to check if this feature is compiled in?
>> There is no way(IP registers) to indicate whether ECC feature is enabled or not.
>
> Isn't this then deductible from compatible? Your binding claims it is
> only for AXI CAN, so xlnx,axi-can-1.00.a, even though you did not
> restrict it in the binding.
BTW, this is not an ACK, because this was not tested by automation. I
don't understand why get_maintainers.pl are so tricky to use, but
nevertheless I require resend to satisfy automation.
Best regards,
Krzysztof
next prev parent reply other threads:[~2023-06-17 7:33 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-12 11:42 [PATCH 0/3] can: xilinx_can: Add ECC feature support Srinivas Goud
2023-06-12 11:42 ` [PATCH 1/3] dt-bindings: can: xilinx_can: Add ECC property ‘xlnx,has-ecc’ Srinivas Goud
2023-06-13 7:52 ` Marc Kleine-Budde
2023-06-14 10:22 ` Goud, Srinivas
2023-06-14 11:11 ` Krzysztof Kozlowski
2023-06-16 10:13 ` Goud, Srinivas
2023-06-16 10:38 ` Krzysztof Kozlowski
2023-06-16 10:44 ` Michal Simek
2023-06-17 7:31 ` Krzysztof Kozlowski
2023-06-19 6:37 ` Michal Simek
2023-06-17 7:32 ` Krzysztof Kozlowski [this message]
2023-06-13 8:46 ` Krzysztof Kozlowski
2023-06-12 11:42 ` [PATCH 2/3] can: xilinx_can: Add ECC support Srinivas Goud
2023-06-13 11:30 ` Marc Kleine-Budde
2023-07-21 5:23 ` Goud, Srinivas
2023-07-24 8:54 ` Marc Kleine-Budde
2023-06-16 11:06 ` Marc Kleine-Budde
2023-06-12 11:42 ` [PATCH 3/3] can: xilinx_can: Add debugfs support for ECC Srinivas Goud
2023-06-13 7:51 ` Marc Kleine-Budde
2023-06-16 11:12 ` [PATCH 0/3] can: xilinx_can: Add ECC feature support Marc Kleine-Budde
2023-06-23 7:48 ` Michal Simek
2023-06-30 8:04 ` Marc Kleine-Budde
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