[PATCH v6 0/5] PCI: brcmstb: Configure appropriate HW CLKREQ# mode

[PATCH v6 0/5] PCI: brcmstb: Configure appropriate HW CLKREQ# mode

[Jim Quinlan]

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v6 -- No code has been changed.
   -- Changed commit subject and comment in "#PERST" commit (Bjorn, Cyril)
   -- Changed sign-off and author email address for all commits.
      This was due to a change in Broadcom's upstreaming policy.

v5 -- Remove DT property "brcm,completion-timeout-us" from	 
      "DT bindings" commit.  Although this error may be reported	 
      as a completion timeout, its cause was traced to an	 
      internal bus timeout which may occur even when there is	 
      no PCIe access being processed.  We set a timeout of four	 
      seconds only if we are operating in "L1SS CLKREQ#" mode.
   -- Correct CEM 2.0 reference provided by HW engineer,
      s/3.2.5.2.5/3.2.5.2.2/ (Bjorn)
   -- Add newline to dev_info() string (Stefan)
   -- Change variable rval to unsigned (Stefan)
   -- s/implementaion/implementation/ (Bjorn)
   -- s/superpowersave/powersupersave/ (Bjorn)
   -- Slightly modify message on "PERST#" commit.
   -- Rebase to torvalds master

v4 -- New commit that asserts PERST# for 2711/RPi SOCs at PCIe RC
      driver probe() time.  This is done in Raspian Linux and its
      absence may be the cause of a failing test case.
   -- New commit that removes stale comment.

v3 -- Rewrote commit msgs and comments refering panics if L1SS
      is enabled/disabled; the code snippet that unadvertises L1SS
      eliminates the panic scenario. (Bjorn)
   -- Add reference for "400ns of CLKREQ# assertion" blurb (Bjorn)
   -- Put binding names in DT commit Subject (Bjorn)
   -- Add a verb to a commit's subject line (Bjorn)
   -- s/accomodat(\w+)/accommodat$1/g (Bjorn)
   -- Rewrote commit msgs and comments refering panics if L1SS
      is enabled/disabled; the code snippet that unadvertises L1SS
      eliminates the panic scenario. (Bjorn)

v2 -- Changed binding property 'brcm,completion-timeout-msec' to
      'brcm,completion-timeout-us'.  (StefanW for standard suffix).
   -- Warn when clamping timeout value, and include clamped
      region in message. Also add min and max in YAML. (StefanW)
   -- Qualify description of "brcm,completion-timeout-us" so that
      it refers to PCIe transactions. (StefanW)
   -- Remvove mention of Linux specifics in binding description. (StefanW)
   -- s/clkreq#/CLKREQ#/g (Bjorn)
   -- Refactor completion-timeout-us code to compare max and min to
      value given by the property (as opposed to the computed value).

v1 -- The current driver assumes the downstream devices can
      provide CLKREQ# for ASPM.  These commits accomodate devices
      w/ or w/o clkreq# and also handle L1SS-capable devices.

   -- The Raspian Linux folks have already been using a PCIe RC
      property "brcm,enable-l1ss".  These commits use the same
      property, in a backward-compatible manner, and the implementaion
      adds more detail and also automatically identifies devices w/o
      a clkreq# signal, i.e. most devices plugged into an RPi CM4
      IO board.


Jim Quinlan (5):
  dt-bindings: PCI: brcmstb: Add brcm,enable-l1ss property
  PCI: brcmstb: Configure HW CLKREQ# mode appropriate for downstream
    device
  PCI: brcmstb: Set higher value for internal bus timeout
  PCI: brcmstb: Assert PERST# on BCM2711
  PCI: brcmstb: Remove stale comment

 .../bindings/pci/brcm,stb-pcie.yaml           |  9 ++
 drivers/pci/controller/pcie-brcmstb.c         | 91 ++++++++++++++++---
 2 files changed, 89 insertions(+), 11 deletions(-)


base-commit: 8a28a0b6f1a1dcbf5a834600a9acfbe2ba51e5eb
-- 
2.17.1


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[PATCH v6 1/5] dt-bindings: PCI: brcmstb: Add brcm,enable-l1ss property

[Jim Quinlan]

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This commit adds the boolean "brcm,enable-l1ss" property:

  The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs --
  requires the driver probe() to deliberately place the HW one of three
  CLKREQ# modes:

  (a) CLKREQ# driven by the RC unconditionally
  (b) CLKREQ# driven by the EP for ASPM L0s, L1
  (c) Bidirectional CLKREQ#, as used for L1 Substates (L1SS).

  The HW+driver can tell the difference between downstream devices that
  need (a) and (b), but does not know when to configure (c).  All devices
  should work fine when the driver chooses (a) or (b), but (c) may be
  desired to realize the extra power savings that L1SS offers.  So we
  introduce the boolean "brcm,enable-l1ss" property to inform the driver
  that (c) is desired.  Setting this property only makes sense when the
  downstream device is L1SS-capable and the OS is configured to activate
  this mode (e.g. policy==powersupersave).

  This property is already present in the Raspian version of Linux, but the
  upstream driver implementation that follows adds more details and
  discerns between (a) and (b).

Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
index 7e15aae7d69e..8b61c2179608 100644
--- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
@@ -64,6 +64,15 @@ properties:
 
   aspm-no-l0s: true
 
+  brcm,enable-l1ss:
+    description: Indicates that PCIe L1SS power savings
+      are desired, the downstream device is L1SS-capable, and the
+      OS has been configured to enable this mode.  For boards
+      using a mini-card connector, this mode may not meet the
+      TCRLon maximum time of 400ns, as specified in 3.2.5.2.2
+      of the PCI Express Mini CEM 2.0 specification.
+    type: boolean
+
   brcm,scb-sizes:
     description: u64 giving the 64bit PCIe memory
       viewport size of a memory controller.  There may be up to
-- 
2.17.1


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[PATCH v6 2/5] PCI: brcmstb: Configure HW CLKREQ# mode appropriate for downstream device

[Jim Quinlan]

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The Broadcom STB/CM PCIe HW core, which is also used in RPi SOCs, must be
deliberately set by the RC probe() into one of three mutually exclusive
modes:

  (a) No CLKREQ# expected or required, refclk is always available.
  (b) CLKREQ# is expected to be driven by downstream device when needed.
  (c) Bidirectional CLKREQ# for L1SS capable devices.

Previously, only (b) was supported by the driver, as almost all STB/CM
boards operate in this mode.  But now there is interest in activating L1SS
power savings from STB/CM customers, and also interest in accommodating
mode (a) for designs such as the RPi CM4 with IO board.

The HW+driver is able to tell us when mode (a) or (b) is needed.  All
devices should be functional using the RC-driver selected (a) or (b) mode.
For those with L1SS-capable devices that desire the power savings that come
with mode (c) we rely on the DT prop "brcm,enable-l1ss".  It would be nice
to do this automatically but there is no easy way to determine this at the
time the PCI RC driver executes its probe().  Using this mode only makes
sense when the downstream device is L1SS-capable and the OS has been
configured to activate L1SS (e.g. policy==powersupersave).

The "brcm,enable-l1ss" property has already been in use by Raspian Linux,
but this implementation adds more details and discerns between (a) and (b)
automatically.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=217276

Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
Tested-by: Florian Fainelli <f.fainelli@gmail.com>
Tested-by: Cyril Brulebois <cyril@debamax.com>
---
 drivers/pci/controller/pcie-brcmstb.c | 69 +++++++++++++++++++++++----
 1 file changed, 59 insertions(+), 10 deletions(-)

diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index edf283e2b5dd..d30636a725d7 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -48,10 +48,17 @@
 #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY			0x04dc
 #define  PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK	0xc00
 
+#define PCIE_RC_CFG_PRIV1_ROOT_CAP			0x4f8
+#define  PCIE_RC_CFG_PRIV1_ROOT_CAP_L1SS_MODE_MASK	0xf8
+
 #define PCIE_RC_DL_MDIO_ADDR				0x1100
 #define PCIE_RC_DL_MDIO_WR_DATA				0x1104
 #define PCIE_RC_DL_MDIO_RD_DATA				0x1108
 
+#define PCIE_0_RC_PL_PHY_DBG_CLKREQ2_0			0x1e30
+#define  CLKREQ2_0_CLKREQ_IN_CNT_MASK			0x3f000000
+#define  CLKREQ2_0_CLKREQ_IN_MASK			0x40000000
+
 #define PCIE_MISC_MISC_CTRL				0x4008
 #define  PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_MASK	0x80
 #define  PCIE_MISC_MISC_CTRL_PCIE_RCB_MPS_MODE_MASK	0x400
@@ -121,9 +128,12 @@
 
 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG					0x4204
 #define  PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK	0x2
+#define  PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK		0x200000
 #define  PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK		0x08000000
 #define  PCIE_BMIPS_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK		0x00800000
-
+#define  PCIE_CLKREQ_MASK \
+	  (PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK | \
+	   PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK)
 
 #define PCIE_INTR2_CPU_BASE		0x4300
 #define PCIE_MSI_INTR2_BASE		0x4500
@@ -1024,13 +1034,58 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
 	return 0;
 }
 
+static void brcm_config_clkreq(struct brcm_pcie *pcie)
+{
+	bool l1ss = of_property_read_bool(pcie->np, "brcm,enable-l1ss");
+	void __iomem *base = pcie->base;
+	u32 clkreq_set, tmp = readl(base + PCIE_0_RC_PL_PHY_DBG_CLKREQ2_0);
+	bool clkreq_in_seen;
+
+	/*
+	 * We have "seen" CLKREQ# if it is asserted or has been in the past.
+	 * Note that the CLKREQ_IN_MASK is 1 if CLKREQ# is asserted.
+	 */
+	clkreq_in_seen = !!(tmp & CLKREQ2_0_CLKREQ_IN_MASK) ||
+		!!FIELD_GET(CLKREQ2_0_CLKREQ_IN_CNT_MASK, tmp);
+
+	/* Start with safest setting where we provide refclk regardless */
+	clkreq_set = readl(pcie->base + PCIE_MISC_HARD_PCIE_HARD_DEBUG) &
+		~PCIE_CLKREQ_MASK;
+
+	if (l1ss && IS_ENABLED(CONFIG_PCIEASPM)) {
+		/*
+		 * Note: For boards using a mini-card connector, this mode
+		 * (L1SS CLKREQ# mode) may not meet the TCRLon maximum time
+		 * of 400ns, as specified in 3.2.5.2.2 of the PCI Express
+		 * Mini CEM 2.0 specification.
+		 */
+		clkreq_set |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK;
+		dev_info(pcie->dev, "bi-dir CLKREQ# for L1SS power savings");
+	} else {
+		if (clkreq_in_seen && IS_ENABLED(CONFIG_PCIEASPM)) {
+			clkreq_set |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK;
+			dev_info(pcie->dev, "uni-dir CLKREQ# for L0s, L1 ASPM\n");
+		} else {
+			dev_info(pcie->dev, "CLKREQ# ignored; no ASPM\n");
+			/* Might as well unadvertise ASPM */
+			tmp = readl(base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY) &
+				~PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK;
+			writel(tmp, base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
+		}
+		/* Setting the field to 2 unadvertises L1SS support */
+		tmp = readl(base + PCIE_RC_CFG_PRIV1_ROOT_CAP);
+		u32p_replace_bits(&tmp, 2, PCIE_RC_CFG_PRIV1_ROOT_CAP_L1SS_MODE_MASK);
+		writel(tmp, base + PCIE_RC_CFG_PRIV1_ROOT_CAP);
+	}
+	writel(clkreq_set, pcie->base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
+}
+
 static int brcm_pcie_start_link(struct brcm_pcie *pcie)
 {
 	struct device *dev = pcie->dev;
 	void __iomem *base = pcie->base;
 	u16 nlw, cls, lnksta;
 	bool ssc_good = false;
-	u32 tmp;
 	int ret, i;
 
 	/* Unassert the fundamental reset */
@@ -1055,6 +1110,8 @@ static int brcm_pcie_start_link(struct brcm_pcie *pcie)
 		return -ENODEV;
 	}
 
+	brcm_config_clkreq(pcie);
+
 	if (pcie->gen)
 		brcm_pcie_set_gen(pcie, pcie->gen);
 
@@ -1073,14 +1130,6 @@ static int brcm_pcie_start_link(struct brcm_pcie *pcie)
 		 pci_speed_string(pcie_link_speed[cls]), nlw,
 		 ssc_good ? "(SSC)" : "(!SSC)");
 
-	/*
-	 * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1
-	 * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1.
-	 */
-	tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
-	tmp |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK;
-	writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
-
 	return 0;
 }
 
-- 
2.17.1


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[PATCH v6 3/5] PCI: brcmstb: Set higher value for internal bus timeout

[Jim Quinlan]

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During long periods of the PCIe RC HW being in an L1SS sleep state, there
may be a timeout on an internal bus access, even though there may not be
any PCIe access involved.  Such a timeout will cause a subsequent CPU
abort.

So, when "brcm,enable-l1ss" is observed, we increase the timeout value to
four seconds instead of using its HW default.

Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
Tested-by: Florian Fainelli <f.fainelli@gmail.com>
---
 drivers/pci/controller/pcie-brcmstb.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index d30636a725d7..fe0415a98c63 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -1034,6 +1034,21 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
 	return 0;
 }
 
+/*
+ * This extends the timeout period for an access to an internal bus.  This
+ * access timeout may occur during L1SS sleep periods even without the
+ * presence of a PCIe access.
+ */
+static void brcm_extend_rbus_timeout(struct brcm_pcie *pcie)
+{
+	/* TIMEOUT register is two registers before RGR1_SW_INIT_1 */
+	const unsigned int REG_OFFSET = PCIE_RGR1_SW_INIT_1(pcie) - 8;
+	u32 timeout_us = 4000000; /* 4 seconds, our setting for L1SS */
+
+	/* Each unit in timeout register is 1/216,000,000 seconds */
+	writel(216 * timeout_us, pcie->base + REG_OFFSET);
+}
+
 static void brcm_config_clkreq(struct brcm_pcie *pcie)
 {
 	bool l1ss = of_property_read_bool(pcie->np, "brcm,enable-l1ss");
@@ -1059,6 +1074,7 @@ static void brcm_config_clkreq(struct brcm_pcie *pcie)
 		 * of 400ns, as specified in 3.2.5.2.2 of the PCI Express
 		 * Mini CEM 2.0 specification.
 		 */
+		brcm_extend_rbus_timeout(pcie);
 		clkreq_set |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK;
 		dev_info(pcie->dev, "bi-dir CLKREQ# for L1SS power savings");
 	} else {
-- 
2.17.1


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[PATCH v6 4/5] PCI: brcmstb: Assert PERST# on BCM2711

[Jim Quinlan]

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The current PCIe driver assumes PERST# is asserted when probe() is invoked.
Some older versions of the 2711/RPi bootloader left PERST# unasserted, as
the Raspian OS does assert PERST# on probe().  For this reason, we assert
PERST# for BCM2711 SOCs (i.e. RPi).

Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
---
 drivers/pci/controller/pcie-brcmstb.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index fe0415a98c63..7b698a9a851e 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -884,6 +884,11 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
 
 	/* Reset the bridge */
 	pcie->bridge_sw_init_set(pcie, 1);
+
+	/* Ensure that PERST# is asserted; some bootloaders may deassert it. */
+	if (pcie->type == BCM2711)
+		pcie->perst_set(pcie, 1);
+
 	usleep_range(100, 200);
 
 	/* Take the bridge out of reset */
-- 
2.17.1


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[PATCH v6 5/5] PCI: brcmstb: Remove stale comment

[Jim Quinlan]

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A comment says that Multi-MSI is not supported by the driver.
A past commit [1] added this feature, so the comment is
incorrect and is removed.

[1] commit 198acab1772f22f2 ("PCI: brcmstb: Enable Multi-MSI")

Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
---
 drivers/pci/controller/pcie-brcmstb.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index 7b698a9a851e..acd478edbe2f 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -449,7 +449,6 @@ static struct irq_chip brcm_msi_irq_chip = {
 };
 
 static struct msi_domain_info brcm_msi_domain_info = {
-	/* Multi MSI is supported by the controller, but not by this driver */
 	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
 		   MSI_FLAG_MULTI_PCI_MSI),
 	.chip	= &brcm_msi_irq_chip,
-- 
2.17.1


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Re: [PATCH v6 0/5] PCI: brcmstb: Configure appropriate HW CLKREQ# mode

[Cyril Brulebois]

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Hi Jim,

Jim Quinlan <james.quinlan@broadcom.com> (2023-06-23):
> v6 -- No code has been changed.
>    -- Changed commit subject and comment in "#PERST" commit (Bjorn, Cyril)
>    -- Changed sign-off and author email address for all commits.
>       This was due to a change in Broadcom's upstreaming policy.

I've just run some more tests to be on the safe side, and I can confirm
everything is still looking good with the updated series and the updated
base commit.

Test setup:
-----------

 - using a $CM with the 20230111 EEPROM
 - on the same CM4 IO Board
 - with a $PCIE board (PCIe to multiple USB ports)
 - and the same Samsung USB flash drive.

where $CM is one of:

 - CM4 Lite Rev 1.0
 - CM4 8/32 Rev 1.0
 - CM4 4/32 Rev 1.1

and $PCIE is one of:

 - SupaHub PCE6U1C-R02, VER 006
 - SupaHub PCE6U1C-R02, VER 006S


Results:
--------

 1. With an unpatched kernel, I'm getting the dreaded Serror for all
    $CM/$PCIE combinations. That's reproducible with:
     - the 6.1.y kernel shipped in Debian 12;
     - a locally-built v6.4-rc7-194-g8a28a0b6f1a1d kernel.

 2. With a patched kernel (v6.4-rc7-194-g8a28a0b6f1a1d + this series),
    for all $CM/$PCIE combinations, I'm getting a system that boots,
    sees the flash drive, and gives decent read performance on the USB
    flash drive (200+ MB/s on the CM4 Lite, 220+ MB/s on the non-Lite
    versions).


In passing, since that looks like it could be merged finally: I suppose
it's fair to say this series adds support for hardware that wasn't
working before, which means it's not a candidate for inclusion via
stable@ (even if it gets rid of a nasty failure to boot depending on
what hardware is plugged in at that time)?

In other words, downstream distributions should be expected to either
adjust their build systems to pick some future Linux release or consider
backporting this series on their own, to each base Linux version they
support?


Thanks again for all the help figuring this out.


Cheers,
-- 
Cyril Brulebois (kibi@debian.org)            <https://debamax.com/>
D-I release manager -- Release team member -- Freelance Consultant

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Re: [PATCH v6 3/5] PCI: brcmstb: Set higher value for internal bus timeout

[Lorenzo Pieralisi]

On Fri, Jun 23, 2023 at 10:40:56AM -0400, Jim Quinlan wrote:
> During long periods of the PCIe RC HW being in an L1SS sleep state, there
> may be a timeout on an internal bus access, even though there may not be
> any PCIe access involved.  Such a timeout will cause a subsequent CPU
> abort.
> 
> So, when "brcm,enable-l1ss" is observed, we increase the timeout value to
> four seconds instead of using its HW default.
> 
> Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
> Tested-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
>  drivers/pci/controller/pcie-brcmstb.c | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
> index d30636a725d7..fe0415a98c63 100644
> --- a/drivers/pci/controller/pcie-brcmstb.c
> +++ b/drivers/pci/controller/pcie-brcmstb.c
> @@ -1034,6 +1034,21 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
>  	return 0;
>  }
>  
> +/*
> + * This extends the timeout period for an access to an internal bus.  This
> + * access timeout may occur during L1SS sleep periods even without the
> + * presence of a PCIe access.
> + */
> +static void brcm_extend_rbus_timeout(struct brcm_pcie *pcie)
> +{
> +	/* TIMEOUT register is two registers before RGR1_SW_INIT_1 */
> +	const unsigned int REG_OFFSET = PCIE_RGR1_SW_INIT_1(pcie) - 8;

Nit: you could define an offset for the TIMEOUT register, if that makes
it any cleaner, up to you.

> +	u32 timeout_us = 4000000; /* 4 seconds, our setting for L1SS */

It would be useful to describe why this has to be 4 seconds in case
someone in the future will have to change it.

Thanks,
Lorenzo

> +	/* Each unit in timeout register is 1/216,000,000 seconds */
> +	writel(216 * timeout_us, pcie->base + REG_OFFSET);
> +}
> +
>  static void brcm_config_clkreq(struct brcm_pcie *pcie)
>  {
>  	bool l1ss = of_property_read_bool(pcie->np, "brcm,enable-l1ss");
> @@ -1059,6 +1074,7 @@ static void brcm_config_clkreq(struct brcm_pcie *pcie)
>  		 * of 400ns, as specified in 3.2.5.2.2 of the PCI Express
>  		 * Mini CEM 2.0 specification.
>  		 */
> +		brcm_extend_rbus_timeout(pcie);
>  		clkreq_set |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK;
>  		dev_info(pcie->dev, "bi-dir CLKREQ# for L1SS power savings");
>  	} else {
> -- 
> 2.17.1
> 

Re: [PATCH v6 3/5] PCI: brcmstb: Set higher value for internal bus timeout

[Jim Quinlan]

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On Fri, Jul 28, 2023 at 12:15 PM Jim Quinlan <james.quinlan@broadcom.com> wrote:
>
>
>
> On Thu, Jul 27, 2023, 10:44 PM Lorenzo Pieralisi <lpieralisi@kernel.org> wrote:
>>
>> On Fri, Jun 23, 2023 at 10:40:56AM -0400, Jim Quinlan wrote:
>> > During long periods of the PCIe RC HW being in an L1SS sleep state, there
>> > may be a timeout on an internal bus access, even though there may not be
>> > any PCIe access involved.  Such a timeout will cause a subsequent CPU
>> > abort.
>> >
>> > So, when "brcm,enable-l1ss" is observed, we increase the timeout value to
>> > four seconds instead of using its HW default.
>> >
>> > Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
>> > Tested-by: Florian Fainelli <f.fainelli@gmail.com>
>> > ---
>> >  drivers/pci/controller/pcie-brcmstb.c | 16 ++++++++++++++++
>> >  1 file changed, 16 insertions(+)
>> >
>> > diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
>> > index d30636a725d7..fe0415a98c63 100644
>> > --- a/drivers/pci/controller/pcie-brcmstb.c
>> > +++ b/drivers/pci/controller/pcie-brcmstb.c
>> > @@ -1034,6 +1034,21 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
>> >       return 0;
>> >  }
>> >
>> > +/*
>> > + * This extends the timeout period for an access to an internal bus.  This
>> > + * access timeout may occur during L1SS sleep periods even without the
>> > + * presence of a PCIe access.
>> > + */
>> > +static void brcm_extend_rbus_timeout(struct brcm_pcie *pcie)
>> > +{
>> > +     /* TIMEOUT register is two registers before RGR1_SW_INIT_1 */
>> > +     const unsigned int REG_OFFSET = PCIE_RGR1_SW_INIT_1(pcie) - 8;
>>
>> Nit: you could define an offset for the TIMEOUT register, if that makes
>> it any cleaner, up to you.
>>
>> > +     u32 timeout_us = 4000000; /* 4 seconds, our setting for L1SS */
>>
>> It would be useful to describe why this has to be 4 seconds in case
>> someone in the future will have to change it.
>
>
> Hello,
> IIRC our customer requested 2s and we doubled it.  Bjorn, can you please add this comment or a paraphrase of it before applying -- I'm currently on vacation.

Hello Bjorn,

Is the above request okay with you?  What is the status of these
commits -- will they be applied to pci-next in the near future?

Regards,
Jim Quinlan
Broadcom STB

>
> Regards,
> Jim Quinlan
>
>>
>> Thanks,
>> Lorenzo
>>
>> > +     /* Each unit in timeout register is 1/216,000,000 seconds */
>> > +     writel(216 * timeout_us, pcie->base + REG_OFFSET);
>> > +}
>> > +
>> >  static void brcm_config_clkreq(struct brcm_pcie *pcie)
>> >  {
>> >       bool l1ss = of_property_read_bool(pcie->np, "brcm,enable-l1ss");
>> > @@ -1059,6 +1074,7 @@ static void brcm_config_clkreq(struct brcm_pcie *pcie)
>> >                * of 400ns, as specified in 3.2.5.2.2 of the PCI Express
>> >                * Mini CEM 2.0 specification.
>> >                */
>> > +             brcm_extend_rbus_timeout(pcie);
>> >               clkreq_set |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK;
>> >               dev_info(pcie->dev, "bi-dir CLKREQ# for L1SS power savings");
>> >       } else {
>> > --
>> > 2.17.1
>> >
>>
>>

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Re: [PATCH v6 3/5] PCI: brcmstb: Set higher value for internal bus timeout

[Bjorn Helgaas]

On Mon, Aug 14, 2023 at 03:30:07PM -0400, Jim Quinlan wrote:
> On Fri, Jul 28, 2023 at 12:15 PM Jim Quinlan <james.quinlan@broadcom.com> wrote:
> > On Thu, Jul 27, 2023, 10:44 PM Lorenzo Pieralisi <lpieralisi@kernel.org> wrote:
> >> On Fri, Jun 23, 2023 at 10:40:56AM -0400, Jim Quinlan wrote:
> >> > During long periods of the PCIe RC HW being in an L1SS sleep state, there
> >> > may be a timeout on an internal bus access, even though there may not be
> >> > any PCIe access involved.  Such a timeout will cause a subsequent CPU
> >> > abort.
> >> >
> >> > So, when "brcm,enable-l1ss" is observed, we increase the timeout value to
> >> > four seconds instead of using its HW default.
> >> >
> >> > Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
> >> > Tested-by: Florian Fainelli <f.fainelli@gmail.com>
> >> > ---
> >> >  drivers/pci/controller/pcie-brcmstb.c | 16 ++++++++++++++++
> >> >  1 file changed, 16 insertions(+)
> >> >
> >> > diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
> >> > index d30636a725d7..fe0415a98c63 100644
> >> > --- a/drivers/pci/controller/pcie-brcmstb.c
> >> > +++ b/drivers/pci/controller/pcie-brcmstb.c
> >> > @@ -1034,6 +1034,21 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
> >> >       return 0;
> >> >  }
> >> >
> >> > +/*
> >> > + * This extends the timeout period for an access to an internal bus.  This
> >> > + * access timeout may occur during L1SS sleep periods even without the
> >> > + * presence of a PCIe access.
> >> > + */
> >> > +static void brcm_extend_rbus_timeout(struct brcm_pcie *pcie)
> >> > +{
> >> > +     /* TIMEOUT register is two registers before RGR1_SW_INIT_1 */
> >> > +     const unsigned int REG_OFFSET = PCIE_RGR1_SW_INIT_1(pcie) - 8;
> >>
> >> Nit: you could define an offset for the TIMEOUT register, if that makes
> >> it any cleaner, up to you.
> >>
> >> > +     u32 timeout_us = 4000000; /* 4 seconds, our setting for L1SS */
> >>
> >> It would be useful to describe why this has to be 4 seconds in case
> >> someone in the future will have to change it.
> >
> > IIRC our customer requested 2s and we doubled it.  Bjorn, can you
> > please add this comment or a paraphrase of it before applying --
> > I'm currently on vacation.
> 
> Is the above request okay with you?  What is the status of these
> commits -- will they be applied to pci-next in the near future?

The "brcm,enable-l1ss" DT property is either unnecessary or an
indication of a hardware defect in the controller.

Requiring the property is a terrible user experience, completely
antithetical to the PCI compatibility story, and per the conversation
at [1], there are no known problems that would occur if we ignored
"brcm,enable-l1ss" and always configured mode (c) ("Bidirectional
CLKREQ# for L1SS capable devices").

Even when configured as mode (c), L1SS is not *always* enabled.  It's
certainly not enabled before ASPM init, and users can always disable
L1SS whenever they desire via the sysfs interfaces or pcie_aspm=off,
so if there's some problem with running in mode (c) with L1SS
disabled, we're still likely to see it.

But if you want to require the DT property, I guess it's mainly an
issue for you and your customers.

So to answer your question, yes, I'm OK with this series.

Bjorn

[1] https://lore.kernel.org/r/20230428223500.23337-2-jim2101024@gmail.com

> >> > +     /* Each unit in timeout register is 1/216,000,000 seconds */
> >> > +     writel(216 * timeout_us, pcie->base + REG_OFFSET);
> >> > +}
> >> > +
> >> >  static void brcm_config_clkreq(struct brcm_pcie *pcie)
> >> >  {
> >> >       bool l1ss = of_property_read_bool(pcie->np, "brcm,enable-l1ss");
> >> > @@ -1059,6 +1074,7 @@ static void brcm_config_clkreq(struct brcm_pcie *pcie)
> >> >                * of 400ns, as specified in 3.2.5.2.2 of the PCI Express
> >> >                * Mini CEM 2.0 specification.
> >> >                */
> >> > +             brcm_extend_rbus_timeout(pcie);
> >> >               clkreq_set |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK;
> >> >               dev_info(pcie->dev, "bi-dir CLKREQ# for L1SS power savings");
> >> >       } else {

Re: [PATCH v6 3/5] PCI: brcmstb: Set higher value for internal bus timeout

[Jim Quinlan]

[-- Attachment #1: Type: text/plain, Size: 5178 bytes --]

On Mon, Aug 14, 2023 at 6:07 PM Bjorn Helgaas <helgaas@kernel.org> wrote:
>
> On Mon, Aug 14, 2023 at 03:30:07PM -0400, Jim Quinlan wrote:
> > On Fri, Jul 28, 2023 at 12:15 PM Jim Quinlan <james.quinlan@broadcom.com> wrote:
> > > On Thu, Jul 27, 2023, 10:44 PM Lorenzo Pieralisi <lpieralisi@kernel.org> wrote:
> > >> On Fri, Jun 23, 2023 at 10:40:56AM -0400, Jim Quinlan wrote:
> > >> > During long periods of the PCIe RC HW being in an L1SS sleep state, there
> > >> > may be a timeout on an internal bus access, even though there may not be
> > >> > any PCIe access involved.  Such a timeout will cause a subsequent CPU
> > >> > abort.
> > >> >
> > >> > So, when "brcm,enable-l1ss" is observed, we increase the timeout value to
> > >> > four seconds instead of using its HW default.
> > >> >
> > >> > Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
> > >> > Tested-by: Florian Fainelli <f.fainelli@gmail.com>
> > >> > ---
> > >> >  drivers/pci/controller/pcie-brcmstb.c | 16 ++++++++++++++++
> > >> >  1 file changed, 16 insertions(+)
> > >> >
> > >> > diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
> > >> > index d30636a725d7..fe0415a98c63 100644
> > >> > --- a/drivers/pci/controller/pcie-brcmstb.c
> > >> > +++ b/drivers/pci/controller/pcie-brcmstb.c
> > >> > @@ -1034,6 +1034,21 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
> > >> >       return 0;
> > >> >  }
> > >> >
> > >> > +/*
> > >> > + * This extends the timeout period for an access to an internal bus.  This
> > >> > + * access timeout may occur during L1SS sleep periods even without the
> > >> > + * presence of a PCIe access.
> > >> > + */
> > >> > +static void brcm_extend_rbus_timeout(struct brcm_pcie *pcie)
> > >> > +{
> > >> > +     /* TIMEOUT register is two registers before RGR1_SW_INIT_1 */
> > >> > +     const unsigned int REG_OFFSET = PCIE_RGR1_SW_INIT_1(pcie) - 8;
> > >>
> > >> Nit: you could define an offset for the TIMEOUT register, if that makes
> > >> it any cleaner, up to you.
> > >>
> > >> > +     u32 timeout_us = 4000000; /* 4 seconds, our setting for L1SS */
> > >>
> > >> It would be useful to describe why this has to be 4 seconds in case
> > >> someone in the future will have to change it.
> > >
> > > IIRC our customer requested 2s and we doubled it.  Bjorn, can you
> > > please add this comment or a paraphrase of it before applying --
> > > I'm currently on vacation.
> >
> > Is the above request okay with you?  What is the status of these
> > commits -- will they be applied to pci-next in the near future?
>
> The "brcm,enable-l1ss" DT property is either unnecessary or an
> indication of a hardware defect in the controller.

Agree.
>
> Requiring the property is a terrible user experience, completely
> antithetical to the PCI compatibility story, and per the conversation
> at [1], there are no known problems that would occur if we ignored
> "brcm,enable-l1ss" and always configured mode (c) ("Bidirectional
> CLKREQ# for L1SS capable devices").

Agree, but I don't believe this issue will be in the top five problems of RPi
folks getting their PCIe systems to work.

>
> Even when configured as mode (c), L1SS is not *always* enabled.  It's
> certainly not enabled before ASPM init, and users can always disable
> L1SS whenever they desire via the sysfs interfaces or pcie_aspm=off,
> so if there's some problem with running in mode (c) with L1SS
> disabled, we're still likely to see it.
>
> But if you want to require the DT property, I guess it's mainly an
> issue for you and your customers.

I believe this to be the best solution for the current HW.  As Cyril
and I have noted, it
allows some platforms to work that were not working previously.

So I am all for these commits being applied.

FWIW, I am currently advocating changing the PCIe HW core to
seamlessly handle all
of the ASPM (sub)states transitions w/o awkward SW driver
intervention.  I am also
advocating other changes as well.  So there is a possibility things will
be changed for the better in the future.

Regards,
Jim Quinlan
Broadcom STB

>
> So to answer your question, yes, I'm OK with this series.
>
> Bjorn
>
> [1] https://lore.kernel.org/r/20230428223500.23337-2-jim2101024@gmail.com
>
> > >> > +     /* Each unit in timeout register is 1/216,000,000 seconds */
> > >> > +     writel(216 * timeout_us, pcie->base + REG_OFFSET);
> > >> > +}
> > >> > +
> > >> >  static void brcm_config_clkreq(struct brcm_pcie *pcie)
> > >> >  {
> > >> >       bool l1ss = of_property_read_bool(pcie->np, "brcm,enable-l1ss");
> > >> > @@ -1059,6 +1074,7 @@ static void brcm_config_clkreq(struct brcm_pcie *pcie)
> > >> >                * of 400ns, as specified in 3.2.5.2.2 of the PCI Express
> > >> >                * Mini CEM 2.0 specification.
> > >> >                */
> > >> > +             brcm_extend_rbus_timeout(pcie);
> > >> >               clkreq_set |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK;
> > >> >               dev_info(pcie->dev, "bi-dir CLKREQ# for L1SS power savings");
> > >> >       } else {

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Re: [PATCH v6 0/5] PCI: brcmstb: Configure appropriate HW CLKREQ# mode

[Lorenzo Pieralisi]

On Fri, Jun 23, 2023 at 10:40:53AM -0400, Jim Quinlan wrote:
> v6 -- No code has been changed.
>    -- Changed commit subject and comment in "#PERST" commit (Bjorn, Cyril)
>    -- Changed sign-off and author email address for all commits.
>       This was due to a change in Broadcom's upstreaming policy.
> 
> v5 -- Remove DT property "brcm,completion-timeout-us" from	 
>       "DT bindings" commit.  Although this error may be reported	 
>       as a completion timeout, its cause was traced to an	 
>       internal bus timeout which may occur even when there is	 
>       no PCIe access being processed.  We set a timeout of four	 
>       seconds only if we are operating in "L1SS CLKREQ#" mode.
>    -- Correct CEM 2.0 reference provided by HW engineer,
>       s/3.2.5.2.5/3.2.5.2.2/ (Bjorn)
>    -- Add newline to dev_info() string (Stefan)
>    -- Change variable rval to unsigned (Stefan)
>    -- s/implementaion/implementation/ (Bjorn)
>    -- s/superpowersave/powersupersave/ (Bjorn)
>    -- Slightly modify message on "PERST#" commit.
>    -- Rebase to torvalds master
> 
> v4 -- New commit that asserts PERST# for 2711/RPi SOCs at PCIe RC
>       driver probe() time.  This is done in Raspian Linux and its
>       absence may be the cause of a failing test case.
>    -- New commit that removes stale comment.
> 
> v3 -- Rewrote commit msgs and comments refering panics if L1SS
>       is enabled/disabled; the code snippet that unadvertises L1SS
>       eliminates the panic scenario. (Bjorn)
>    -- Add reference for "400ns of CLKREQ# assertion" blurb (Bjorn)
>    -- Put binding names in DT commit Subject (Bjorn)
>    -- Add a verb to a commit's subject line (Bjorn)
>    -- s/accomodat(\w+)/accommodat$1/g (Bjorn)
>    -- Rewrote commit msgs and comments refering panics if L1SS
>       is enabled/disabled; the code snippet that unadvertises L1SS
>       eliminates the panic scenario. (Bjorn)
> 
> v2 -- Changed binding property 'brcm,completion-timeout-msec' to
>       'brcm,completion-timeout-us'.  (StefanW for standard suffix).
>    -- Warn when clamping timeout value, and include clamped
>       region in message. Also add min and max in YAML. (StefanW)
>    -- Qualify description of "brcm,completion-timeout-us" so that
>       it refers to PCIe transactions. (StefanW)
>    -- Remvove mention of Linux specifics in binding description. (StefanW)
>    -- s/clkreq#/CLKREQ#/g (Bjorn)
>    -- Refactor completion-timeout-us code to compare max and min to
>       value given by the property (as opposed to the computed value).
> 
> v1 -- The current driver assumes the downstream devices can
>       provide CLKREQ# for ASPM.  These commits accomodate devices
>       w/ or w/o clkreq# and also handle L1SS-capable devices.
> 
>    -- The Raspian Linux folks have already been using a PCIe RC
>       property "brcm,enable-l1ss".  These commits use the same
>       property, in a backward-compatible manner, and the implementaion
>       adds more detail and also automatically identifies devices w/o
>       a clkreq# signal, i.e. most devices plugged into an RPi CM4
>       IO board.
> 
> 
> Jim Quinlan (5):
>   dt-bindings: PCI: brcmstb: Add brcm,enable-l1ss property
>   PCI: brcmstb: Configure HW CLKREQ# mode appropriate for downstream
>     device

I am not merging the first two patches since the discussion thread
is still open and I'd like to understand better what can/should be
done, sorry.

>   PCI: brcmstb: Set higher value for internal bus timeout
>   PCI: brcmstb: Assert PERST# on BCM2711
>   PCI: brcmstb: Remove stale comment

Is it OK to apply these three on their own ? Overall it would be
great to avoid mixing patches with different end goals in a single
series.

Thanks,
Lorenzo

>  .../bindings/pci/brcm,stb-pcie.yaml           |  9 ++
>  drivers/pci/controller/pcie-brcmstb.c         | 91 ++++++++++++++++---
>  2 files changed, 89 insertions(+), 11 deletions(-)
> 
> 
> base-commit: 8a28a0b6f1a1dcbf5a834600a9acfbe2ba51e5eb
> -- 
> 2.17.1
> 

Re: [PATCH v6 0/5] PCI: brcmstb: Configure appropriate HW CLKREQ# mode

[Jim Quinlan]

[-- Attachment #1: Type: text/plain, Size: 5667 bytes --]

On Mon, Aug 21, 2023 at 4:35 AM Lorenzo Pieralisi <lpieralisi@kernel.org> wrote:
>
> On Fri, Jun 23, 2023 at 10:40:53AM -0400, Jim Quinlan wrote:
> > v6 -- No code has been changed.
> >    -- Changed commit subject and comment in "#PERST" commit (Bjorn, Cyril)
> >    -- Changed sign-off and author email address for all commits.
> >       This was due to a change in Broadcom's upstreaming policy.
> >
> > v5 -- Remove DT property "brcm,completion-timeout-us" from
> >       "DT bindings" commit.  Although this error may be reported
> >       as a completion timeout, its cause was traced to an
> >       internal bus timeout which may occur even when there is
> >       no PCIe access being processed.  We set a timeout of four
> >       seconds only if we are operating in "L1SS CLKREQ#" mode.
> >    -- Correct CEM 2.0 reference provided by HW engineer,
> >       s/3.2.5.2.5/3.2.5.2.2/ (Bjorn)
> >    -- Add newline to dev_info() string (Stefan)
> >    -- Change variable rval to unsigned (Stefan)
> >    -- s/implementaion/implementation/ (Bjorn)
> >    -- s/superpowersave/powersupersave/ (Bjorn)
> >    -- Slightly modify message on "PERST#" commit.
> >    -- Rebase to torvalds master
> >
> > v4 -- New commit that asserts PERST# for 2711/RPi SOCs at PCIe RC
> >       driver probe() time.  This is done in Raspian Linux and its
> >       absence may be the cause of a failing test case.
> >    -- New commit that removes stale comment.
> >
> > v3 -- Rewrote commit msgs and comments refering panics if L1SS
> >       is enabled/disabled; the code snippet that unadvertises L1SS
> >       eliminates the panic scenario. (Bjorn)
> >    -- Add reference for "400ns of CLKREQ# assertion" blurb (Bjorn)
> >    -- Put binding names in DT commit Subject (Bjorn)
> >    -- Add a verb to a commit's subject line (Bjorn)
> >    -- s/accomodat(\w+)/accommodat$1/g (Bjorn)
> >    -- Rewrote commit msgs and comments refering panics if L1SS
> >       is enabled/disabled; the code snippet that unadvertises L1SS
> >       eliminates the panic scenario. (Bjorn)
> >
> > v2 -- Changed binding property 'brcm,completion-timeout-msec' to
> >       'brcm,completion-timeout-us'.  (StefanW for standard suffix).
> >    -- Warn when clamping timeout value, and include clamped
> >       region in message. Also add min and max in YAML. (StefanW)
> >    -- Qualify description of "brcm,completion-timeout-us" so that
> >       it refers to PCIe transactions. (StefanW)
> >    -- Remvove mention of Linux specifics in binding description. (StefanW)
> >    -- s/clkreq#/CLKREQ#/g (Bjorn)
> >    -- Refactor completion-timeout-us code to compare max and min to
> >       value given by the property (as opposed to the computed value).
> >
> > v1 -- The current driver assumes the downstream devices can
> >       provide CLKREQ# for ASPM.  These commits accomodate devices
> >       w/ or w/o clkreq# and also handle L1SS-capable devices.
> >
> >    -- The Raspian Linux folks have already been using a PCIe RC
> >       property "brcm,enable-l1ss".  These commits use the same
> >       property, in a backward-compatible manner, and the implementaion
> >       adds more detail and also automatically identifies devices w/o
> >       a clkreq# signal, i.e. most devices plugged into an RPi CM4
> >       IO board.
> >
> >
> > Jim Quinlan (5):
> >   dt-bindings: PCI: brcmstb: Add brcm,enable-l1ss property
> >   PCI: brcmstb: Configure HW CLKREQ# mode appropriate for downstream
> >     device
>
> I am not merging the first two patches since the discussion thread
> is still open and I'd like to understand better what can/should be
> done, sorry.

Hello Lorenzo,

This patch-set has been stable for months, V5 was out early May and
the V6 changes
did not involve code.  I'm a little surprised that you are voicing
concern at this stage.

The previous discussions covered all aspects of these commits AFAICT.
Please  review
them and the commit messages and let me know what issues you do not understand
or any topics that were not considered.

Are you concerned about the Broadcom STB/CM community  or the RPi community?
For the former, I have direct communication w/ our customers and none of them
are even close to using upstream (they may backport my commits).  For
the latter, I have
tested these commits on the official RPi4 and CM4 IO platforms, and
Cyril has also put in
an admiral amount of testing.

Note that I have on my desk a CM4 IO board w/ a conventional PCIe
device, and it does not boot
upstream master Linux until these patches are applied.

Further, Raspian OS has already introduced the "brcm,enable-l1ss"
property but did not upstream it, and
my commits are backwards compatible with this.

>
> >   PCI: brcmstb: Set higher value for internal bus timeout
> >   PCI: brcmstb: Assert PERST# on BCM2711
> >   PCI: brcmstb: Remove stale comment
>
> Is it OK to apply these three on their own ? Overall it would be
> great to avoid mixing patches with different end goals in a single
> series.

Well, they are related for one customer who wants to use L1SS power
savings AND require
a long  period for the internal timeout.  But, yes, these commits are
fine  to apply
independently.

Regards,
Jim Quinlan
Broadcom STB

>
> Thanks,
> Lorenzo
>
> >  .../bindings/pci/brcm,stb-pcie.yaml           |  9 ++
> >  drivers/pci/controller/pcie-brcmstb.c         | 91 ++++++++++++++++---
> >  2 files changed, 89 insertions(+), 11 deletions(-)
> >
> >
> > base-commit: 8a28a0b6f1a1dcbf5a834600a9acfbe2ba51e5eb
> > --
> > 2.17.1
> >
>
>

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Re: [PATCH v6 0/5] PCI: brcmstb: Configure appropriate HW CLKREQ# mode

[Lorenzo Pieralisi]

On Mon, Aug 21, 2023 at 08:15:02AM -0400, Jim Quinlan wrote:
> On Mon, Aug 21, 2023 at 4:35 AM Lorenzo Pieralisi <lpieralisi@kernel.org> wrote:
> >
> > On Fri, Jun 23, 2023 at 10:40:53AM -0400, Jim Quinlan wrote:
> > > v6 -- No code has been changed.
> > >    -- Changed commit subject and comment in "#PERST" commit (Bjorn, Cyril)
> > >    -- Changed sign-off and author email address for all commits.
> > >       This was due to a change in Broadcom's upstreaming policy.
> > >
> > > v5 -- Remove DT property "brcm,completion-timeout-us" from
> > >       "DT bindings" commit.  Although this error may be reported
> > >       as a completion timeout, its cause was traced to an
> > >       internal bus timeout which may occur even when there is
> > >       no PCIe access being processed.  We set a timeout of four
> > >       seconds only if we are operating in "L1SS CLKREQ#" mode.
> > >    -- Correct CEM 2.0 reference provided by HW engineer,
> > >       s/3.2.5.2.5/3.2.5.2.2/ (Bjorn)
> > >    -- Add newline to dev_info() string (Stefan)
> > >    -- Change variable rval to unsigned (Stefan)
> > >    -- s/implementaion/implementation/ (Bjorn)
> > >    -- s/superpowersave/powersupersave/ (Bjorn)
> > >    -- Slightly modify message on "PERST#" commit.
> > >    -- Rebase to torvalds master
> > >
> > > v4 -- New commit that asserts PERST# for 2711/RPi SOCs at PCIe RC
> > >       driver probe() time.  This is done in Raspian Linux and its
> > >       absence may be the cause of a failing test case.
> > >    -- New commit that removes stale comment.
> > >
> > > v3 -- Rewrote commit msgs and comments refering panics if L1SS
> > >       is enabled/disabled; the code snippet that unadvertises L1SS
> > >       eliminates the panic scenario. (Bjorn)
> > >    -- Add reference for "400ns of CLKREQ# assertion" blurb (Bjorn)
> > >    -- Put binding names in DT commit Subject (Bjorn)
> > >    -- Add a verb to a commit's subject line (Bjorn)
> > >    -- s/accomodat(\w+)/accommodat$1/g (Bjorn)
> > >    -- Rewrote commit msgs and comments refering panics if L1SS
> > >       is enabled/disabled; the code snippet that unadvertises L1SS
> > >       eliminates the panic scenario. (Bjorn)
> > >
> > > v2 -- Changed binding property 'brcm,completion-timeout-msec' to
> > >       'brcm,completion-timeout-us'.  (StefanW for standard suffix).
> > >    -- Warn when clamping timeout value, and include clamped
> > >       region in message. Also add min and max in YAML. (StefanW)
> > >    -- Qualify description of "brcm,completion-timeout-us" so that
> > >       it refers to PCIe transactions. (StefanW)
> > >    -- Remvove mention of Linux specifics in binding description. (StefanW)
> > >    -- s/clkreq#/CLKREQ#/g (Bjorn)
> > >    -- Refactor completion-timeout-us code to compare max and min to
> > >       value given by the property (as opposed to the computed value).
> > >
> > > v1 -- The current driver assumes the downstream devices can
> > >       provide CLKREQ# for ASPM.  These commits accomodate devices
> > >       w/ or w/o clkreq# and also handle L1SS-capable devices.
> > >
> > >    -- The Raspian Linux folks have already been using a PCIe RC
> > >       property "brcm,enable-l1ss".  These commits use the same
> > >       property, in a backward-compatible manner, and the implementaion
> > >       adds more detail and also automatically identifies devices w/o
> > >       a clkreq# signal, i.e. most devices plugged into an RPi CM4
> > >       IO board.
> > >
> > >
> > > Jim Quinlan (5):
> > >   dt-bindings: PCI: brcmstb: Add brcm,enable-l1ss property
> > >   PCI: brcmstb: Configure HW CLKREQ# mode appropriate for downstream
> > >     device
> >
> > I am not merging the first two patches since the discussion thread
> > is still open and I'd like to understand better what can/should be
> > done, sorry.
> 
> Hello Lorenzo,
> 
> This patch-set has been stable for months, V5 was out early May and
> the V6 changes
> did not involve code.  I'm a little surprised that you are voicing
> concern at this stage.
> 
> The previous discussions covered all aspects of these commits AFAICT.
> Please  review
> them and the commit messages and let me know what issues you do not understand
> or any topics that were not considered.

I disagree with the reasoning behind "brcm,enable-l1ss" property usage
instead of a command line option - at least I would like to get a
comment from DT maintainers about it.

I think Bjorn made the point consistently and I also think he is right.

I would like to get Rob's opinion on this. I know he acked the DT
bindings (I have a comment on those too) but regardless, it is clearly a
property used for what is a command line configuration parameter,
no two ways about it.

Thanks,
Lorenzo

> 
> Are you concerned about the Broadcom STB/CM community  or the RPi community?
> For the former, I have direct communication w/ our customers and none of them
> are even close to using upstream (they may backport my commits).  For
> the latter, I have
> tested these commits on the official RPi4 and CM4 IO platforms, and
> Cyril has also put in
> an admiral amount of testing.
> 
> Note that I have on my desk a CM4 IO board w/ a conventional PCIe
> device, and it does not boot
> upstream master Linux until these patches are applied.
> 
> Further, Raspian OS has already introduced the "brcm,enable-l1ss"
> property but did not upstream it, and
> my commits are backwards compatible with this.
> 
> >
> > >   PCI: brcmstb: Set higher value for internal bus timeout
> > >   PCI: brcmstb: Assert PERST# on BCM2711
> > >   PCI: brcmstb: Remove stale comment
> >
> > Is it OK to apply these three on their own ? Overall it would be
> > great to avoid mixing patches with different end goals in a single
> > series.
> 
> Well, they are related for one customer who wants to use L1SS power
> savings AND require
> a long  period for the internal timeout.  But, yes, these commits are
> fine  to apply
> independently.
> 
> Regards,
> Jim Quinlan
> Broadcom STB
> 
> >
> > Thanks,
> > Lorenzo
> >
> > >  .../bindings/pci/brcm,stb-pcie.yaml           |  9 ++
> > >  drivers/pci/controller/pcie-brcmstb.c         | 91 ++++++++++++++++---
> > >  2 files changed, 89 insertions(+), 11 deletions(-)
> > >
> > >
> > > base-commit: 8a28a0b6f1a1dcbf5a834600a9acfbe2ba51e5eb
> > > --
> > > 2.17.1
> > >
> >
> >

Re: [PATCH v6 1/5] dt-bindings: PCI: brcmstb: Add brcm,enable-l1ss property

[Lorenzo Pieralisi]

On Fri, Jun 23, 2023 at 10:40:54AM -0400, Jim Quinlan wrote:
> This commit adds the boolean "brcm,enable-l1ss" property:
> 
>   The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs --
>   requires the driver probe() to deliberately place the HW one of three
>   CLKREQ# modes:
> 
>   (a) CLKREQ# driven by the RC unconditionally
>   (b) CLKREQ# driven by the EP for ASPM L0s, L1
>   (c) Bidirectional CLKREQ#, as used for L1 Substates (L1SS).
> 
>   The HW+driver can tell the difference between downstream devices that
>   need (a) and (b), but does not know when to configure (c).  All devices
>   should work fine when the driver chooses (a) or (b), but (c) may be
>   desired to realize the extra power savings that L1SS offers.  So we
>   introduce the boolean "brcm,enable-l1ss" property to inform the driver
>   that (c) is desired.  Setting this property only makes sense when the
>   downstream device is L1SS-capable and the OS is configured to activate
>   this mode (e.g. policy==powersupersave).
> 
>   This property is already present in the Raspian version of Linux, but the
>   upstream driver implementation that follows adds more details and
>   discerns between (a) and (b).
> 
> Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
>  Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> index 7e15aae7d69e..8b61c2179608 100644
> --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> @@ -64,6 +64,15 @@ properties:
>  
>    aspm-no-l0s: true
>  
> +  brcm,enable-l1ss:
> +    description: Indicates that PCIe L1SS power savings
> +      are desired, the downstream device is L1SS-capable, and the
> +      OS has been configured to enable this mode.  For boards

What does this mean ? I don't think DT properties are supposed
to carry information related to how the OS is configured.

Again - it depends on what DT should be used for, I am not claiming to
have any authority on that, just asking.

Thanks,
Lorenzo

> +      using a mini-card connector, this mode may not meet the
> +      TCRLon maximum time of 400ns, as specified in 3.2.5.2.2
> +      of the PCI Express Mini CEM 2.0 specification.
> +    type: boolean
> +
>    brcm,scb-sizes:
>      description: u64 giving the 64bit PCIe memory
>        viewport size of a memory controller.  There may be up to
> -- 
> 2.17.1
> 

Re: [PATCH v6 1/5] dt-bindings: PCI: brcmstb: Add brcm,enable-l1ss property

[Jim Quinlan]

[-- Attachment #1: Type: text/plain, Size: 3510 bytes --]

On Mon, Aug 21, 2023 at 10:47 AM Lorenzo Pieralisi
<lpieralisi@kernel.org> wrote:
>
> On Fri, Jun 23, 2023 at 10:40:54AM -0400, Jim Quinlan wrote:
> > This commit adds the boolean "brcm,enable-l1ss" property:
> >
> >   The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs --
> >   requires the driver probe() to deliberately place the HW one of three
> >   CLKREQ# modes:
> >
> >   (a) CLKREQ# driven by the RC unconditionally
> >   (b) CLKREQ# driven by the EP for ASPM L0s, L1
> >   (c) Bidirectional CLKREQ#, as used for L1 Substates (L1SS).
> >
> >   The HW+driver can tell the difference between downstream devices that
> >   need (a) and (b), but does not know when to configure (c).  All devices
> >   should work fine when the driver chooses (a) or (b), but (c) may be
> >   desired to realize the extra power savings that L1SS offers.  So we
> >   introduce the boolean "brcm,enable-l1ss" property to inform the driver
> >   that (c) is desired.  Setting this property only makes sense when the
> >   downstream device is L1SS-capable and the OS is configured to activate
> >   this mode (e.g. policy==powersupersave).
> >
> >   This property is already present in the Raspian version of Linux, but the
> >   upstream driver implementation that follows adds more details and
> >   discerns between (a) and (b).
> >
> > Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
> > Reviewed-by: Rob Herring <robh@kernel.org>
> > ---
> >  Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 9 +++++++++
> >  1 file changed, 9 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > index 7e15aae7d69e..8b61c2179608 100644
> > --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > @@ -64,6 +64,15 @@ properties:
> >
> >    aspm-no-l0s: true
> >
> > +  brcm,enable-l1ss:
> > +    description: Indicates that PCIe L1SS power savings
> > +      are desired, the downstream device is L1SS-capable, and the
> > +      OS has been configured to enable this mode.  For boards
>
> What does this mean ? I don't think DT properties are supposed
> to carry information related to how the OS is configured.

The DT setting in question is unrelated to the statement "and the OS
has been configured to
enable this mode".

This is merely saying that even if you enable "brcm,l1ss-enable"
that you may not get L1SS power savings w/o setting
"CONFIG_PCIEASPM_POWER_SUPERSAVE=y".
I mentioned that exact term but a reviewer nakked it because
apparently DT descriptions should not be OS specific.

I am actually open for this to be a command-line option but I wanted to honor
what the Raspian OS folks have already done.  RaspianOS already has
"brcm,enable-l1ss"
set in their DTS files.

Regards,
Jim

> Again - it depends on what DT should be used for, I am not claiming to
> have any authority on that, just asking.
>
> Thanks,
> Lorenzo
>
> > +      using a mini-card connector, this mode may not meet the
> > +      TCRLon maximum time of 400ns, as specified in 3.2.5.2.2
> > +      of the PCI Express Mini CEM 2.0 specification.
> > +    type: boolean
> > +
> >    brcm,scb-sizes:
> >      description: u64 giving the 64bit PCIe memory
> >        viewport size of a memory controller.  There may be up to
> > --
> > 2.17.1
> >
>
>

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Re: [PATCH v6 1/5] dt-bindings: PCI: brcmstb: Add brcm,enable-l1ss property

[Lorenzo Pieralisi]

On Mon, Aug 21, 2023 at 11:25:11AM -0400, Jim Quinlan wrote:
> On Mon, Aug 21, 2023 at 10:47 AM Lorenzo Pieralisi
> <lpieralisi@kernel.org> wrote:
> >
> > On Fri, Jun 23, 2023 at 10:40:54AM -0400, Jim Quinlan wrote:
> > > This commit adds the boolean "brcm,enable-l1ss" property:
> > >
> > >   The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs --
> > >   requires the driver probe() to deliberately place the HW one of three
> > >   CLKREQ# modes:
> > >
> > >   (a) CLKREQ# driven by the RC unconditionally
> > >   (b) CLKREQ# driven by the EP for ASPM L0s, L1
> > >   (c) Bidirectional CLKREQ#, as used for L1 Substates (L1SS).
> > >
> > >   The HW+driver can tell the difference between downstream devices that
> > >   need (a) and (b), but does not know when to configure (c).  All devices
> > >   should work fine when the driver chooses (a) or (b), but (c) may be
> > >   desired to realize the extra power savings that L1SS offers.  So we
> > >   introduce the boolean "brcm,enable-l1ss" property to inform the driver
> > >   that (c) is desired.  Setting this property only makes sense when the
> > >   downstream device is L1SS-capable and the OS is configured to activate
> > >   this mode (e.g. policy==powersupersave).
> > >
> > >   This property is already present in the Raspian version of Linux, but the
> > >   upstream driver implementation that follows adds more details and
> > >   discerns between (a) and (b).
> > >
> > > Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
> > > Reviewed-by: Rob Herring <robh@kernel.org>
> > > ---
> > >  Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 9 +++++++++
> > >  1 file changed, 9 insertions(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > index 7e15aae7d69e..8b61c2179608 100644
> > > --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > @@ -64,6 +64,15 @@ properties:
> > >
> > >    aspm-no-l0s: true
> > >
> > > +  brcm,enable-l1ss:
> > > +    description: Indicates that PCIe L1SS power savings
> > > +      are desired, the downstream device is L1SS-capable, and the
> > > +      OS has been configured to enable this mode.  For boards
> >
> > What does this mean ? I don't think DT properties are supposed
> > to carry information related to how the OS is configured.
> 
> The DT setting in question is unrelated to the statement "and the OS
> has been configured to
> enable this mode".
> 
> This is merely saying that even if you enable "brcm,l1ss-enable"
> that you may not get L1SS power savings w/o setting
> "CONFIG_PCIEASPM_POWER_SUPERSAVE=y".
> I mentioned that exact term but a reviewer nakked it because
> apparently DT descriptions should not be OS specific.
> 
> I am actually open for this to be a command-line option but I wanted to honor
> what the Raspian OS folks have already done.  RaspianOS already has
> "brcm,enable-l1ss"
> set in their DTS files.

This is about the mainline kernel, I don't have any visibility into
downstream kernels (where that property management was added without DT
and PCI maintainers supervision).

Raspian OS folks' choice is theirs but it can't and it shouldn't override
the mainline review process even though I understand the position you
are in.

Thanks,
Lorenzo

> 
> Regards,
> Jim
> 
> > Again - it depends on what DT should be used for, I am not claiming to
> > have any authority on that, just asking.
> >
> > Thanks,
> > Lorenzo
> >
> > > +      using a mini-card connector, this mode may not meet the
> > > +      TCRLon maximum time of 400ns, as specified in 3.2.5.2.2
> > > +      of the PCI Express Mini CEM 2.0 specification.
> > > +    type: boolean
> > > +
> > >    brcm,scb-sizes:
> > >      description: u64 giving the 64bit PCIe memory
> > >        viewport size of a memory controller.  There may be up to
> > > --
> > > 2.17.1
> > >
> >
> >

Re: [PATCH v6 1/5] dt-bindings: PCI: brcmstb: Add brcm,enable-l1ss property

[Jim Quinlan]

[-- Attachment #1: Type: text/plain, Size: 5354 bytes --]

On Mon, Aug 21, 2023 at 11:41 AM Lorenzo Pieralisi
<lpieralisi@kernel.org> wrote:
>
> On Mon, Aug 21, 2023 at 11:25:11AM -0400, Jim Quinlan wrote:
> > On Mon, Aug 21, 2023 at 10:47 AM Lorenzo Pieralisi
> > <lpieralisi@kernel.org> wrote:
> > >
> > > On Fri, Jun 23, 2023 at 10:40:54AM -0400, Jim Quinlan wrote:
> > > > This commit adds the boolean "brcm,enable-l1ss" property:
> > > >
> > > >   The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs --
> > > >   requires the driver probe() to deliberately place the HW one of three
> > > >   CLKREQ# modes:
> > > >
> > > >   (a) CLKREQ# driven by the RC unconditionally
> > > >   (b) CLKREQ# driven by the EP for ASPM L0s, L1
> > > >   (c) Bidirectional CLKREQ#, as used for L1 Substates (L1SS).
> > > >
> > > >   The HW+driver can tell the difference between downstream devices that
> > > >   need (a) and (b), but does not know when to configure (c).  All devices
> > > >   should work fine when the driver chooses (a) or (b), but (c) may be
> > > >   desired to realize the extra power savings that L1SS offers.  So we
> > > >   introduce the boolean "brcm,enable-l1ss" property to inform the driver
> > > >   that (c) is desired.  Setting this property only makes sense when the
> > > >   downstream device is L1SS-capable and the OS is configured to activate
> > > >   this mode (e.g. policy==powersupersave).
> > > >
> > > >   This property is already present in the Raspian version of Linux, but the
> > > >   upstream driver implementation that follows adds more details and
> > > >   discerns between (a) and (b).
> > > >
> > > > Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
> > > > Reviewed-by: Rob Herring <robh@kernel.org>
> > > > ---
> > > >  Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 9 +++++++++
> > > >  1 file changed, 9 insertions(+)
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > index 7e15aae7d69e..8b61c2179608 100644
> > > > --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > @@ -64,6 +64,15 @@ properties:
> > > >
> > > >    aspm-no-l0s: true
> > > >
> > > > +  brcm,enable-l1ss:
> > > > +    description: Indicates that PCIe L1SS power savings
> > > > +      are desired, the downstream device is L1SS-capable, and the
> > > > +      OS has been configured to enable this mode.  For boards
> > >
> > > What does this mean ? I don't think DT properties are supposed
> > > to carry information related to how the OS is configured.
> >
> > The DT setting in question is unrelated to the statement "and the OS
> > has been configured to
> > enable this mode".
> >
> > This is merely saying that even if you enable "brcm,l1ss-enable"
> > that you may not get L1SS power savings w/o setting
> > "CONFIG_PCIEASPM_POWER_SUPERSAVE=y".
> > I mentioned that exact term but a reviewer nakked it because
> > apparently DT descriptions should not be OS specific.
> >
> > I am actually open for this to be a command-line option but I wanted to honor
> > what the Raspian OS folks have already done.  RaspianOS already has
> > "brcm,enable-l1ss"
> > set in their DTS files.
>
> This is about the mainline kernel, I don't have any visibility into
> downstream kernels (where that property management was added without DT
> and PCI maintainers supervision).
>
> Raspian OS folks' choice is theirs but it can't and it shouldn't override
> the mainline review process even though I understand the position you
> are in.

Understood, but using the command line has its warts as well; I now recall the
discussion Bjorn and I  had regarding this option.  I'm pretty sure
that upstreaam will not allow the following
possible command line kernel params:

    brcm,enable-l1ss
    pci=brcm,entable-l1ss

Bjorn suggested using the  documented but (IMO) obscure  and  rarely
used  format

    pci=[<domain>:]<bus>:<dev>.<func>[/<dev>.<func>]*pci:<vendor>:<device>[:<subvendor>:<subdevice>]

but this is just going in the wrong direction; here's why.  Using the
above iformat s completely dependent on the
PCI "linux-domaiin"  property,  a non-HW related DT property I  might
add.  Since "linux-domain" is already
a valid and well-used  DT property, and the value of  the above
command line format is dependent
on the value of the "linux-domain", why not be consistent and let
"brcm,enable-l1ss" be a Broadcom specific property?

Regards,
Jim Quinlan
Broadcom STB/CM


>
> Thanks,
> Lorenzo
>
> >
> > Regards,
> > Jim
> >
> > > Again - it depends on what DT should be used for, I am not claiming to
> > > have any authority on that, just asking.
> > >
> > > Thanks,
> > > Lorenzo
> > >
> > > > +      using a mini-card connector, this mode may not meet the
> > > > +      TCRLon maximum time of 400ns, as specified in 3.2.5.2.2
> > > > +      of the PCI Express Mini CEM 2.0 specification.
> > > > +    type: boolean
> > > > +
> > > >    brcm,scb-sizes:
> > > >      description: u64 giving the 64bit PCIe memory
> > > >        viewport size of a memory controller.  There may be up to
> > > > --
> > > > 2.17.1
> > > >
> > >
> > >
>
>

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Re: [PATCH v6 1/5] dt-bindings: PCI: brcmstb: Add brcm,enable-l1ss property

[Lorenzo Pieralisi]

On Mon, Aug 21, 2023 at 12:01:50PM -0400, Jim Quinlan wrote:
> On Mon, Aug 21, 2023 at 11:41 AM Lorenzo Pieralisi
> <lpieralisi@kernel.org> wrote:
> >
> > On Mon, Aug 21, 2023 at 11:25:11AM -0400, Jim Quinlan wrote:
> > > On Mon, Aug 21, 2023 at 10:47 AM Lorenzo Pieralisi
> > > <lpieralisi@kernel.org> wrote:
> > > >
> > > > On Fri, Jun 23, 2023 at 10:40:54AM -0400, Jim Quinlan wrote:
> > > > > This commit adds the boolean "brcm,enable-l1ss" property:
> > > > >
> > > > >   The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs --
> > > > >   requires the driver probe() to deliberately place the HW one of three
> > > > >   CLKREQ# modes:
> > > > >
> > > > >   (a) CLKREQ# driven by the RC unconditionally
> > > > >   (b) CLKREQ# driven by the EP for ASPM L0s, L1
> > > > >   (c) Bidirectional CLKREQ#, as used for L1 Substates (L1SS).
> > > > >
> > > > >   The HW+driver can tell the difference between downstream devices that
> > > > >   need (a) and (b), but does not know when to configure (c).  All devices
> > > > >   should work fine when the driver chooses (a) or (b), but (c) may be
> > > > >   desired to realize the extra power savings that L1SS offers.  So we
> > > > >   introduce the boolean "brcm,enable-l1ss" property to inform the driver
> > > > >   that (c) is desired.  Setting this property only makes sense when the
> > > > >   downstream device is L1SS-capable and the OS is configured to activate
> > > > >   this mode (e.g. policy==powersupersave).
> > > > >
> > > > >   This property is already present in the Raspian version of Linux, but the
> > > > >   upstream driver implementation that follows adds more details and
> > > > >   discerns between (a) and (b).
> > > > >
> > > > > Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
> > > > > Reviewed-by: Rob Herring <robh@kernel.org>
> > > > > ---
> > > > >  Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 9 +++++++++
> > > > >  1 file changed, 9 insertions(+)
> > > > >
> > > > > diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > index 7e15aae7d69e..8b61c2179608 100644
> > > > > --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > @@ -64,6 +64,15 @@ properties:
> > > > >
> > > > >    aspm-no-l0s: true
> > > > >
> > > > > +  brcm,enable-l1ss:
> > > > > +    description: Indicates that PCIe L1SS power savings
> > > > > +      are desired, the downstream device is L1SS-capable, and the
> > > > > +      OS has been configured to enable this mode.  For boards
> > > >
> > > > What does this mean ? I don't think DT properties are supposed
> > > > to carry information related to how the OS is configured.
> > >
> > > The DT setting in question is unrelated to the statement "and the OS
> > > has been configured to
> > > enable this mode".
> > >
> > > This is merely saying that even if you enable "brcm,l1ss-enable"
> > > that you may not get L1SS power savings w/o setting
> > > "CONFIG_PCIEASPM_POWER_SUPERSAVE=y".
> > > I mentioned that exact term but a reviewer nakked it because
> > > apparently DT descriptions should not be OS specific.
> > >
> > > I am actually open for this to be a command-line option but I wanted to honor
> > > what the Raspian OS folks have already done.  RaspianOS already has
> > > "brcm,enable-l1ss"
> > > set in their DTS files.
> >
> > This is about the mainline kernel, I don't have any visibility into
> > downstream kernels (where that property management was added without DT
> > and PCI maintainers supervision).
> >
> > Raspian OS folks' choice is theirs but it can't and it shouldn't override
> > the mainline review process even though I understand the position you
> > are in.
> 
> Understood, but using the command line has its warts as well; I now recall the
> discussion Bjorn and I  had regarding this option.  I'm pretty sure
> that upstreaam will not allow the following
> possible command line kernel params:
> 
>     brcm,enable-l1ss
>     pci=brcm,entable-l1ss
> 
> Bjorn suggested using the  documented but (IMO) obscure  and  rarely
> used  format
> 
>     pci=[<domain>:]<bus>:<dev>.<func>[/<dev>.<func>]*pci:<vendor>:<device>[:<subvendor>:<subdevice>]
> 
> but this is just going in the wrong direction; here's why.  Using the
> above iformat s completely dependent on the
> PCI "linux-domaiin"  property,  a non-HW related DT property I  might
> add.  Since "linux-domain" is already
> a valid and well-used  DT property, and the value of  the above
> command line format is dependent
> on the value of the "linux-domain", why not be consistent and let
> "brcm,enable-l1ss" be a Broadcom specific property?

I am just asking to add a module_param to the host controller driver.

Anyway - time is running out for v6.6, I need Rob's feedback, if I don't
hear from him today I will merge the last three patches and postpone the
discussion.

Thanks,
Lorenzo

> 
> Regards,
> Jim Quinlan
> Broadcom STB/CM
> 
> 
> >
> > Thanks,
> > Lorenzo
> >
> > >
> > > Regards,
> > > Jim
> > >
> > > > Again - it depends on what DT should be used for, I am not claiming to
> > > > have any authority on that, just asking.
> > > >
> > > > Thanks,
> > > > Lorenzo
> > > >
> > > > > +      using a mini-card connector, this mode may not meet the
> > > > > +      TCRLon maximum time of 400ns, as specified in 3.2.5.2.2
> > > > > +      of the PCI Express Mini CEM 2.0 specification.
> > > > > +    type: boolean
> > > > > +
> > > > >    brcm,scb-sizes:
> > > > >      description: u64 giving the 64bit PCIe memory
> > > > >        viewport size of a memory controller.  There may be up to
> > > > > --
> > > > > 2.17.1
> > > > >
> > > >
> > > >
> >
> >

Re: [PATCH v6 1/5] dt-bindings: PCI: brcmstb: Add brcm,enable-l1ss property

[Bjorn Helgaas]

On Wed, Aug 23, 2023 at 09:30:48AM +0200, Lorenzo Pieralisi wrote:
> On Mon, Aug 21, 2023 at 12:01:50PM -0400, Jim Quinlan wrote:
> > On Mon, Aug 21, 2023 at 11:41 AM Lorenzo Pieralisi
> > <lpieralisi@kernel.org> wrote:
> > > On Mon, Aug 21, 2023 at 11:25:11AM -0400, Jim Quinlan wrote:
> > > > On Mon, Aug 21, 2023 at 10:47 AM Lorenzo Pieralisi
> > > > <lpieralisi@kernel.org> wrote:
> > > > > On Fri, Jun 23, 2023 at 10:40:54AM -0400, Jim Quinlan wrote:
> > > > > > This commit adds the boolean "brcm,enable-l1ss" property:
> > > > > >
> > > > > >   The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs --
> > > > > >   requires the driver probe() to deliberately place the HW one of three
> > > > > >   CLKREQ# modes:
> > > > > >
> > > > > >   (a) CLKREQ# driven by the RC unconditionally
> > > > > >   (b) CLKREQ# driven by the EP for ASPM L0s, L1
> > > > > >   (c) Bidirectional CLKREQ#, as used for L1 Substates (L1SS).
> > > > > >
> > > > > >   The HW+driver can tell the difference between downstream devices that
> > > > > >   need (a) and (b), but does not know when to configure (c).  All devices
> > > > > >   should work fine when the driver chooses (a) or (b), but (c) may be
> > > > > >   desired to realize the extra power savings that L1SS offers.  So we
> > > > > >   introduce the boolean "brcm,enable-l1ss" property to inform the driver
> > > > > >   that (c) is desired.  Setting this property only makes sense when the
> > > > > >   downstream device is L1SS-capable and the OS is configured to activate
> > > > > >   this mode (e.g. policy==powersupersave).
> > > > > >
> > > > > >   This property is already present in the Raspian version of Linux, but the
> > > > > >   upstream driver implementation that follows adds more details and
> > > > > >   discerns between (a) and (b).
> > > > > >
> > > > > > Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
> > > > > > Reviewed-by: Rob Herring <robh@kernel.org>
> > > > > > ---
> > > > > >  Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 9 +++++++++
> > > > > >  1 file changed, 9 insertions(+)
> > > > > >
> > > > > > diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > > index 7e15aae7d69e..8b61c2179608 100644
> > > > > > --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > > +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > > @@ -64,6 +64,15 @@ properties:
> > > > > >
> > > > > >    aspm-no-l0s: true
> > > > > >
> > > > > > +  brcm,enable-l1ss:
> > > > > > +    description: Indicates that PCIe L1SS power savings
> > > > > > +      are desired, the downstream device is L1SS-capable, and the
> > > > > > +      OS has been configured to enable this mode.  For boards
> > > > >
> > > > > What does this mean ? I don't think DT properties are supposed
> > > > > to carry information related to how the OS is configured.
> > > >
> > > > The DT setting in question is unrelated to the statement "and the OS
> > > > has been configured to
> > > > enable this mode".
> > > >
> > > > This is merely saying that even if you enable "brcm,l1ss-enable"
> > > > that you may not get L1SS power savings w/o setting
> > > > "CONFIG_PCIEASPM_POWER_SUPERSAVE=y".
> > > > I mentioned that exact term but a reviewer nakked it because
> > > > apparently DT descriptions should not be OS specific.
> > > >
> > > > I am actually open for this to be a command-line option but I wanted to honor
> > > > what the Raspian OS folks have already done.  RaspianOS already has
> > > > "brcm,enable-l1ss"
> > > > set in their DTS files.
> > >
> > > This is about the mainline kernel, I don't have any visibility into
> > > downstream kernels (where that property management was added without DT
> > > and PCI maintainers supervision).
> > >
> > > Raspian OS folks' choice is theirs but it can't and it shouldn't override
> > > the mainline review process even though I understand the position you
> > > are in.
> > 
> > Understood, but using the command line has its warts as well; I now recall the
> > discussion Bjorn and I  had regarding this option.  I'm pretty sure
> > that upstreaam will not allow the following
> > possible command line kernel params:
> > 
> >     brcm,enable-l1ss
> >     pci=brcm,entable-l1ss
> > 
> > Bjorn suggested using the  documented but (IMO) obscure  and  rarely
> > used  format
> > 
> >     pci=[<domain>:]<bus>:<dev>.<func>[/<dev>.<func>]*pci:<vendor>:<device>[:<subvendor>:<subdevice>]
> > 
> > but this is just going in the wrong direction; here's why.  Using the
> > above iformat s completely dependent on the
> > PCI "linux-domaiin"  property,  a non-HW related DT property I  might
> > add.  Since "linux-domain" is already
> > a valid and well-used  DT property, and the value of  the above
> > command line format is dependent
> > on the value of the "linux-domain", why not be consistent and let
> > "brcm,enable-l1ss" be a Broadcom specific property?
> 
> I am just asking to add a module_param to the host controller driver.

A module_param sounds possible to me.  IIRC the bidirectional CLKREQ#
(config (c)) has been tested and there are no known problems even if
the OS doesn't enable L1SS.  The only issue (again, IIRC) is that the
hardware engineer has unspecified reservations about it.

Is there any room to make (c) the default and have a module_param to
*disable* the L1SS support?  I think the driver knows enough to then
select (a) or (b) by itself.

Bjorn

Re: [PATCH v6 1/5] dt-bindings: PCI: brcmstb: Add brcm,enable-l1ss property

[Rob Herring]

On Wed, Aug 23, 2023 at 2:30 AM Lorenzo Pieralisi <lpieralisi@kernel.org> wrote:
>
> On Mon, Aug 21, 2023 at 12:01:50PM -0400, Jim Quinlan wrote:
> > On Mon, Aug 21, 2023 at 11:41 AM Lorenzo Pieralisi
> > <lpieralisi@kernel.org> wrote:
> > >
> > > On Mon, Aug 21, 2023 at 11:25:11AM -0400, Jim Quinlan wrote:
> > > > On Mon, Aug 21, 2023 at 10:47 AM Lorenzo Pieralisi
> > > > <lpieralisi@kernel.org> wrote:
> > > > >
> > > > > On Fri, Jun 23, 2023 at 10:40:54AM -0400, Jim Quinlan wrote:
> > > > > > This commit adds the boolean "brcm,enable-l1ss" property:
> > > > > >
> > > > > >   The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs --
> > > > > >   requires the driver probe() to deliberately place the HW one of three
> > > > > >   CLKREQ# modes:
> > > > > >
> > > > > >   (a) CLKREQ# driven by the RC unconditionally
> > > > > >   (b) CLKREQ# driven by the EP for ASPM L0s, L1
> > > > > >   (c) Bidirectional CLKREQ#, as used for L1 Substates (L1SS).
> > > > > >
> > > > > >   The HW+driver can tell the difference between downstream devices that
> > > > > >   need (a) and (b), but does not know when to configure (c).  All devices
> > > > > >   should work fine when the driver chooses (a) or (b), but (c) may be
> > > > > >   desired to realize the extra power savings that L1SS offers.  So we
> > > > > >   introduce the boolean "brcm,enable-l1ss" property to inform the driver
> > > > > >   that (c) is desired.  Setting this property only makes sense when the
> > > > > >   downstream device is L1SS-capable and the OS is configured to activate
> > > > > >   this mode (e.g. policy==powersupersave).
> > > > > >
> > > > > >   This property is already present in the Raspian version of Linux, but the
> > > > > >   upstream driver implementation that follows adds more details and
> > > > > >   discerns between (a) and (b).
> > > > > >
> > > > > > Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
> > > > > > Reviewed-by: Rob Herring <robh@kernel.org>
> > > > > > ---
> > > > > >  Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 9 +++++++++
> > > > > >  1 file changed, 9 insertions(+)
> > > > > >
> > > > > > diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > > index 7e15aae7d69e..8b61c2179608 100644
> > > > > > --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > > +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > > @@ -64,6 +64,15 @@ properties:
> > > > > >
> > > > > >    aspm-no-l0s: true
> > > > > >
> > > > > > +  brcm,enable-l1ss:
> > > > > > +    description: Indicates that PCIe L1SS power savings
> > > > > > +      are desired, the downstream device is L1SS-capable, and the
> > > > > > +      OS has been configured to enable this mode.  For boards
> > > > >
> > > > > What does this mean ? I don't think DT properties are supposed
> > > > > to carry information related to how the OS is configured.
> > > >
> > > > The DT setting in question is unrelated to the statement "and the OS
> > > > has been configured to
> > > > enable this mode".
> > > >
> > > > This is merely saying that even if you enable "brcm,l1ss-enable"
> > > > that you may not get L1SS power savings w/o setting
> > > > "CONFIG_PCIEASPM_POWER_SUPERSAVE=y".
> > > > I mentioned that exact term but a reviewer nakked it because
> > > > apparently DT descriptions should not be OS specific.

Yeah, probably the OS part should be dropped.

> > > >
> > > > I am actually open for this to be a command-line option but I wanted to honor
> > > > what the Raspian OS folks have already done.  RaspianOS already has
> > > > "brcm,enable-l1ss"
> > > > set in their DTS files.
> > >
> > > This is about the mainline kernel, I don't have any visibility into
> > > downstream kernels (where that property management was added without DT
> > > and PCI maintainers supervision).
> > >
> > > Raspian OS folks' choice is theirs but it can't and it shouldn't override
> > > the mainline review process even though I understand the position you
> > > are in.

Sure, but we shouldn't change things just to be different from
downstream. If we're only discussing the color of the shed, then no
point changing it.

> >
> > Understood, but using the command line has its warts as well; I now recall the
> > discussion Bjorn and I  had regarding this option.  I'm pretty sure
> > that upstreaam will not allow the following
> > possible command line kernel params:
> >
> >     brcm,enable-l1ss
> >     pci=brcm,entable-l1ss
> >
> > Bjorn suggested using the  documented but (IMO) obscure  and  rarely
> > used  format
> >
> >     pci=[<domain>:]<bus>:<dev>.<func>[/<dev>.<func>]*pci:<vendor>:<device>[:<subvendor>:<subdevice>]
> >
> > but this is just going in the wrong direction; here's why.  Using the
> > above iformat s completely dependent on the
> > PCI "linux-domaiin"  property,  a non-HW related DT property I  might
> > add.  Since "linux-domain" is already
> > a valid and well-used  DT property, and the value of  the above
> > command line format is dependent
> > on the value of the "linux-domain", why not be consistent and let
> > "brcm,enable-l1ss" be a Broadcom specific property?
>
> I am just asking to add a module_param to the host controller driver.

FWIW, gregkh pretty much always nacks new module parameters.

>
> Anyway - time is running out for v6.6, I need Rob's feedback, if I don't
> hear from him today I will merge the last three patches and postpone the
> discussion.

You've already got my reviewed-by. If you aren't happy with this, then
fine. I don't know enough about L1SS to comment further. Is it
normally always supported or discoverable? If so, then I'd think we'd
want it default enabled with a disable override flag. Maybe it should
be generic?

Rob

Re: [PATCH v6 1/5] dt-bindings: PCI: brcmstb: Add brcm,enable-l1ss property

[Jim Quinlan]

[-- Attachment #1: Type: text/plain, Size: 7905 bytes --]

On Wed, Aug 23, 2023 at 8:42 AM Bjorn Helgaas <helgaas@kernel.org> wrote:
>
> On Wed, Aug 23, 2023 at 09:30:48AM +0200, Lorenzo Pieralisi wrote:
> > On Mon, Aug 21, 2023 at 12:01:50PM -0400, Jim Quinlan wrote:
> > > On Mon, Aug 21, 2023 at 11:41 AM Lorenzo Pieralisi
> > > <lpieralisi@kernel.org> wrote:
> > > > On Mon, Aug 21, 2023 at 11:25:11AM -0400, Jim Quinlan wrote:
> > > > > On Mon, Aug 21, 2023 at 10:47 AM Lorenzo Pieralisi
> > > > > <lpieralisi@kernel.org> wrote:
> > > > > > On Fri, Jun 23, 2023 at 10:40:54AM -0400, Jim Quinlan wrote:
> > > > > > > This commit adds the boolean "brcm,enable-l1ss" property:
> > > > > > >
> > > > > > >   The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs --
> > > > > > >   requires the driver probe() to deliberately place the HW one of three
> > > > > > >   CLKREQ# modes:
> > > > > > >
> > > > > > >   (a) CLKREQ# driven by the RC unconditionally
> > > > > > >   (b) CLKREQ# driven by the EP for ASPM L0s, L1
> > > > > > >   (c) Bidirectional CLKREQ#, as used for L1 Substates (L1SS).
> > > > > > >
> > > > > > >   The HW+driver can tell the difference between downstream devices that
> > > > > > >   need (a) and (b), but does not know when to configure (c).  All devices
> > > > > > >   should work fine when the driver chooses (a) or (b), but (c) may be
> > > > > > >   desired to realize the extra power savings that L1SS offers.  So we
> > > > > > >   introduce the boolean "brcm,enable-l1ss" property to inform the driver
> > > > > > >   that (c) is desired.  Setting this property only makes sense when the
> > > > > > >   downstream device is L1SS-capable and the OS is configured to activate
> > > > > > >   this mode (e.g. policy==powersupersave).
> > > > > > >
> > > > > > >   This property is already present in the Raspian version of Linux, but the
> > > > > > >   upstream driver implementation that follows adds more details and
> > > > > > >   discerns between (a) and (b).
> > > > > > >
> > > > > > > Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
> > > > > > > Reviewed-by: Rob Herring <robh@kernel.org>
> > > > > > > ---
> > > > > > >  Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 9 +++++++++
> > > > > > >  1 file changed, 9 insertions(+)
> > > > > > >
> > > > > > > diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > > > index 7e15aae7d69e..8b61c2179608 100644
> > > > > > > --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > > > +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > > > @@ -64,6 +64,15 @@ properties:
> > > > > > >
> > > > > > >    aspm-no-l0s: true
> > > > > > >
> > > > > > > +  brcm,enable-l1ss:
> > > > > > > +    description: Indicates that PCIe L1SS power savings
> > > > > > > +      are desired, the downstream device is L1SS-capable, and the
> > > > > > > +      OS has been configured to enable this mode.  For boards
> > > > > >
> > > > > > What does this mean ? I don't think DT properties are supposed
> > > > > > to carry information related to how the OS is configured.
> > > > >
> > > > > The DT setting in question is unrelated to the statement "and the OS
> > > > > has been configured to
> > > > > enable this mode".
> > > > >
> > > > > This is merely saying that even if you enable "brcm,l1ss-enable"
> > > > > that you may not get L1SS power savings w/o setting
> > > > > "CONFIG_PCIEASPM_POWER_SUPERSAVE=y".
> > > > > I mentioned that exact term but a reviewer nakked it because
> > > > > apparently DT descriptions should not be OS specific.
> > > > >
> > > > > I am actually open for this to be a command-line option but I wanted to honor
> > > > > what the Raspian OS folks have already done.  RaspianOS already has
> > > > > "brcm,enable-l1ss"
> > > > > set in their DTS files.
> > > >
> > > > This is about the mainline kernel, I don't have any visibility into
> > > > downstream kernels (where that property management was added without DT
> > > > and PCI maintainers supervision).
> > > >
> > > > Raspian OS folks' choice is theirs but it can't and it shouldn't override
> > > > the mainline review process even though I understand the position you
> > > > are in.
> > >
> > > Understood, but using the command line has its warts as well; I now recall the
> > > discussion Bjorn and I  had regarding this option.  I'm pretty sure
> > > that upstreaam will not allow the following
> > > possible command line kernel params:
> > >
> > >     brcm,enable-l1ss
> > >     pci=brcm,entable-l1ss
> > >
> > > Bjorn suggested using the  documented but (IMO) obscure  and  rarely
> > > used  format
> > >
> > >     pci=[<domain>:]<bus>:<dev>.<func>[/<dev>.<func>]*pci:<vendor>:<device>[:<subvendor>:<subdevice>]
> > >
> > > but this is just going in the wrong direction; here's why.  Using the
> > > above iformat s completely dependent on the
> > > PCI "linux-domaiin"  property,  a non-HW related DT property I  might
> > > add.  Since "linux-domain" is already
> > > a valid and well-used  DT property, and the value of  the above
> > > command line format is dependent
> > > on the value of the "linux-domain", why not be consistent and let
> > > "brcm,enable-l1ss" be a Broadcom specific property?
> >
> > I am just asking to add a module_param to the host controller driver.

Adding a module_param, which would have a command line setting such as
"brcm_pcie.enable-l1ss=1"
is for the driver -- we need a per PCIe controller param, as each
controller may have a different setting.

Which brings us to the alternative, a command line param using
pci_dev_str_match() such as

      pci=brcm,enable-l1ss=1:0:0.0

Implementing this would require this AFAICT:

    (1) New file:  drivers/pci/controller/pcie-brcmstb.h
    (2) The "pci.c" file would have to include the above file which I
don't think is a good thing.

>
> A module_param sounds possible to me.  IIRC the bidirectional CLKREQ#
> (config (c)) has been tested and there are no known problems even if
> the OS doesn't enable L1SS.

Ah, I have an update on this.  I was able to communicate with the HW
designer and he explained
that when setting the PCIe core "l1ss bit"  one  loses the benefit  of
Clock Power  Management.  Actually,
let me quote his email so I do not distort his words:

   "If RC is placed in L1SS clkreq mode, may take advantage
    of L1SS power savings, L0s, and L1 power savings, but cannot
    employ Clock Power Management power savings.

    If the RC is placed in "clkreq" clkreq mode, it can only take
    advantage of L0s, L1 power savings, and Clock Power Management
    savings - only omitting L1SS power savings

    The issue is that the Clock Power Management and PM L1 Substates
    are incompatible. The original Clock Power Management feature
    requires the clock to turn on within Tclron=400ns from CLKREQ#
    deassertion, and we feel we need to continue to support products
    that were designed to this requirement. The CLKREQ# deassertion
    to clock turned on requirement with PM L1 Substates was relaxed
    with the addition of the Latency Tolerance Reporting (LTR)
    mechanism. We use the mode bit to distinguish the two modes of
    operation, but currently we aren't looking at whether the RC+EP
    both support the LTR mechanism to make the decision."

I'm not sure if this changes your mind one way or another.

Regards,
Jim Quinlan
Broadcom STB/CM





The only issue (again, IIRC) is that the
> hardware engineer has unspecified reservations about it.
>
> Is there any room to make (c) the default and have a module_param to
> *disable* the L1SS support?  I think the driver knows enough to then
> select (a) or (b) by itself.
>
> Bjorn

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Re: [PATCH v6 1/5] dt-bindings: PCI: brcmstb: Add brcm,enable-l1ss property

[Lorenzo Pieralisi]

On Wed, Aug 23, 2023 at 09:48:40AM -0500, Rob Herring wrote:
> On Wed, Aug 23, 2023 at 2:30 AM Lorenzo Pieralisi <lpieralisi@kernel.org> wrote:
> >
> > On Mon, Aug 21, 2023 at 12:01:50PM -0400, Jim Quinlan wrote:
> > > On Mon, Aug 21, 2023 at 11:41 AM Lorenzo Pieralisi
> > > <lpieralisi@kernel.org> wrote:
> > > >
> > > > On Mon, Aug 21, 2023 at 11:25:11AM -0400, Jim Quinlan wrote:
> > > > > On Mon, Aug 21, 2023 at 10:47 AM Lorenzo Pieralisi
> > > > > <lpieralisi@kernel.org> wrote:
> > > > > >
> > > > > > On Fri, Jun 23, 2023 at 10:40:54AM -0400, Jim Quinlan wrote:
> > > > > > > This commit adds the boolean "brcm,enable-l1ss" property:
> > > > > > >
> > > > > > >   The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs --
> > > > > > >   requires the driver probe() to deliberately place the HW one of three
> > > > > > >   CLKREQ# modes:
> > > > > > >
> > > > > > >   (a) CLKREQ# driven by the RC unconditionally
> > > > > > >   (b) CLKREQ# driven by the EP for ASPM L0s, L1
> > > > > > >   (c) Bidirectional CLKREQ#, as used for L1 Substates (L1SS).
> > > > > > >
> > > > > > >   The HW+driver can tell the difference between downstream devices that
> > > > > > >   need (a) and (b), but does not know when to configure (c).  All devices
> > > > > > >   should work fine when the driver chooses (a) or (b), but (c) may be
> > > > > > >   desired to realize the extra power savings that L1SS offers.  So we
> > > > > > >   introduce the boolean "brcm,enable-l1ss" property to inform the driver
> > > > > > >   that (c) is desired.  Setting this property only makes sense when the
> > > > > > >   downstream device is L1SS-capable and the OS is configured to activate
> > > > > > >   this mode (e.g. policy==powersupersave).
> > > > > > >
> > > > > > >   This property is already present in the Raspian version of Linux, but the
> > > > > > >   upstream driver implementation that follows adds more details and
> > > > > > >   discerns between (a) and (b).
> > > > > > >
> > > > > > > Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
> > > > > > > Reviewed-by: Rob Herring <robh@kernel.org>
> > > > > > > ---
> > > > > > >  Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 9 +++++++++
> > > > > > >  1 file changed, 9 insertions(+)
> > > > > > >
> > > > > > > diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > > > index 7e15aae7d69e..8b61c2179608 100644
> > > > > > > --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > > > +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > > > @@ -64,6 +64,15 @@ properties:
> > > > > > >
> > > > > > >    aspm-no-l0s: true
> > > > > > >
> > > > > > > +  brcm,enable-l1ss:
> > > > > > > +    description: Indicates that PCIe L1SS power savings
> > > > > > > +      are desired, the downstream device is L1SS-capable, and the
> > > > > > > +      OS has been configured to enable this mode.  For boards
> > > > > >
> > > > > > What does this mean ? I don't think DT properties are supposed
> > > > > > to carry information related to how the OS is configured.
> > > > >
> > > > > The DT setting in question is unrelated to the statement "and the OS
> > > > > has been configured to
> > > > > enable this mode".
> > > > >
> > > > > This is merely saying that even if you enable "brcm,l1ss-enable"
> > > > > that you may not get L1SS power savings w/o setting
> > > > > "CONFIG_PCIEASPM_POWER_SUPERSAVE=y".
> > > > > I mentioned that exact term but a reviewer nakked it because
> > > > > apparently DT descriptions should not be OS specific.
> 
> Yeah, probably the OS part should be dropped.

I will drop it - if you don't mind.

> > > > > I am actually open for this to be a command-line option but I wanted to honor
> > > > > what the Raspian OS folks have already done.  RaspianOS already has
> > > > > "brcm,enable-l1ss"
> > > > > set in their DTS files.
> > > >
> > > > This is about the mainline kernel, I don't have any visibility into
> > > > downstream kernels (where that property management was added without DT
> > > > and PCI maintainers supervision).
> > > >
> > > > Raspian OS folks' choice is theirs but it can't and it shouldn't override
> > > > the mainline review process even though I understand the position you
> > > > are in.
> 
> Sure, but we shouldn't change things just to be different from
> downstream. If we're only discussing the color of the shed, then no
> point changing it.

Sure, no problem.

> > > Understood, but using the command line has its warts as well; I now recall the
> > > discussion Bjorn and I  had regarding this option.  I'm pretty sure
> > > that upstreaam will not allow the following
> > > possible command line kernel params:
> > >
> > >     brcm,enable-l1ss
> > >     pci=brcm,entable-l1ss
> > >
> > > Bjorn suggested using the  documented but (IMO) obscure  and  rarely
> > > used  format
> > >
> > >     pci=[<domain>:]<bus>:<dev>.<func>[/<dev>.<func>]*pci:<vendor>:<device>[:<subvendor>:<subdevice>]
> > >
> > > but this is just going in the wrong direction; here's why.  Using the
> > > above iformat s completely dependent on the
> > > PCI "linux-domaiin"  property,  a non-HW related DT property I  might
> > > add.  Since "linux-domain" is already
> > > a valid and well-used  DT property, and the value of  the above
> > > command line format is dependent
> > > on the value of the "linux-domain", why not be consistent and let
> > > "brcm,enable-l1ss" be a Broadcom specific property?
> >
> > I am just asking to add a module_param to the host controller driver.
> 
> FWIW, gregkh pretty much always nacks new module parameters.

Fine by me.

> > Anyway - time is running out for v6.6, I need Rob's feedback, if I don't
> > hear from him today I will merge the last three patches and postpone the
> > discussion.
> 
> You've already got my reviewed-by. If you aren't happy with this, then
> fine. I don't know enough about L1SS to comment further. Is it
> normally always supported or discoverable? If so, then I'd think we'd
> want it default enabled with a disable override flag. Maybe it should
> be generic?

It is not that I am not happy with it - we asked questions to understand
what this property was for, I think that's normal.

I will merge this series as-is.

Lorenzo

Re: [PATCH v6 1/5] dt-bindings: PCI: brcmstb: Add brcm,enable-l1ss property

[Manivannan Sadhasivam]

On Wed, Aug 23, 2023 at 06:29:08PM +0200, Lorenzo Pieralisi wrote:
> On Wed, Aug 23, 2023 at 09:48:40AM -0500, Rob Herring wrote:
> > On Wed, Aug 23, 2023 at 2:30 AM Lorenzo Pieralisi <lpieralisi@kernel.org> wrote:
> > >
> > > On Mon, Aug 21, 2023 at 12:01:50PM -0400, Jim Quinlan wrote:
> > > > On Mon, Aug 21, 2023 at 11:41 AM Lorenzo Pieralisi
> > > > <lpieralisi@kernel.org> wrote:
> > > > >
> > > > > On Mon, Aug 21, 2023 at 11:25:11AM -0400, Jim Quinlan wrote:
> > > > > > On Mon, Aug 21, 2023 at 10:47 AM Lorenzo Pieralisi
> > > > > > <lpieralisi@kernel.org> wrote:
> > > > > > >
> > > > > > > On Fri, Jun 23, 2023 at 10:40:54AM -0400, Jim Quinlan wrote:
> > > > > > > > This commit adds the boolean "brcm,enable-l1ss" property:
> > > > > > > >
> > > > > > > >   The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs --
> > > > > > > >   requires the driver probe() to deliberately place the HW one of three
> > > > > > > >   CLKREQ# modes:
> > > > > > > >
> > > > > > > >   (a) CLKREQ# driven by the RC unconditionally
> > > > > > > >   (b) CLKREQ# driven by the EP for ASPM L0s, L1
> > > > > > > >   (c) Bidirectional CLKREQ#, as used for L1 Substates (L1SS).
> > > > > > > >
> > > > > > > >   The HW+driver can tell the difference between downstream devices that
> > > > > > > >   need (a) and (b), but does not know when to configure (c).  All devices
> > > > > > > >   should work fine when the driver chooses (a) or (b), but (c) may be
> > > > > > > >   desired to realize the extra power savings that L1SS offers.  So we
> > > > > > > >   introduce the boolean "brcm,enable-l1ss" property to inform the driver
> > > > > > > >   that (c) is desired.  Setting this property only makes sense when the
> > > > > > > >   downstream device is L1SS-capable and the OS is configured to activate
> > > > > > > >   this mode (e.g. policy==powersupersave).
> > > > > > > >
> > > > > > > >   This property is already present in the Raspian version of Linux, but the
> > > > > > > >   upstream driver implementation that follows adds more details and
> > > > > > > >   discerns between (a) and (b).
> > > > > > > >
> > > > > > > > Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
> > > > > > > > Reviewed-by: Rob Herring <robh@kernel.org>
> > > > > > > > ---
> > > > > > > >  Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 9 +++++++++
> > > > > > > >  1 file changed, 9 insertions(+)
> > > > > > > >
> > > > > > > > diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > > > > index 7e15aae7d69e..8b61c2179608 100644
> > > > > > > > --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > > > > +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > > > > @@ -64,6 +64,15 @@ properties:
> > > > > > > >
> > > > > > > >    aspm-no-l0s: true
> > > > > > > >
> > > > > > > > +  brcm,enable-l1ss:
> > > > > > > > +    description: Indicates that PCIe L1SS power savings
> > > > > > > > +      are desired, the downstream device is L1SS-capable, and the
> > > > > > > > +      OS has been configured to enable this mode.  For boards
> > > > > > >
> > > > > > > What does this mean ? I don't think DT properties are supposed
> > > > > > > to carry information related to how the OS is configured.
> > > > > >
> > > > > > The DT setting in question is unrelated to the statement "and the OS
> > > > > > has been configured to
> > > > > > enable this mode".
> > > > > >
> > > > > > This is merely saying that even if you enable "brcm,l1ss-enable"
> > > > > > that you may not get L1SS power savings w/o setting
> > > > > > "CONFIG_PCIEASPM_POWER_SUPERSAVE=y".
> > > > > > I mentioned that exact term but a reviewer nakked it because
> > > > > > apparently DT descriptions should not be OS specific.
> > 
> > Yeah, probably the OS part should be dropped.
> 
> I will drop it - if you don't mind.
> 
> > > > > > I am actually open for this to be a command-line option but I wanted to honor
> > > > > > what the Raspian OS folks have already done.  RaspianOS already has
> > > > > > "brcm,enable-l1ss"
> > > > > > set in their DTS files.
> > > > >
> > > > > This is about the mainline kernel, I don't have any visibility into
> > > > > downstream kernels (where that property management was added without DT
> > > > > and PCI maintainers supervision).
> > > > >
> > > > > Raspian OS folks' choice is theirs but it can't and it shouldn't override
> > > > > the mainline review process even though I understand the position you
> > > > > are in.
> > 
> > Sure, but we shouldn't change things just to be different from
> > downstream. If we're only discussing the color of the shed, then no
> > point changing it.
> 
> Sure, no problem.
> 
> > > > Understood, but using the command line has its warts as well; I now recall the
> > > > discussion Bjorn and I  had regarding this option.  I'm pretty sure
> > > > that upstreaam will not allow the following
> > > > possible command line kernel params:
> > > >
> > > >     brcm,enable-l1ss
> > > >     pci=brcm,entable-l1ss
> > > >
> > > > Bjorn suggested using the  documented but (IMO) obscure  and  rarely
> > > > used  format
> > > >
> > > >     pci=[<domain>:]<bus>:<dev>.<func>[/<dev>.<func>]*pci:<vendor>:<device>[:<subvendor>:<subdevice>]
> > > >
> > > > but this is just going in the wrong direction; here's why.  Using the
> > > > above iformat s completely dependent on the
> > > > PCI "linux-domaiin"  property,  a non-HW related DT property I  might
> > > > add.  Since "linux-domain" is already
> > > > a valid and well-used  DT property, and the value of  the above
> > > > command line format is dependent
> > > > on the value of the "linux-domain", why not be consistent and let
> > > > "brcm,enable-l1ss" be a Broadcom specific property?
> > >
> > > I am just asking to add a module_param to the host controller driver.
> > 
> > FWIW, gregkh pretty much always nacks new module parameters.
> 
> Fine by me.
> 
> > > Anyway - time is running out for v6.6, I need Rob's feedback, if I don't
> > > hear from him today I will merge the last three patches and postpone the
> > > discussion.
> > 
> > You've already got my reviewed-by. If you aren't happy with this, then
> > fine. I don't know enough about L1SS to comment further. Is it
> > normally always supported or discoverable? If so, then I'd think we'd
> > want it default enabled with a disable override flag. Maybe it should
> > be generic?
> 
> It is not that I am not happy with it - we asked questions to understand
> what this property was for, I think that's normal.
> 
> I will merge this series as-is.
> 

There is a discussion ongoing here: https://lore.kernel.org/linux-pci/20230823181650.GL3737@thinkpad/T/#u

Can you please hold on to merging this series until we've reached a conclusion?

- Mani

> Lorenzo

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH v6 1/5] dt-bindings: PCI: brcmstb: Add brcm,enable-l1ss property

[Jim Quinlan]

[-- Attachment #1: Type: text/plain, Size: 8464 bytes --]

On Wed, Aug 23, 2023 at 2:26 PM Manivannan Sadhasivam
<manivannan.sadhasivam@linaro.org> wrote:
>
> On Wed, Aug 23, 2023 at 06:29:08PM +0200, Lorenzo Pieralisi wrote:
> > On Wed, Aug 23, 2023 at 09:48:40AM -0500, Rob Herring wrote:
> > > On Wed, Aug 23, 2023 at 2:30 AM Lorenzo Pieralisi <lpieralisi@kernel.org> wrote:
> > > >
> > > > On Mon, Aug 21, 2023 at 12:01:50PM -0400, Jim Quinlan wrote:
> > > > > On Mon, Aug 21, 2023 at 11:41 AM Lorenzo Pieralisi
> > > > > <lpieralisi@kernel.org> wrote:
> > > > > >
> > > > > > On Mon, Aug 21, 2023 at 11:25:11AM -0400, Jim Quinlan wrote:
> > > > > > > On Mon, Aug 21, 2023 at 10:47 AM Lorenzo Pieralisi
> > > > > > > <lpieralisi@kernel.org> wrote:
> > > > > > > >
> > > > > > > > On Fri, Jun 23, 2023 at 10:40:54AM -0400, Jim Quinlan wrote:
> > > > > > > > > This commit adds the boolean "brcm,enable-l1ss" property:
> > > > > > > > >
> > > > > > > > >   The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs --
> > > > > > > > >   requires the driver probe() to deliberately place the HW one of three
> > > > > > > > >   CLKREQ# modes:
> > > > > > > > >
> > > > > > > > >   (a) CLKREQ# driven by the RC unconditionally
> > > > > > > > >   (b) CLKREQ# driven by the EP for ASPM L0s, L1
> > > > > > > > >   (c) Bidirectional CLKREQ#, as used for L1 Substates (L1SS).
> > > > > > > > >
> > > > > > > > >   The HW+driver can tell the difference between downstream devices that
> > > > > > > > >   need (a) and (b), but does not know when to configure (c).  All devices
> > > > > > > > >   should work fine when the driver chooses (a) or (b), but (c) may be
> > > > > > > > >   desired to realize the extra power savings that L1SS offers.  So we
> > > > > > > > >   introduce the boolean "brcm,enable-l1ss" property to inform the driver
> > > > > > > > >   that (c) is desired.  Setting this property only makes sense when the
> > > > > > > > >   downstream device is L1SS-capable and the OS is configured to activate
> > > > > > > > >   this mode (e.g. policy==powersupersave).
> > > > > > > > >
> > > > > > > > >   This property is already present in the Raspian version of Linux, but the
> > > > > > > > >   upstream driver implementation that follows adds more details and
> > > > > > > > >   discerns between (a) and (b).
> > > > > > > > >
> > > > > > > > > Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
> > > > > > > > > Reviewed-by: Rob Herring <robh@kernel.org>
> > > > > > > > > ---
> > > > > > > > >  Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 9 +++++++++
> > > > > > > > >  1 file changed, 9 insertions(+)
> > > > > > > > >
> > > > > > > > > diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > > > > > index 7e15aae7d69e..8b61c2179608 100644
> > > > > > > > > --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > > > > > +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > > > > > @@ -64,6 +64,15 @@ properties:
> > > > > > > > >
> > > > > > > > >    aspm-no-l0s: true
> > > > > > > > >
> > > > > > > > > +  brcm,enable-l1ss:
> > > > > > > > > +    description: Indicates that PCIe L1SS power savings
> > > > > > > > > +      are desired, the downstream device is L1SS-capable, and the
> > > > > > > > > +      OS has been configured to enable this mode.  For boards
> > > > > > > >
> > > > > > > > What does this mean ? I don't think DT properties are supposed
> > > > > > > > to carry information related to how the OS is configured.
> > > > > > >
> > > > > > > The DT setting in question is unrelated to the statement "and the OS
> > > > > > > has been configured to
> > > > > > > enable this mode".
> > > > > > >
> > > > > > > This is merely saying that even if you enable "brcm,l1ss-enable"
> > > > > > > that you may not get L1SS power savings w/o setting
> > > > > > > "CONFIG_PCIEASPM_POWER_SUPERSAVE=y".
> > > > > > > I mentioned that exact term but a reviewer nakked it because
> > > > > > > apparently DT descriptions should not be OS specific.
> > >
> > > Yeah, probably the OS part should be dropped.
> >
> > I will drop it - if you don't mind.
> >
> > > > > > > I am actually open for this to be a command-line option but I wanted to honor
> > > > > > > what the Raspian OS folks have already done.  RaspianOS already has
> > > > > > > "brcm,enable-l1ss"
> > > > > > > set in their DTS files.
> > > > > >
> > > > > > This is about the mainline kernel, I don't have any visibility into
> > > > > > downstream kernels (where that property management was added without DT
> > > > > > and PCI maintainers supervision).
> > > > > >
> > > > > > Raspian OS folks' choice is theirs but it can't and it shouldn't override
> > > > > > the mainline review process even though I understand the position you
> > > > > > are in.
> > >
> > > Sure, but we shouldn't change things just to be different from
> > > downstream. If we're only discussing the color of the shed, then no
> > > point changing it.
> >
> > Sure, no problem.
> >
> > > > > Understood, but using the command line has its warts as well; I now recall the
> > > > > discussion Bjorn and I  had regarding this option.  I'm pretty sure
> > > > > that upstreaam will not allow the following
> > > > > possible command line kernel params:
> > > > >
> > > > >     brcm,enable-l1ss
> > > > >     pci=brcm,entable-l1ss
> > > > >
> > > > > Bjorn suggested using the  documented but (IMO) obscure  and  rarely
> > > > > used  format
> > > > >
> > > > >     pci=[<domain>:]<bus>:<dev>.<func>[/<dev>.<func>]*pci:<vendor>:<device>[:<subvendor>:<subdevice>]
> > > > >
> > > > > but this is just going in the wrong direction; here's why.  Using the
> > > > > above iformat s completely dependent on the
> > > > > PCI "linux-domaiin"  property,  a non-HW related DT property I  might
> > > > > add.  Since "linux-domain" is already
> > > > > a valid and well-used  DT property, and the value of  the above
> > > > > command line format is dependent
> > > > > on the value of the "linux-domain", why not be consistent and let
> > > > > "brcm,enable-l1ss" be a Broadcom specific property?
> > > >
> > > > I am just asking to add a module_param to the host controller driver.
> > >
> > > FWIW, gregkh pretty much always nacks new module parameters.
> >
> > Fine by me.
> >
> > > > Anyway - time is running out for v6.6, I need Rob's feedback, if I don't
> > > > hear from him today I will merge the last three patches and postpone the
> > > > discussion.
> > >
> > > You've already got my reviewed-by. If you aren't happy with this, then
> > > fine. I don't know enough about L1SS to comment further. Is it
> > > normally always supported or discoverable? If so, then I'd think we'd
> > > want it default enabled with a disable override flag. Maybe it should
> > > be generic?
> >
> > It is not that I am not happy with it - we asked questions to understand
> > what this property was for, I think that's normal.
> >
> > I will merge this series as-is.
> >
>
> There is a discussion ongoing here: https://lore.kernel.org/linux-pci/20230823181650.GL3737@thinkpad/T/#u
>
> Can you please hold on to merging this series until we've reached a conclusion?
 (2) There are odd boards out there which

TL;DR:  I'm okay with postponing the two clkreq# commits.

Sigh.  I really wish we had this discussion months ago when this
series was submitted.

I do think the best -- but not perfect -- way to do this is with a DT
param.  AFAICT there
is no way to do this with a command line param with it being accepted,
module_param or otherwise; please see
my reasons from this thread.  Also, Rob just said that GregH will
probably reject a new module_param
anyway.

That being said, the recent discussions are insightful and have me
reconsidering having
the "l1ss mode" be the default -- it has certainly worked well for the
RaspianOS folks.
That being said, the RaspianOS folks do not experience the flavor of
form-factors and devices
as Broadcom STB, and the admonitions of our HW designer are of great
concern to me.

In light of the above I am okay with postponing the two clkreq-related
commits to avoid any missteps.

Regards,
Jim

>
> - Mani
>
> > Lorenzo
>
> --
> மணிவண்ணன் சதாசிவம்

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Re: (subset) [PATCH v6 0/5] PCI: brcmstb: Configure appropriate HW CLKREQ# mode

[Lorenzo Pieralisi]

On Fri, 23 Jun 2023 10:40:53 -0400, Jim Quinlan wrote:
> v6 -- No code has been changed.
>    -- Changed commit subject and comment in "#PERST" commit (Bjorn, Cyril)
>    -- Changed sign-off and author email address for all commits.
>       This was due to a change in Broadcom's upstreaming policy.
> 
> v5 -- Remove DT property "brcm,completion-timeout-us" from
>       "DT bindings" commit.  Although this error may be reported
>       as a completion timeout, its cause was traced to an
>       internal bus timeout which may occur even when there is
>       no PCIe access being processed.  We set a timeout of four
>       seconds only if we are operating in "L1SS CLKREQ#" mode.
>    -- Correct CEM 2.0 reference provided by HW engineer,
>       s/3.2.5.2.5/3.2.5.2.2/ (Bjorn)
>    -- Add newline to dev_info() string (Stefan)
>    -- Change variable rval to unsigned (Stefan)
>    -- s/implementaion/implementation/ (Bjorn)
>    -- s/superpowersave/powersupersave/ (Bjorn)
>    -- Slightly modify message on "PERST#" commit.
>    -- Rebase to torvalds master
> 
> [...]

Applied to controller/brcmstb, thanks!

[4/5] PCI: brcmstb: Assert PERST# on BCM2711
      https://git.kernel.org/pci/pci/c/8eb8c2735306
[5/5] PCI: brcmstb: Remove stale comment
      https://git.kernel.org/pci/pci/c/6dac1507a654

Thanks,
Lorenzo

Re: [PATCH v6 2/5] PCI: brcmstb: Configure HW CLKREQ# mode appropriate for downstream device

[Sam Edwards]

On 6/23/23 08:40, Jim Quinlan wrote:

Hi Jim,

As I understand, the issue that this patch fixes can be difficult to 
trigger reliably. So I'll report that the abort occurs 100% of the time 
on a Compute Module 4, installed in slot 3 of a Turing Pi 2 cluster 
board, when a bootloader (U-Boot, in my case) is in the boot path. The 
third slot of the TP2 board connects to an ASM1061 chip with the CLKREQ# 
line left floating. I do not know why the bootloader is necessary for 
the crash to occur; I suspect it's timing-related.

With this patch applied to my kernel, my observed crash rate goes from 
100% to 0%, so:

> Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
> Tested-by: Florian Fainelli <f.fainelli@gmail.com>
> Tested-by: Cyril Brulebois <cyril@debamax.com>
Tested-by: Sam Edwards <CFSworks@gmail.com>

Many thanks,
Sam