* [PATCH 1/2] ARM: dts: qcom: sdx65: correct PCIe EP phy-names
@ 2023-08-27 11:45 Krzysztof Kozlowski
2023-08-27 11:45 ` [PATCH 2/2] ARM: dts: qcom: sdx65: add missing GCC clocks Krzysztof Kozlowski
2023-08-28 9:53 ` [PATCH 1/2] ARM: dts: qcom: sdx65: correct PCIe EP phy-names Konrad Dybcio
0 siblings, 2 replies; 5+ messages in thread
From: Krzysztof Kozlowski @ 2023-08-27 11:45 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel
Cc: Krzysztof Kozlowski
Qualcomm PCIe endpoint bindings expect phy-names to be "pciephy":
arch/arm/boot/dts/qcom/qcom-sdx65-mtp.dtb: pcie-ep@1c00000: phy-names:0: 'pciephy' was expected
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
index 81d018fe7d9b..93c6c80dc379 100644
--- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
@@ -337,7 +337,7 @@ pcie_ep: pcie-ep@1c00000 {
power-domains = <&gcc PCIE_GDSC>;
phys = <&pcie_phy>;
- phy-names = "pcie-phy";
+ phy-names = "pciephy";
max-link-speed = <3>;
num-lanes = <2>;
--
2.34.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/2] ARM: dts: qcom: sdx65: add missing GCC clocks
2023-08-27 11:45 [PATCH 1/2] ARM: dts: qcom: sdx65: correct PCIe EP phy-names Krzysztof Kozlowski
@ 2023-08-27 11:45 ` Krzysztof Kozlowski
2023-08-28 9:54 ` Konrad Dybcio
2023-08-28 9:53 ` [PATCH 1/2] ARM: dts: qcom: sdx65: correct PCIe EP phy-names Konrad Dybcio
1 sibling, 1 reply; 5+ messages in thread
From: Krzysztof Kozlowski @ 2023-08-27 11:45 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel
Cc: Krzysztof Kozlowski
The SDX65 GCC clock controller expects two required clocks:
pcie_pipe_clk and usb3_phy_wrapper_gcc_usb30_pipe_clk. The first one is
provided by existing phy node, but second is not yet implemented.
qcom-sdx65-mtp.dtb: clock-controller@100000: clocks: [[11, 0], [11, 1], [12]] is too short
qcom-sdx65-mtp.dtb: clock-controller@100000: clock-names: ['bi_tcxo', 'bi_tcxo_ao', 'sleep_clk'] is too short
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
index 93c6c80dc379..58635bbc1123 100644
--- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
@@ -204,8 +204,16 @@ soc: soc {
gcc: clock-controller@100000 {
compatible = "qcom,gcc-sdx65";
reg = <0x00100000 0x001f7400>;
- clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>;
- clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&sleep_clk>,
+ <&pcie_phy>,
+ <0>;
+ clock-names = "bi_tcxo",
+ "bi_tcxo_ao",
+ "sleep_clk",
+ "pcie_pipe_clk",
+ "usb3_phy_wrapper_gcc_usb30_pipe_clk";
#power-domain-cells = <1>;
#clock-cells = <1>;
#reset-cells = <1>;
--
2.34.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] ARM: dts: qcom: sdx65: correct PCIe EP phy-names
2023-08-27 11:45 [PATCH 1/2] ARM: dts: qcom: sdx65: correct PCIe EP phy-names Krzysztof Kozlowski
2023-08-27 11:45 ` [PATCH 2/2] ARM: dts: qcom: sdx65: add missing GCC clocks Krzysztof Kozlowski
@ 2023-08-28 9:53 ` Konrad Dybcio
2023-08-28 10:29 ` Krzysztof Kozlowski
1 sibling, 1 reply; 5+ messages in thread
From: Konrad Dybcio @ 2023-08-28 9:53 UTC (permalink / raw)
To: Krzysztof Kozlowski, Andy Gross, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel
On 27.08.2023 13:45, Krzysztof Kozlowski wrote:
> Qualcomm PCIe endpoint bindings expect phy-names to be "pciephy":
>
> arch/arm/boot/dts/qcom/qcom-sdx65-mtp.dtb: pcie-ep@1c00000: phy-names:0: 'pciephy' was expected
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
drivers/pci/controller/dwc/pcie-qcom-ep.c
549: pcie_ep->phy = devm_phy_optional_get(dev, "pciephy");
welp looks like this never worked..
Fixes: 9c0bb38414a4 ("ARM: dts: qcom: sdx65: Add support for PCIe EP")
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] ARM: dts: qcom: sdx65: add missing GCC clocks
2023-08-27 11:45 ` [PATCH 2/2] ARM: dts: qcom: sdx65: add missing GCC clocks Krzysztof Kozlowski
@ 2023-08-28 9:54 ` Konrad Dybcio
0 siblings, 0 replies; 5+ messages in thread
From: Konrad Dybcio @ 2023-08-28 9:54 UTC (permalink / raw)
To: Krzysztof Kozlowski, Andy Gross, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel
On 27.08.2023 13:45, Krzysztof Kozlowski wrote:
> The SDX65 GCC clock controller expects two required clocks:
> pcie_pipe_clk and usb3_phy_wrapper_gcc_usb30_pipe_clk. The first one is
> provided by existing phy node, but second is not yet implemented.
>
> qcom-sdx65-mtp.dtb: clock-controller@100000: clocks: [[11, 0], [11, 1], [12]] is too short
> qcom-sdx65-mtp.dtb: clock-controller@100000: clock-names: ['bi_tcxo', 'bi_tcxo_ao', 'sleep_clk'] is too short
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] ARM: dts: qcom: sdx65: correct PCIe EP phy-names
2023-08-28 9:53 ` [PATCH 1/2] ARM: dts: qcom: sdx65: correct PCIe EP phy-names Konrad Dybcio
@ 2023-08-28 10:29 ` Krzysztof Kozlowski
0 siblings, 0 replies; 5+ messages in thread
From: Krzysztof Kozlowski @ 2023-08-28 10:29 UTC (permalink / raw)
To: Konrad Dybcio, Andy Gross, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel
On 28/08/2023 11:53, Konrad Dybcio wrote:
> On 27.08.2023 13:45, Krzysztof Kozlowski wrote:
>> Qualcomm PCIe endpoint bindings expect phy-names to be "pciephy":
>>
>> arch/arm/boot/dts/qcom/qcom-sdx65-mtp.dtb: pcie-ep@1c00000: phy-names:0: 'pciephy' was expected
>>
>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>> ---
> drivers/pci/controller/dwc/pcie-qcom-ep.c
> 549: pcie_ep->phy = devm_phy_optional_get(dev, "pciephy");
>
> welp looks like this never worked..
And if only it could have been spotted with some automated tooling,
before posting to LKML...
>
>
> Fixes: 9c0bb38414a4 ("ARM: dts: qcom: sdx65: Add support for PCIe EP")
> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Thanks
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2023-08-28 10:30 UTC | newest]
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2023-08-27 11:45 [PATCH 1/2] ARM: dts: qcom: sdx65: correct PCIe EP phy-names Krzysztof Kozlowski
2023-08-27 11:45 ` [PATCH 2/2] ARM: dts: qcom: sdx65: add missing GCC clocks Krzysztof Kozlowski
2023-08-28 9:54 ` Konrad Dybcio
2023-08-28 9:53 ` [PATCH 1/2] ARM: dts: qcom: sdx65: correct PCIe EP phy-names Konrad Dybcio
2023-08-28 10:29 ` Krzysztof Kozlowski
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