* [PATCH 0/7] KVM RISC-V Conditional Operations
@ 2023-09-19 3:53 Anup Patel
2023-09-19 3:53 ` [PATCH 1/7] RISC-V: Detect XVentanaCondOps from ISA string Anup Patel
` (6 more replies)
0 siblings, 7 replies; 24+ messages in thread
From: Anup Patel @ 2023-09-19 3:53 UTC (permalink / raw)
To: Paolo Bonzini, Atish Patra, Palmer Dabbelt, Paul Walmsley,
Conor Dooley, Rob Herring, Krzysztof Kozlowski, Shuah Khan
Cc: Andrew Jones, Mayuresh Chitale, devicetree, kvm, kvm-riscv,
linux-riscv, linux-kernel, linux-kselftest, Anup Patel
This series extends KVM RISC-V to allow Guest/VM discover and use
conditional operations related ISA extensions (namely XVentanaCondOps
and Zicond).
To try these patches, use KVMTOOL from riscv_zbx_zicntr_smstateen_condops_v1
branch at: https://github.com/avpatel/kvmtool.git
These patches are based upon the latest riscv_kvm_queue and can also be
found in the riscv_kvm_condops_v1 branch at:
https://github.com/avpatel/linux.git
Anup Patel (7):
RISC-V: Detect XVentanaCondOps from ISA string
RISC-V: Detect Zicond from ISA string
RISC-V: KVM: Allow XVentanaCondOps extension for Guest/VM
RISC-V: KVM: Allow Zicond extension for Guest/VM
KVM: riscv: selftests: Add senvcfg register to get-reg-list test
KVM: riscv: selftests: Add smstateen registers to get-reg-list test
KVM: riscv: selftests: Add condops extensions to get-reg-list test
.../devicetree/bindings/riscv/extensions.yaml | 13 ++++++
arch/riscv/include/asm/hwcap.h | 2 +
arch/riscv/include/uapi/asm/kvm.h | 2 +
arch/riscv/kernel/cpufeature.c | 2 +
arch/riscv/kvm/vcpu_onereg.c | 4 ++
.../selftests/kvm/riscv/get-reg-list.c | 41 +++++++++++++++++++
6 files changed, 64 insertions(+)
--
2.34.1
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 1/7] RISC-V: Detect XVentanaCondOps from ISA string
2023-09-19 3:53 [PATCH 0/7] KVM RISC-V Conditional Operations Anup Patel
@ 2023-09-19 3:53 ` Anup Patel
2023-09-19 7:26 ` Conor Dooley
` (2 more replies)
2023-09-19 3:53 ` [PATCH 2/7] RISC-V: Detect Zicond " Anup Patel
` (5 subsequent siblings)
6 siblings, 3 replies; 24+ messages in thread
From: Anup Patel @ 2023-09-19 3:53 UTC (permalink / raw)
To: Paolo Bonzini, Atish Patra, Palmer Dabbelt, Paul Walmsley,
Conor Dooley, Rob Herring, Krzysztof Kozlowski, Shuah Khan
Cc: Andrew Jones, Mayuresh Chitale, devicetree, kvm, kvm-riscv,
linux-riscv, linux-kernel, linux-kselftest, Anup Patel
The Veyron-V1 CPU supports custom conditional arithmetic and
conditional-select/move operations referred to as XVentanaCondOps
extension. In fact, QEMU RISC-V also has support for emulating
XVentanaCondOps extension.
Let us detect XVentanaCondOps extension from ISA string available
through DT or ACPI.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++
arch/riscv/include/asm/hwcap.h | 1 +
arch/riscv/kernel/cpufeature.c | 1 +
3 files changed, 9 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 36ff6749fbba..cad8ef68eca7 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -171,6 +171,13 @@ properties:
memory types as ratified in the 20191213 version of the privileged
ISA specification.
+ - const: xventanacondops
+ description: |
+ The Ventana specific XVentanaCondOps extension for conditional
+ arithmetic and conditional-select/move operations defined by the
+ Ventana custom extensions specification v1.0.1 (or higher) at
+ https://github.com/ventanamicro/ventana-custom-extensions/releases.
+
- const: zba
description: |
The standard Zba bit-manipulation extension for address generation
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 0f520f7d058a..b7efe9e2fa89 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -59,6 +59,7 @@
#define RISCV_ISA_EXT_ZIFENCEI 41
#define RISCV_ISA_EXT_ZIHPM 42
#define RISCV_ISA_EXT_SMSTATEEN 43
+#define RISCV_ISA_EXT_XVENTANACONDOPS 44
#define RISCV_ISA_EXT_MAX 64
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 3755a8c2a9de..3a31d34fe709 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -182,6 +182,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
__RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
__RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
__RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
+ __RISCV_ISA_EXT_DATA(xventanacondops, RISCV_ISA_EXT_XVENTANACONDOPS),
};
const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext);
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 2/7] RISC-V: Detect Zicond from ISA string
2023-09-19 3:53 [PATCH 0/7] KVM RISC-V Conditional Operations Anup Patel
2023-09-19 3:53 ` [PATCH 1/7] RISC-V: Detect XVentanaCondOps from ISA string Anup Patel
@ 2023-09-19 3:53 ` Anup Patel
2023-09-19 7:27 ` Conor Dooley
2023-09-20 7:44 ` Andrew Jones
2023-09-19 3:53 ` [PATCH 3/7] RISC-V: KVM: Allow XVentanaCondOps extension for Guest/VM Anup Patel
` (4 subsequent siblings)
6 siblings, 2 replies; 24+ messages in thread
From: Anup Patel @ 2023-09-19 3:53 UTC (permalink / raw)
To: Paolo Bonzini, Atish Patra, Palmer Dabbelt, Paul Walmsley,
Conor Dooley, Rob Herring, Krzysztof Kozlowski, Shuah Khan
Cc: Andrew Jones, Mayuresh Chitale, devicetree, kvm, kvm-riscv,
linux-riscv, linux-kernel, linux-kselftest, Anup Patel
The RISC-V integer conditional (Zicond) operation extension defines
standard conditional arithmetic and conditional-select/move operations
which are inspired from the XVentanaCondOps extension. In fact, QEMU
RISC-V also has support for emulating Zicond extension.
Let us detect Zicond extension from ISA string available through
DT or ACPI.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
arch/riscv/include/asm/hwcap.h | 1 +
arch/riscv/kernel/cpufeature.c | 1 +
3 files changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index cad8ef68eca7..7ea90e2dbc5b 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -225,6 +225,12 @@ properties:
ratified in the 20191213 version of the unprivileged ISA
specification.
+ - const: zicond
+ description:
+ The standard Zicond extension for conditional arithmetic and
+ conditional-select/move operations as ratified in commit 8fb6694
+ ("Update Gemfile") of riscv-zicond.
+
- const: zicsr
description: |
The standard Zicsr extension for control and status register
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index b7efe9e2fa89..15bafc02ffd4 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -60,6 +60,7 @@
#define RISCV_ISA_EXT_ZIHPM 42
#define RISCV_ISA_EXT_SMSTATEEN 43
#define RISCV_ISA_EXT_XVENTANACONDOPS 44
+#define RISCV_ISA_EXT_ZICOND 45
#define RISCV_ISA_EXT_MAX 64
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 3a31d34fe709..49b6551f3347 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -174,6 +174,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
__RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA),
__RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
__RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS),
+ __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND),
__RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),
__RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN),
__RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 3/7] RISC-V: KVM: Allow XVentanaCondOps extension for Guest/VM
2023-09-19 3:53 [PATCH 0/7] KVM RISC-V Conditional Operations Anup Patel
2023-09-19 3:53 ` [PATCH 1/7] RISC-V: Detect XVentanaCondOps from ISA string Anup Patel
2023-09-19 3:53 ` [PATCH 2/7] RISC-V: Detect Zicond " Anup Patel
@ 2023-09-19 3:53 ` Anup Patel
2023-09-20 7:46 ` Andrew Jones
2023-09-19 3:53 ` [PATCH 4/7] RISC-V: KVM: Allow Zicond " Anup Patel
` (3 subsequent siblings)
6 siblings, 1 reply; 24+ messages in thread
From: Anup Patel @ 2023-09-19 3:53 UTC (permalink / raw)
To: Paolo Bonzini, Atish Patra, Palmer Dabbelt, Paul Walmsley,
Conor Dooley, Rob Herring, Krzysztof Kozlowski, Shuah Khan
Cc: Andrew Jones, Mayuresh Chitale, devicetree, kvm, kvm-riscv,
linux-riscv, linux-kernel, linux-kselftest, Anup Patel
We extend the KVM ISA extension ONE_REG interface to allow KVM
user space to detect and enable XVentanaCondOps extension for
Guest/VM.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
arch/riscv/include/uapi/asm/kvm.h | 1 +
arch/riscv/kvm/vcpu_onereg.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
index b1baf6f096a3..e030c12c7dfc 100644
--- a/arch/riscv/include/uapi/asm/kvm.h
+++ b/arch/riscv/include/uapi/asm/kvm.h
@@ -138,6 +138,7 @@ enum KVM_RISCV_ISA_EXT_ID {
KVM_RISCV_ISA_EXT_ZIFENCEI,
KVM_RISCV_ISA_EXT_ZIHPM,
KVM_RISCV_ISA_EXT_SMSTATEEN,
+ KVM_RISCV_ISA_EXT_XVENTANACONDOPS,
KVM_RISCV_ISA_EXT_MAX,
};
diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c
index 388599fcf684..17a847a1114b 100644
--- a/arch/riscv/kvm/vcpu_onereg.c
+++ b/arch/riscv/kvm/vcpu_onereg.c
@@ -40,6 +40,7 @@ static const unsigned long kvm_isa_ext_arr[] = {
KVM_ISA_EXT_ARR(SVINVAL),
KVM_ISA_EXT_ARR(SVNAPOT),
KVM_ISA_EXT_ARR(SVPBMT),
+ KVM_ISA_EXT_ARR(XVENTANACONDOPS),
KVM_ISA_EXT_ARR(ZBA),
KVM_ISA_EXT_ARR(ZBB),
KVM_ISA_EXT_ARR(ZBS),
@@ -89,6 +90,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext)
case KVM_RISCV_ISA_EXT_SSTC:
case KVM_RISCV_ISA_EXT_SVINVAL:
case KVM_RISCV_ISA_EXT_SVNAPOT:
+ case KVM_RISCV_ISA_EXT_XVENTANACONDOPS:
case KVM_RISCV_ISA_EXT_ZBA:
case KVM_RISCV_ISA_EXT_ZBB:
case KVM_RISCV_ISA_EXT_ZBS:
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 4/7] RISC-V: KVM: Allow Zicond extension for Guest/VM
2023-09-19 3:53 [PATCH 0/7] KVM RISC-V Conditional Operations Anup Patel
` (2 preceding siblings ...)
2023-09-19 3:53 ` [PATCH 3/7] RISC-V: KVM: Allow XVentanaCondOps extension for Guest/VM Anup Patel
@ 2023-09-19 3:53 ` Anup Patel
2023-09-20 7:46 ` Andrew Jones
2023-09-19 3:53 ` [PATCH 5/7] KVM: riscv: selftests: Add senvcfg register to get-reg-list test Anup Patel
` (2 subsequent siblings)
6 siblings, 1 reply; 24+ messages in thread
From: Anup Patel @ 2023-09-19 3:53 UTC (permalink / raw)
To: Paolo Bonzini, Atish Patra, Palmer Dabbelt, Paul Walmsley,
Conor Dooley, Rob Herring, Krzysztof Kozlowski, Shuah Khan
Cc: Andrew Jones, Mayuresh Chitale, devicetree, kvm, kvm-riscv,
linux-riscv, linux-kernel, linux-kselftest, Anup Patel
We extend the KVM ISA extension ONE_REG interface to allow KVM
user space to detect and enable Zicond extension for Guest/VM.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
arch/riscv/include/uapi/asm/kvm.h | 1 +
arch/riscv/kvm/vcpu_onereg.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
index e030c12c7dfc..35ceb38a4eff 100644
--- a/arch/riscv/include/uapi/asm/kvm.h
+++ b/arch/riscv/include/uapi/asm/kvm.h
@@ -139,6 +139,7 @@ enum KVM_RISCV_ISA_EXT_ID {
KVM_RISCV_ISA_EXT_ZIHPM,
KVM_RISCV_ISA_EXT_SMSTATEEN,
KVM_RISCV_ISA_EXT_XVENTANACONDOPS,
+ KVM_RISCV_ISA_EXT_ZICOND,
KVM_RISCV_ISA_EXT_MAX,
};
diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c
index 17a847a1114b..d3ca4969c985 100644
--- a/arch/riscv/kvm/vcpu_onereg.c
+++ b/arch/riscv/kvm/vcpu_onereg.c
@@ -47,6 +47,7 @@ static const unsigned long kvm_isa_ext_arr[] = {
KVM_ISA_EXT_ARR(ZICBOM),
KVM_ISA_EXT_ARR(ZICBOZ),
KVM_ISA_EXT_ARR(ZICNTR),
+ KVM_ISA_EXT_ARR(ZICOND),
KVM_ISA_EXT_ARR(ZICSR),
KVM_ISA_EXT_ARR(ZIFENCEI),
KVM_ISA_EXT_ARR(ZIHINTPAUSE),
@@ -95,6 +96,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext)
case KVM_RISCV_ISA_EXT_ZBB:
case KVM_RISCV_ISA_EXT_ZBS:
case KVM_RISCV_ISA_EXT_ZICNTR:
+ case KVM_RISCV_ISA_EXT_ZICOND:
case KVM_RISCV_ISA_EXT_ZICSR:
case KVM_RISCV_ISA_EXT_ZIFENCEI:
case KVM_RISCV_ISA_EXT_ZIHINTPAUSE:
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 5/7] KVM: riscv: selftests: Add senvcfg register to get-reg-list test
2023-09-19 3:53 [PATCH 0/7] KVM RISC-V Conditional Operations Anup Patel
` (3 preceding siblings ...)
2023-09-19 3:53 ` [PATCH 4/7] RISC-V: KVM: Allow Zicond " Anup Patel
@ 2023-09-19 3:53 ` Anup Patel
2023-09-20 7:50 ` Andrew Jones
2023-09-19 3:53 ` [PATCH 6/7] KVM: riscv: selftests: Add smstateen registers " Anup Patel
2023-09-19 3:53 ` [PATCH 7/7] KVM: riscv: selftests: Add condops extensions " Anup Patel
6 siblings, 1 reply; 24+ messages in thread
From: Anup Patel @ 2023-09-19 3:53 UTC (permalink / raw)
To: Paolo Bonzini, Atish Patra, Palmer Dabbelt, Paul Walmsley,
Conor Dooley, Rob Herring, Krzysztof Kozlowski, Shuah Khan
Cc: Andrew Jones, Mayuresh Chitale, devicetree, kvm, kvm-riscv,
linux-riscv, linux-kernel, linux-kselftest, Anup Patel
We have a new senvcfg register in the general CSR ONE_REG interface
so let us add it to get-reg-list test.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
tools/testing/selftests/kvm/riscv/get-reg-list.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c
index 85907c86b835..0928c35470ae 100644
--- a/tools/testing/selftests/kvm/riscv/get-reg-list.c
+++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c
@@ -209,6 +209,8 @@ static const char *general_csr_id_to_str(__u64 reg_off)
return RISCV_CSR_GENERAL(satp);
case KVM_REG_RISCV_CSR_REG(scounteren):
return RISCV_CSR_GENERAL(scounteren);
+ case KVM_REG_RISCV_CSR_REG(senvcfg):
+ return RISCV_CSR_GENERAL(senvcfg);
}
TEST_FAIL("Unknown general csr reg: 0x%llx", reg_off);
@@ -532,6 +534,7 @@ static __u64 base_regs[] = {
KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(sip),
KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(satp),
KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(scounteren),
+ KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(senvcfg),
KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(frequency),
KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(time),
KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(compare),
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 6/7] KVM: riscv: selftests: Add smstateen registers to get-reg-list test
2023-09-19 3:53 [PATCH 0/7] KVM RISC-V Conditional Operations Anup Patel
` (4 preceding siblings ...)
2023-09-19 3:53 ` [PATCH 5/7] KVM: riscv: selftests: Add senvcfg register to get-reg-list test Anup Patel
@ 2023-09-19 3:53 ` Anup Patel
2023-09-20 8:13 ` Andrew Jones
2023-09-19 3:53 ` [PATCH 7/7] KVM: riscv: selftests: Add condops extensions " Anup Patel
6 siblings, 1 reply; 24+ messages in thread
From: Anup Patel @ 2023-09-19 3:53 UTC (permalink / raw)
To: Paolo Bonzini, Atish Patra, Palmer Dabbelt, Paul Walmsley,
Conor Dooley, Rob Herring, Krzysztof Kozlowski, Shuah Khan
Cc: Andrew Jones, Mayuresh Chitale, devicetree, kvm, kvm-riscv,
linux-riscv, linux-kernel, linux-kselftest, Anup Patel
We have a new smstateen registers as separate sub-type of CSR ONE_REG
interface so let us add these registers to get-reg-list test.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
.../selftests/kvm/riscv/get-reg-list.c | 34 +++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c
index 0928c35470ae..9f464c7996c6 100644
--- a/tools/testing/selftests/kvm/riscv/get-reg-list.c
+++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c
@@ -49,6 +49,7 @@ bool filter_reg(__u64 reg)
case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICSR:
case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIFENCEI:
case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHPM:
+ case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SMSTATEEN:
return true;
/* AIA registers are always available when Ssaia can't be disabled */
case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siselect):
@@ -184,6 +185,8 @@ static const char *core_id_to_str(const char *prefix, __u64 id)
"KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(" #csr ")"
#define RISCV_CSR_AIA(csr) \
"KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_REG(" #csr ")"
+#define RISCV_CSR_SMSTATEEN(csr) \
+ "KVM_REG_RISCV_CSR_SMSTATEEN | KVM_REG_RISCV_CSR_REG(" #csr ")"
static const char *general_csr_id_to_str(__u64 reg_off)
{
@@ -241,6 +244,18 @@ static const char *aia_csr_id_to_str(__u64 reg_off)
return NULL;
}
+static const char *smstateen_csr_id_to_str(__u64 reg_off)
+{
+ /* reg_off is the offset into struct kvm_riscv_smstateen_csr */
+ switch (reg_off) {
+ case KVM_REG_RISCV_CSR_SMSTATEEN_REG(sstateen0):
+ return RISCV_CSR_SMSTATEEN(sstateen0);
+ }
+
+ TEST_FAIL("Unknown smstateen csr reg: 0x%llx", reg_off);
+ return NULL;
+}
+
static const char *csr_id_to_str(const char *prefix, __u64 id)
{
__u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CSR);
@@ -253,6 +268,8 @@ static const char *csr_id_to_str(const char *prefix, __u64 id)
return general_csr_id_to_str(reg_off);
case KVM_REG_RISCV_CSR_AIA:
return aia_csr_id_to_str(reg_off);
+ case KVM_REG_RISCV_CSR_SMSTATEEN:
+ return smstateen_csr_id_to_str(reg_off);
}
TEST_FAIL("%s: Unknown csr subtype: 0x%llx", prefix, reg_subtype);
@@ -342,6 +359,7 @@ static const char *isa_ext_id_to_str(__u64 id)
"KVM_RISCV_ISA_EXT_ZICSR",
"KVM_RISCV_ISA_EXT_ZIFENCEI",
"KVM_RISCV_ISA_EXT_ZIHPM",
+ "KVM_RISCV_ISA_EXT_SMSTATEEN",
};
if (reg_off >= ARRAY_SIZE(kvm_isa_ext_reg_name)) {
@@ -629,6 +647,11 @@ static __u64 aia_regs[] = {
KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSAIA,
};
+static __u64 smstateen_regs[] = {
+ KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_SMSTATEEN | KVM_REG_RISCV_CSR_SMSTATEEN_REG(sstateen0),
+ KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SMSTATEEN,
+};
+
static __u64 fp_f_regs[] = {
KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[0]),
KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[1]),
@@ -736,6 +759,8 @@ static __u64 fp_d_regs[] = {
{"zihpm", .feature = KVM_RISCV_ISA_EXT_ZIHPM, .regs = zihpm_regs, .regs_n = ARRAY_SIZE(zihpm_regs),}
#define AIA_REGS_SUBLIST \
{"aia", .feature = KVM_RISCV_ISA_EXT_SSAIA, .regs = aia_regs, .regs_n = ARRAY_SIZE(aia_regs),}
+#define SMSTATEEN_REGS_SUBLIST \
+ {"smstateen", .feature = KVM_RISCV_ISA_EXT_SMSTATEEN, .regs = smstateen_regs, .regs_n = ARRAY_SIZE(smstateen_regs),}
#define FP_F_REGS_SUBLIST \
{"fp_f", .feature = KVM_RISCV_ISA_EXT_F, .regs = fp_f_regs, \
.regs_n = ARRAY_SIZE(fp_f_regs),}
@@ -863,6 +888,14 @@ static struct vcpu_reg_list aia_config = {
},
};
+static struct vcpu_reg_list smstateen_config = {
+ .sublists = {
+ BASE_SUBLIST,
+ SMSTATEEN_REGS_SUBLIST,
+ {0},
+ },
+};
+
static struct vcpu_reg_list fp_f_config = {
.sublists = {
BASE_SUBLIST,
@@ -895,6 +928,7 @@ struct vcpu_reg_list *vcpu_configs[] = {
&zifencei_config,
&zihpm_config,
&aia_config,
+ &smstateen_config,
&fp_f_config,
&fp_d_config,
};
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 7/7] KVM: riscv: selftests: Add condops extensions to get-reg-list test
2023-09-19 3:53 [PATCH 0/7] KVM RISC-V Conditional Operations Anup Patel
` (5 preceding siblings ...)
2023-09-19 3:53 ` [PATCH 6/7] KVM: riscv: selftests: Add smstateen registers " Anup Patel
@ 2023-09-19 3:53 ` Anup Patel
2023-09-20 8:18 ` Andrew Jones
6 siblings, 1 reply; 24+ messages in thread
From: Anup Patel @ 2023-09-19 3:53 UTC (permalink / raw)
To: Paolo Bonzini, Atish Patra, Palmer Dabbelt, Paul Walmsley,
Conor Dooley, Rob Herring, Krzysztof Kozlowski, Shuah Khan
Cc: Andrew Jones, Mayuresh Chitale, devicetree, kvm, kvm-riscv,
linux-riscv, linux-kernel, linux-kselftest, Anup Patel
We have a new conditional operations related ISA extensions so let us add
these extensions to get-reg-list test.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
tools/testing/selftests/kvm/riscv/get-reg-list.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c
index 9f464c7996c6..4ad4bf87fa78 100644
--- a/tools/testing/selftests/kvm/riscv/get-reg-list.c
+++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c
@@ -50,6 +50,8 @@ bool filter_reg(__u64 reg)
case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIFENCEI:
case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHPM:
case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SMSTATEEN:
+ case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_XVENTANACONDOPS:
+ case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICOND:
return true;
/* AIA registers are always available when Ssaia can't be disabled */
case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siselect):
@@ -360,6 +362,8 @@ static const char *isa_ext_id_to_str(__u64 id)
"KVM_RISCV_ISA_EXT_ZIFENCEI",
"KVM_RISCV_ISA_EXT_ZIHPM",
"KVM_RISCV_ISA_EXT_SMSTATEEN",
+ "KVM_RISCV_ISA_EXT_XVENTANACONDOPS",
+ "KVM_RISCV_ISA_EXT_ZICOND",
};
if (reg_off >= ARRAY_SIZE(kvm_isa_ext_reg_name)) {
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH 1/7] RISC-V: Detect XVentanaCondOps from ISA string
2023-09-19 3:53 ` [PATCH 1/7] RISC-V: Detect XVentanaCondOps from ISA string Anup Patel
@ 2023-09-19 7:26 ` Conor Dooley
2023-09-25 13:30 ` Anup Patel
2023-09-20 7:38 ` Andrew Jones
2023-10-02 6:27 ` Christoph Hellwig
2 siblings, 1 reply; 24+ messages in thread
From: Conor Dooley @ 2023-09-19 7:26 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Atish Patra, Palmer Dabbelt, Paul Walmsley,
Rob Herring, Krzysztof Kozlowski, Shuah Khan, Andrew Jones,
Mayuresh Chitale, devicetree, kvm, kvm-riscv, linux-riscv,
linux-kernel, linux-kselftest
[-- Attachment #1: Type: text/plain, Size: 3055 bytes --]
Hey Anup,
On Tue, Sep 19, 2023 at 09:23:37AM +0530, Anup Patel wrote:
> The Veyron-V1 CPU supports custom conditional arithmetic and
> conditional-select/move operations referred to as XVentanaCondOps
> extension. In fact, QEMU RISC-V also has support for emulating
> XVentanaCondOps extension.
>
> Let us detect XVentanaCondOps extension from ISA string available
> through DT or ACPI.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
> Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++
> arch/riscv/include/asm/hwcap.h | 1 +
> arch/riscv/kernel/cpufeature.c | 1 +
> 3 files changed, 9 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index 36ff6749fbba..cad8ef68eca7 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -171,6 +171,13 @@ properties:
> memory types as ratified in the 20191213 version of the privileged
> ISA specification.
>
> + - const: xventanacondops
> + description: |
> + The Ventana specific XVentanaCondOps extension for conditional
> + arithmetic and conditional-select/move operations defined by the
> + Ventana custom extensions specification v1.0.1 (or higher) at
> + https://github.com/ventanamicro/ventana-custom-extensions/releases.
> +
For this and the next patch, the binding change needs to be split out
from the code. checkpatch should've complained about it.
> - const: zba
> description: |
> The standard Zba bit-manipulation extension for address generation
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index 0f520f7d058a..b7efe9e2fa89 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -59,6 +59,7 @@
> #define RISCV_ISA_EXT_ZIFENCEI 41
> #define RISCV_ISA_EXT_ZIHPM 42
> #define RISCV_ISA_EXT_SMSTATEEN 43
> +#define RISCV_ISA_EXT_XVENTANACONDOPS 44
>
> #define RISCV_ISA_EXT_MAX 64
>
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 3755a8c2a9de..3a31d34fe709 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -182,6 +182,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
> __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
> __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
> + __RISCV_ISA_EXT_DATA(xventanacondops, RISCV_ISA_EXT_XVENTANACONDOPS),
I've been banging on for a bit about people doing weird stuff to detect
their vendor extensions, so nice to see it being done properly :)
Cheers,
Conor.
> };
>
> const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext);
> --
> 2.34.1
>
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 2/7] RISC-V: Detect Zicond from ISA string
2023-09-19 3:53 ` [PATCH 2/7] RISC-V: Detect Zicond " Anup Patel
@ 2023-09-19 7:27 ` Conor Dooley
2023-09-25 13:31 ` Anup Patel
2023-09-20 7:44 ` Andrew Jones
1 sibling, 1 reply; 24+ messages in thread
From: Conor Dooley @ 2023-09-19 7:27 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Atish Patra, Palmer Dabbelt, Paul Walmsley,
Rob Herring, Krzysztof Kozlowski, Shuah Khan, Andrew Jones,
Mayuresh Chitale, devicetree, kvm, kvm-riscv, linux-riscv,
linux-kernel, linux-kselftest
[-- Attachment #1: Type: text/plain, Size: 2760 bytes --]
On Tue, Sep 19, 2023 at 09:23:38AM +0530, Anup Patel wrote:
> The RISC-V integer conditional (Zicond) operation extension defines
> standard conditional arithmetic and conditional-select/move operations
> which are inspired from the XVentanaCondOps extension. In fact, QEMU
> RISC-V also has support for emulating Zicond extension.
>
> Let us detect Zicond extension from ISA string available through
> DT or ACPI.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Same applies here w.r.t. splitting in two.
Thanks,
Conor.
> ---
> Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
> arch/riscv/include/asm/hwcap.h | 1 +
> arch/riscv/kernel/cpufeature.c | 1 +
> 3 files changed, 8 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index cad8ef68eca7..7ea90e2dbc5b 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -225,6 +225,12 @@ properties:
> ratified in the 20191213 version of the unprivileged ISA
> specification.
>
> + - const: zicond
> + description:
> + The standard Zicond extension for conditional arithmetic and
> + conditional-select/move operations as ratified in commit 8fb6694
> + ("Update Gemfile") of riscv-zicond.
> +
> - const: zicsr
> description: |
> The standard Zicsr extension for control and status register
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index b7efe9e2fa89..15bafc02ffd4 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -60,6 +60,7 @@
> #define RISCV_ISA_EXT_ZIHPM 42
> #define RISCV_ISA_EXT_SMSTATEEN 43
> #define RISCV_ISA_EXT_XVENTANACONDOPS 44
> +#define RISCV_ISA_EXT_ZICOND 45
>
> #define RISCV_ISA_EXT_MAX 64
>
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 3a31d34fe709..49b6551f3347 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -174,6 +174,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA),
> __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
> __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS),
> + __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND),
> __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),
> __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN),
> __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
> --
> 2.34.1
>
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 1/7] RISC-V: Detect XVentanaCondOps from ISA string
2023-09-19 3:53 ` [PATCH 1/7] RISC-V: Detect XVentanaCondOps from ISA string Anup Patel
2023-09-19 7:26 ` Conor Dooley
@ 2023-09-20 7:38 ` Andrew Jones
2023-10-02 6:27 ` Christoph Hellwig
2 siblings, 0 replies; 24+ messages in thread
From: Andrew Jones @ 2023-09-20 7:38 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Atish Patra, Palmer Dabbelt, Paul Walmsley,
Conor Dooley, Rob Herring, Krzysztof Kozlowski, Shuah Khan,
Mayuresh Chitale, devicetree, kvm, kvm-riscv, linux-riscv,
linux-kernel, linux-kselftest
On Tue, Sep 19, 2023 at 09:23:37AM +0530, Anup Patel wrote:
> The Veyron-V1 CPU supports custom conditional arithmetic and
> conditional-select/move operations referred to as XVentanaCondOps
> extension. In fact, QEMU RISC-V also has support for emulating
> XVentanaCondOps extension.
>
> Let us detect XVentanaCondOps extension from ISA string available
> through DT or ACPI.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
> Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++
> arch/riscv/include/asm/hwcap.h | 1 +
> arch/riscv/kernel/cpufeature.c | 1 +
> 3 files changed, 9 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index 36ff6749fbba..cad8ef68eca7 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -171,6 +171,13 @@ properties:
> memory types as ratified in the 20191213 version of the privileged
> ISA specification.
>
> + - const: xventanacondops
> + description: |
> + The Ventana specific XVentanaCondOps extension for conditional
> + arithmetic and conditional-select/move operations defined by the
> + Ventana custom extensions specification v1.0.1 (or higher) at
> + https://github.com/ventanamicro/ventana-custom-extensions/releases.
> +
> - const: zba
> description: |
> The standard Zba bit-manipulation extension for address generation
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index 0f520f7d058a..b7efe9e2fa89 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -59,6 +59,7 @@
> #define RISCV_ISA_EXT_ZIFENCEI 41
> #define RISCV_ISA_EXT_ZIHPM 42
> #define RISCV_ISA_EXT_SMSTATEEN 43
> +#define RISCV_ISA_EXT_XVENTANACONDOPS 44
>
> #define RISCV_ISA_EXT_MAX 64
>
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 3755a8c2a9de..3a31d34fe709 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -182,6 +182,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
> __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
> __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
> + __RISCV_ISA_EXT_DATA(xventanacondops, RISCV_ISA_EXT_XVENTANACONDOPS),
> };
>
> const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext);
> --
> 2.34.1
>
Besides Conor's comment about splitting the patch,
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Thanks,
drew
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 2/7] RISC-V: Detect Zicond from ISA string
2023-09-19 3:53 ` [PATCH 2/7] RISC-V: Detect Zicond " Anup Patel
2023-09-19 7:27 ` Conor Dooley
@ 2023-09-20 7:44 ` Andrew Jones
2023-09-25 13:31 ` Anup Patel
1 sibling, 1 reply; 24+ messages in thread
From: Andrew Jones @ 2023-09-20 7:44 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Atish Patra, Palmer Dabbelt, Paul Walmsley,
Conor Dooley, Rob Herring, Krzysztof Kozlowski, Shuah Khan,
Mayuresh Chitale, devicetree, kvm, kvm-riscv, linux-riscv,
linux-kernel, linux-kselftest
On Tue, Sep 19, 2023 at 09:23:38AM +0530, Anup Patel wrote:
> The RISC-V integer conditional (Zicond) operation extension defines
> standard conditional arithmetic and conditional-select/move operations
> which are inspired from the XVentanaCondOps extension. In fact, QEMU
> RISC-V also has support for emulating Zicond extension.
>
> Let us detect Zicond extension from ISA string available through
> DT or ACPI.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
> Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
> arch/riscv/include/asm/hwcap.h | 1 +
> arch/riscv/kernel/cpufeature.c | 1 +
> 3 files changed, 8 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index cad8ef68eca7..7ea90e2dbc5b 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -225,6 +225,12 @@ properties:
> ratified in the 20191213 version of the unprivileged ISA
> specification.
>
> + - const: zicond
> + description:
> + The standard Zicond extension for conditional arithmetic and
> + conditional-select/move operations as ratified in commit 8fb6694
> + ("Update Gemfile") of riscv-zicond.
As of yesterday, v1.0 of the spec points at commit 95cf1f9 ("Add changes
requested by Ved during signoff")
> +
> - const: zicsr
> description: |
> The standard Zicsr extension for control and status register
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index b7efe9e2fa89..15bafc02ffd4 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -60,6 +60,7 @@
> #define RISCV_ISA_EXT_ZIHPM 42
> #define RISCV_ISA_EXT_SMSTATEEN 43
> #define RISCV_ISA_EXT_XVENTANACONDOPS 44
> +#define RISCV_ISA_EXT_ZICOND 45
>
> #define RISCV_ISA_EXT_MAX 64
>
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 3a31d34fe709..49b6551f3347 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -174,6 +174,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA),
> __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
> __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS),
> + __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND),
Zi extensions come before Zb extensions.
> __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),
> __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN),
> __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
> --
> 2.34.1
>
Thanks,
drew
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 3/7] RISC-V: KVM: Allow XVentanaCondOps extension for Guest/VM
2023-09-19 3:53 ` [PATCH 3/7] RISC-V: KVM: Allow XVentanaCondOps extension for Guest/VM Anup Patel
@ 2023-09-20 7:46 ` Andrew Jones
0 siblings, 0 replies; 24+ messages in thread
From: Andrew Jones @ 2023-09-20 7:46 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Atish Patra, Palmer Dabbelt, Paul Walmsley,
Conor Dooley, Rob Herring, Krzysztof Kozlowski, Shuah Khan,
Mayuresh Chitale, devicetree, kvm, kvm-riscv, linux-riscv,
linux-kernel, linux-kselftest
On Tue, Sep 19, 2023 at 09:23:39AM +0530, Anup Patel wrote:
> We extend the KVM ISA extension ONE_REG interface to allow KVM
> user space to detect and enable XVentanaCondOps extension for
> Guest/VM.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
> arch/riscv/include/uapi/asm/kvm.h | 1 +
> arch/riscv/kvm/vcpu_onereg.c | 2 ++
> 2 files changed, 3 insertions(+)
>
> diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
> index b1baf6f096a3..e030c12c7dfc 100644
> --- a/arch/riscv/include/uapi/asm/kvm.h
> +++ b/arch/riscv/include/uapi/asm/kvm.h
> @@ -138,6 +138,7 @@ enum KVM_RISCV_ISA_EXT_ID {
> KVM_RISCV_ISA_EXT_ZIFENCEI,
> KVM_RISCV_ISA_EXT_ZIHPM,
> KVM_RISCV_ISA_EXT_SMSTATEEN,
> + KVM_RISCV_ISA_EXT_XVENTANACONDOPS,
> KVM_RISCV_ISA_EXT_MAX,
> };
>
> diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c
> index 388599fcf684..17a847a1114b 100644
> --- a/arch/riscv/kvm/vcpu_onereg.c
> +++ b/arch/riscv/kvm/vcpu_onereg.c
> @@ -40,6 +40,7 @@ static const unsigned long kvm_isa_ext_arr[] = {
> KVM_ISA_EXT_ARR(SVINVAL),
> KVM_ISA_EXT_ARR(SVNAPOT),
> KVM_ISA_EXT_ARR(SVPBMT),
> + KVM_ISA_EXT_ARR(XVENTANACONDOPS),
> KVM_ISA_EXT_ARR(ZBA),
> KVM_ISA_EXT_ARR(ZBB),
> KVM_ISA_EXT_ARR(ZBS),
> @@ -89,6 +90,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext)
> case KVM_RISCV_ISA_EXT_SSTC:
> case KVM_RISCV_ISA_EXT_SVINVAL:
> case KVM_RISCV_ISA_EXT_SVNAPOT:
> + case KVM_RISCV_ISA_EXT_XVENTANACONDOPS:
> case KVM_RISCV_ISA_EXT_ZBA:
> case KVM_RISCV_ISA_EXT_ZBB:
> case KVM_RISCV_ISA_EXT_ZBS:
> --
> 2.34.1
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 4/7] RISC-V: KVM: Allow Zicond extension for Guest/VM
2023-09-19 3:53 ` [PATCH 4/7] RISC-V: KVM: Allow Zicond " Anup Patel
@ 2023-09-20 7:46 ` Andrew Jones
0 siblings, 0 replies; 24+ messages in thread
From: Andrew Jones @ 2023-09-20 7:46 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Atish Patra, Palmer Dabbelt, Paul Walmsley,
Conor Dooley, Rob Herring, Krzysztof Kozlowski, Shuah Khan,
Mayuresh Chitale, devicetree, kvm, kvm-riscv, linux-riscv,
linux-kernel, linux-kselftest
On Tue, Sep 19, 2023 at 09:23:40AM +0530, Anup Patel wrote:
> We extend the KVM ISA extension ONE_REG interface to allow KVM
> user space to detect and enable Zicond extension for Guest/VM.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
> arch/riscv/include/uapi/asm/kvm.h | 1 +
> arch/riscv/kvm/vcpu_onereg.c | 2 ++
> 2 files changed, 3 insertions(+)
>
> diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
> index e030c12c7dfc..35ceb38a4eff 100644
> --- a/arch/riscv/include/uapi/asm/kvm.h
> +++ b/arch/riscv/include/uapi/asm/kvm.h
> @@ -139,6 +139,7 @@ enum KVM_RISCV_ISA_EXT_ID {
> KVM_RISCV_ISA_EXT_ZIHPM,
> KVM_RISCV_ISA_EXT_SMSTATEEN,
> KVM_RISCV_ISA_EXT_XVENTANACONDOPS,
> + KVM_RISCV_ISA_EXT_ZICOND,
> KVM_RISCV_ISA_EXT_MAX,
> };
>
> diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c
> index 17a847a1114b..d3ca4969c985 100644
> --- a/arch/riscv/kvm/vcpu_onereg.c
> +++ b/arch/riscv/kvm/vcpu_onereg.c
> @@ -47,6 +47,7 @@ static const unsigned long kvm_isa_ext_arr[] = {
> KVM_ISA_EXT_ARR(ZICBOM),
> KVM_ISA_EXT_ARR(ZICBOZ),
> KVM_ISA_EXT_ARR(ZICNTR),
> + KVM_ISA_EXT_ARR(ZICOND),
> KVM_ISA_EXT_ARR(ZICSR),
> KVM_ISA_EXT_ARR(ZIFENCEI),
> KVM_ISA_EXT_ARR(ZIHINTPAUSE),
> @@ -95,6 +96,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext)
> case KVM_RISCV_ISA_EXT_ZBB:
> case KVM_RISCV_ISA_EXT_ZBS:
> case KVM_RISCV_ISA_EXT_ZICNTR:
> + case KVM_RISCV_ISA_EXT_ZICOND:
> case KVM_RISCV_ISA_EXT_ZICSR:
> case KVM_RISCV_ISA_EXT_ZIFENCEI:
> case KVM_RISCV_ISA_EXT_ZIHINTPAUSE:
> --
> 2.34.1
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 5/7] KVM: riscv: selftests: Add senvcfg register to get-reg-list test
2023-09-19 3:53 ` [PATCH 5/7] KVM: riscv: selftests: Add senvcfg register to get-reg-list test Anup Patel
@ 2023-09-20 7:50 ` Andrew Jones
0 siblings, 0 replies; 24+ messages in thread
From: Andrew Jones @ 2023-09-20 7:50 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Atish Patra, Palmer Dabbelt, Paul Walmsley,
Conor Dooley, Rob Herring, Krzysztof Kozlowski, Shuah Khan,
Mayuresh Chitale, devicetree, kvm, kvm-riscv, linux-riscv,
linux-kernel, linux-kselftest
On Tue, Sep 19, 2023 at 09:23:41AM +0530, Anup Patel wrote:
> We have a new senvcfg register in the general CSR ONE_REG interface
> so let us add it to get-reg-list test.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
> tools/testing/selftests/kvm/riscv/get-reg-list.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c
> index 85907c86b835..0928c35470ae 100644
> --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c
> +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c
> @@ -209,6 +209,8 @@ static const char *general_csr_id_to_str(__u64 reg_off)
> return RISCV_CSR_GENERAL(satp);
> case KVM_REG_RISCV_CSR_REG(scounteren):
> return RISCV_CSR_GENERAL(scounteren);
> + case KVM_REG_RISCV_CSR_REG(senvcfg):
> + return RISCV_CSR_GENERAL(senvcfg);
> }
>
> TEST_FAIL("Unknown general csr reg: 0x%llx", reg_off);
> @@ -532,6 +534,7 @@ static __u64 base_regs[] = {
> KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(sip),
> KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(satp),
> KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(scounteren),
> + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(senvcfg),
> KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(frequency),
> KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(time),
> KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(compare),
> --
> 2.34.1
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 6/7] KVM: riscv: selftests: Add smstateen registers to get-reg-list test
2023-09-19 3:53 ` [PATCH 6/7] KVM: riscv: selftests: Add smstateen registers " Anup Patel
@ 2023-09-20 8:13 ` Andrew Jones
0 siblings, 0 replies; 24+ messages in thread
From: Andrew Jones @ 2023-09-20 8:13 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Atish Patra, Palmer Dabbelt, Paul Walmsley,
Conor Dooley, Rob Herring, Krzysztof Kozlowski, Shuah Khan,
Mayuresh Chitale, devicetree, kvm, kvm-riscv, linux-riscv,
linux-kernel, linux-kselftest
On Tue, Sep 19, 2023 at 09:23:42AM +0530, Anup Patel wrote:
> We have a new smstateen registers as separate sub-type of CSR ONE_REG
> interface so let us add these registers to get-reg-list test.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
> .../selftests/kvm/riscv/get-reg-list.c | 34 +++++++++++++++++++
> 1 file changed, 34 insertions(+)
>
> diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c
> index 0928c35470ae..9f464c7996c6 100644
> --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c
> +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c
> @@ -49,6 +49,7 @@ bool filter_reg(__u64 reg)
> case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICSR:
> case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIFENCEI:
> case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHPM:
> + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SMSTATEEN:
> return true;
> /* AIA registers are always available when Ssaia can't be disabled */
> case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siselect):
> @@ -184,6 +185,8 @@ static const char *core_id_to_str(const char *prefix, __u64 id)
> "KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(" #csr ")"
> #define RISCV_CSR_AIA(csr) \
> "KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_REG(" #csr ")"
> +#define RISCV_CSR_SMSTATEEN(csr) \
> + "KVM_REG_RISCV_CSR_SMSTATEEN | KVM_REG_RISCV_CSR_REG(" #csr ")"
>
> static const char *general_csr_id_to_str(__u64 reg_off)
> {
> @@ -241,6 +244,18 @@ static const char *aia_csr_id_to_str(__u64 reg_off)
> return NULL;
> }
>
> +static const char *smstateen_csr_id_to_str(__u64 reg_off)
> +{
> + /* reg_off is the offset into struct kvm_riscv_smstateen_csr */
> + switch (reg_off) {
> + case KVM_REG_RISCV_CSR_SMSTATEEN_REG(sstateen0):
> + return RISCV_CSR_SMSTATEEN(sstateen0);
> + }
> +
> + TEST_FAIL("Unknown smstateen csr reg: 0x%llx", reg_off);
> + return NULL;
> +}
> +
> static const char *csr_id_to_str(const char *prefix, __u64 id)
> {
> __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CSR);
> @@ -253,6 +268,8 @@ static const char *csr_id_to_str(const char *prefix, __u64 id)
> return general_csr_id_to_str(reg_off);
> case KVM_REG_RISCV_CSR_AIA:
> return aia_csr_id_to_str(reg_off);
> + case KVM_REG_RISCV_CSR_SMSTATEEN:
> + return smstateen_csr_id_to_str(reg_off);
> }
>
> TEST_FAIL("%s: Unknown csr subtype: 0x%llx", prefix, reg_subtype);
> @@ -342,6 +359,7 @@ static const char *isa_ext_id_to_str(__u64 id)
> "KVM_RISCV_ISA_EXT_ZICSR",
> "KVM_RISCV_ISA_EXT_ZIFENCEI",
> "KVM_RISCV_ISA_EXT_ZIHPM",
> + "KVM_RISCV_ISA_EXT_SMSTATEEN",
If we merge [1] first, then this would be added in alphabetical order.
[1] https://lore.kernel.org/all/20230817162344.17076-6-ajones@ventanamicro.com/
> };
>
> if (reg_off >= ARRAY_SIZE(kvm_isa_ext_reg_name)) {
> @@ -629,6 +647,11 @@ static __u64 aia_regs[] = {
> KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSAIA,
> };
>
> +static __u64 smstateen_regs[] = {
> + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_SMSTATEEN | KVM_REG_RISCV_CSR_SMSTATEEN_REG(sstateen0),
> + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SMSTATEEN,
> +};
> +
> static __u64 fp_f_regs[] = {
> KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[0]),
> KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[1]),
> @@ -736,6 +759,8 @@ static __u64 fp_d_regs[] = {
> {"zihpm", .feature = KVM_RISCV_ISA_EXT_ZIHPM, .regs = zihpm_regs, .regs_n = ARRAY_SIZE(zihpm_regs),}
> #define AIA_REGS_SUBLIST \
> {"aia", .feature = KVM_RISCV_ISA_EXT_SSAIA, .regs = aia_regs, .regs_n = ARRAY_SIZE(aia_regs),}
> +#define SMSTATEEN_REGS_SUBLIST \
> + {"smstateen", .feature = KVM_RISCV_ISA_EXT_SMSTATEEN, .regs = smstateen_regs, .regs_n = ARRAY_SIZE(smstateen_regs),}
> #define FP_F_REGS_SUBLIST \
> {"fp_f", .feature = KVM_RISCV_ISA_EXT_F, .regs = fp_f_regs, \
> .regs_n = ARRAY_SIZE(fp_f_regs),}
> @@ -863,6 +888,14 @@ static struct vcpu_reg_list aia_config = {
> },
> };
>
> +static struct vcpu_reg_list smstateen_config = {
> + .sublists = {
> + BASE_SUBLIST,
> + SMSTATEEN_REGS_SUBLIST,
> + {0},
> + },
> +};
> +
> static struct vcpu_reg_list fp_f_config = {
> .sublists = {
> BASE_SUBLIST,
> @@ -895,6 +928,7 @@ struct vcpu_reg_list *vcpu_configs[] = {
> &zifencei_config,
> &zihpm_config,
> &aia_config,
> + &smstateen_config,
> &fp_f_config,
> &fp_d_config,
> };
> --
> 2.34.1
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Thanks,
drew
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 7/7] KVM: riscv: selftests: Add condops extensions to get-reg-list test
2023-09-19 3:53 ` [PATCH 7/7] KVM: riscv: selftests: Add condops extensions " Anup Patel
@ 2023-09-20 8:18 ` Andrew Jones
2023-09-25 13:32 ` Anup Patel
0 siblings, 1 reply; 24+ messages in thread
From: Andrew Jones @ 2023-09-20 8:18 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Atish Patra, Palmer Dabbelt, Paul Walmsley,
Conor Dooley, Rob Herring, Krzysztof Kozlowski, Shuah Khan,
Mayuresh Chitale, devicetree, kvm, kvm-riscv, linux-riscv,
linux-kernel, linux-kselftest
On Tue, Sep 19, 2023 at 09:23:43AM +0530, Anup Patel wrote:
> We have a new conditional operations related ISA extensions so let us add
> these extensions to get-reg-list test.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
> tools/testing/selftests/kvm/riscv/get-reg-list.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c
> index 9f464c7996c6..4ad4bf87fa78 100644
> --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c
> +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c
> @@ -50,6 +50,8 @@ bool filter_reg(__u64 reg)
> case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIFENCEI:
> case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHPM:
> case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SMSTATEEN:
> + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_XVENTANACONDOPS:
> + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICOND:
> return true;
> /* AIA registers are always available when Ssaia can't be disabled */
> case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siselect):
> @@ -360,6 +362,8 @@ static const char *isa_ext_id_to_str(__u64 id)
> "KVM_RISCV_ISA_EXT_ZIFENCEI",
> "KVM_RISCV_ISA_EXT_ZIHPM",
> "KVM_RISCV_ISA_EXT_SMSTATEEN",
> + "KVM_RISCV_ISA_EXT_XVENTANACONDOPS",
> + "KVM_RISCV_ISA_EXT_ZICOND",
> };
>
> if (reg_off >= ARRAY_SIZE(kvm_isa_ext_reg_name)) {
> --
> 2.34.1
>
Don't we want to add test configs for these?
Thanks,
drew
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 1/7] RISC-V: Detect XVentanaCondOps from ISA string
2023-09-19 7:26 ` Conor Dooley
@ 2023-09-25 13:30 ` Anup Patel
0 siblings, 0 replies; 24+ messages in thread
From: Anup Patel @ 2023-09-25 13:30 UTC (permalink / raw)
To: Conor Dooley
Cc: Paolo Bonzini, Atish Patra, Palmer Dabbelt, Paul Walmsley,
Rob Herring, Krzysztof Kozlowski, Shuah Khan, Andrew Jones,
Mayuresh Chitale, devicetree, kvm, kvm-riscv, linux-riscv,
linux-kernel, linux-kselftest
On Tue, Sep 19, 2023 at 12:56 PM Conor Dooley <conor@kernel.org> wrote:
>
> Hey Anup,
>
> On Tue, Sep 19, 2023 at 09:23:37AM +0530, Anup Patel wrote:
> > The Veyron-V1 CPU supports custom conditional arithmetic and
> > conditional-select/move operations referred to as XVentanaCondOps
> > extension. In fact, QEMU RISC-V also has support for emulating
> > XVentanaCondOps extension.
> >
> > Let us detect XVentanaCondOps extension from ISA string available
> > through DT or ACPI.
> >
> > Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> > ---
> > Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++
> > arch/riscv/include/asm/hwcap.h | 1 +
> > arch/riscv/kernel/cpufeature.c | 1 +
> > 3 files changed, 9 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > index 36ff6749fbba..cad8ef68eca7 100644
> > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > @@ -171,6 +171,13 @@ properties:
> > memory types as ratified in the 20191213 version of the privileged
> > ISA specification.
> >
> > + - const: xventanacondops
> > + description: |
> > + The Ventana specific XVentanaCondOps extension for conditional
> > + arithmetic and conditional-select/move operations defined by the
> > + Ventana custom extensions specification v1.0.1 (or higher) at
> > + https://github.com/ventanamicro/ventana-custom-extensions/releases.
> > +
>
> For this and the next patch, the binding change needs to be split out
> from the code. checkpatch should've complained about it.
Okay, I will split this patch.
>
> > - const: zba
> > description: |
> > The standard Zba bit-manipulation extension for address generation
> > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> > index 0f520f7d058a..b7efe9e2fa89 100644
> > --- a/arch/riscv/include/asm/hwcap.h
> > +++ b/arch/riscv/include/asm/hwcap.h
> > @@ -59,6 +59,7 @@
> > #define RISCV_ISA_EXT_ZIFENCEI 41
> > #define RISCV_ISA_EXT_ZIHPM 42
> > #define RISCV_ISA_EXT_SMSTATEEN 43
> > +#define RISCV_ISA_EXT_XVENTANACONDOPS 44
> >
> > #define RISCV_ISA_EXT_MAX 64
> >
> > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > index 3755a8c2a9de..3a31d34fe709 100644
> > --- a/arch/riscv/kernel/cpufeature.c
> > +++ b/arch/riscv/kernel/cpufeature.c
> > @@ -182,6 +182,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> > __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
> > __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
> > __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
> > + __RISCV_ISA_EXT_DATA(xventanacondops, RISCV_ISA_EXT_XVENTANACONDOPS),
>
> I've been banging on for a bit about people doing weird stuff to detect
> their vendor extensions, so nice to see it being done properly :)
>
>
> Cheers,
> Conor.
>
> > };
> >
> > const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext);
> > --
> > 2.34.1
> >
Regards,
Anup
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 2/7] RISC-V: Detect Zicond from ISA string
2023-09-19 7:27 ` Conor Dooley
@ 2023-09-25 13:31 ` Anup Patel
0 siblings, 0 replies; 24+ messages in thread
From: Anup Patel @ 2023-09-25 13:31 UTC (permalink / raw)
To: Conor Dooley
Cc: Paolo Bonzini, Atish Patra, Palmer Dabbelt, Paul Walmsley,
Rob Herring, Krzysztof Kozlowski, Shuah Khan, Andrew Jones,
Mayuresh Chitale, devicetree, kvm, kvm-riscv, linux-riscv,
linux-kernel, linux-kselftest
On Tue, Sep 19, 2023 at 12:57 PM Conor Dooley <conor@kernel.org> wrote:
>
> On Tue, Sep 19, 2023 at 09:23:38AM +0530, Anup Patel wrote:
> > The RISC-V integer conditional (Zicond) operation extension defines
> > standard conditional arithmetic and conditional-select/move operations
> > which are inspired from the XVentanaCondOps extension. In fact, QEMU
> > RISC-V also has support for emulating Zicond extension.
> >
> > Let us detect Zicond extension from ISA string available through
> > DT or ACPI.
> >
> > Signed-off-by: Anup Patel <apatel@ventanamicro.com>
>
> Same applies here w.r.t. splitting in two.
Okay, I will update.
Regards,
Anup
>
> Thanks,
> Conor.
>
> > ---
> > Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
> > arch/riscv/include/asm/hwcap.h | 1 +
> > arch/riscv/kernel/cpufeature.c | 1 +
> > 3 files changed, 8 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > index cad8ef68eca7..7ea90e2dbc5b 100644
> > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > @@ -225,6 +225,12 @@ properties:
> > ratified in the 20191213 version of the unprivileged ISA
> > specification.
> >
> > + - const: zicond
> > + description:
> > + The standard Zicond extension for conditional arithmetic and
> > + conditional-select/move operations as ratified in commit 8fb6694
> > + ("Update Gemfile") of riscv-zicond.
> > +
> > - const: zicsr
> > description: |
> > The standard Zicsr extension for control and status register
> > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> > index b7efe9e2fa89..15bafc02ffd4 100644
> > --- a/arch/riscv/include/asm/hwcap.h
> > +++ b/arch/riscv/include/asm/hwcap.h
> > @@ -60,6 +60,7 @@
> > #define RISCV_ISA_EXT_ZIHPM 42
> > #define RISCV_ISA_EXT_SMSTATEEN 43
> > #define RISCV_ISA_EXT_XVENTANACONDOPS 44
> > +#define RISCV_ISA_EXT_ZICOND 45
> >
> > #define RISCV_ISA_EXT_MAX 64
> >
> > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > index 3a31d34fe709..49b6551f3347 100644
> > --- a/arch/riscv/kernel/cpufeature.c
> > +++ b/arch/riscv/kernel/cpufeature.c
> > @@ -174,6 +174,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> > __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA),
> > __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
> > __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS),
> > + __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND),
> > __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),
> > __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN),
> > __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
> > --
> > 2.34.1
> >
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 2/7] RISC-V: Detect Zicond from ISA string
2023-09-20 7:44 ` Andrew Jones
@ 2023-09-25 13:31 ` Anup Patel
0 siblings, 0 replies; 24+ messages in thread
From: Anup Patel @ 2023-09-25 13:31 UTC (permalink / raw)
To: Andrew Jones
Cc: Paolo Bonzini, Atish Patra, Palmer Dabbelt, Paul Walmsley,
Conor Dooley, Rob Herring, Krzysztof Kozlowski, Shuah Khan,
Mayuresh Chitale, devicetree, kvm, kvm-riscv, linux-riscv,
linux-kernel, linux-kselftest
On Wed, Sep 20, 2023 at 1:14 PM Andrew Jones <ajones@ventanamicro.com> wrote:
>
> On Tue, Sep 19, 2023 at 09:23:38AM +0530, Anup Patel wrote:
> > The RISC-V integer conditional (Zicond) operation extension defines
> > standard conditional arithmetic and conditional-select/move operations
> > which are inspired from the XVentanaCondOps extension. In fact, QEMU
> > RISC-V also has support for emulating Zicond extension.
> >
> > Let us detect Zicond extension from ISA string available through
> > DT or ACPI.
> >
> > Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> > ---
> > Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
> > arch/riscv/include/asm/hwcap.h | 1 +
> > arch/riscv/kernel/cpufeature.c | 1 +
> > 3 files changed, 8 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > index cad8ef68eca7..7ea90e2dbc5b 100644
> > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > @@ -225,6 +225,12 @@ properties:
> > ratified in the 20191213 version of the unprivileged ISA
> > specification.
> >
> > + - const: zicond
> > + description:
> > + The standard Zicond extension for conditional arithmetic and
> > + conditional-select/move operations as ratified in commit 8fb6694
> > + ("Update Gemfile") of riscv-zicond.
>
> As of yesterday, v1.0 of the spec points at commit 95cf1f9 ("Add changes
> requested by Ved during signoff")
Okay, I will update.
>
> > +
> > - const: zicsr
> > description: |
> > The standard Zicsr extension for control and status register
> > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> > index b7efe9e2fa89..15bafc02ffd4 100644
> > --- a/arch/riscv/include/asm/hwcap.h
> > +++ b/arch/riscv/include/asm/hwcap.h
> > @@ -60,6 +60,7 @@
> > #define RISCV_ISA_EXT_ZIHPM 42
> > #define RISCV_ISA_EXT_SMSTATEEN 43
> > #define RISCV_ISA_EXT_XVENTANACONDOPS 44
> > +#define RISCV_ISA_EXT_ZICOND 45
> >
> > #define RISCV_ISA_EXT_MAX 64
> >
> > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > index 3a31d34fe709..49b6551f3347 100644
> > --- a/arch/riscv/kernel/cpufeature.c
> > +++ b/arch/riscv/kernel/cpufeature.c
> > @@ -174,6 +174,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> > __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA),
> > __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
> > __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS),
> > + __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND),
>
> Zi extensions come before Zb extensions.
Okay, I will update.
>
> > __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),
> > __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN),
> > __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
> > --
> > 2.34.1
> >
>
> Thanks,
> drew
Regards,
Anup
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 7/7] KVM: riscv: selftests: Add condops extensions to get-reg-list test
2023-09-20 8:18 ` Andrew Jones
@ 2023-09-25 13:32 ` Anup Patel
0 siblings, 0 replies; 24+ messages in thread
From: Anup Patel @ 2023-09-25 13:32 UTC (permalink / raw)
To: Andrew Jones
Cc: Paolo Bonzini, Atish Patra, Palmer Dabbelt, Paul Walmsley,
Conor Dooley, Rob Herring, Krzysztof Kozlowski, Shuah Khan,
Mayuresh Chitale, devicetree, kvm, kvm-riscv, linux-riscv,
linux-kernel, linux-kselftest
On Wed, Sep 20, 2023 at 1:48 PM Andrew Jones <ajones@ventanamicro.com> wrote:
>
> On Tue, Sep 19, 2023 at 09:23:43AM +0530, Anup Patel wrote:
> > We have a new conditional operations related ISA extensions so let us add
> > these extensions to get-reg-list test.
> >
> > Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> > ---
> > tools/testing/selftests/kvm/riscv/get-reg-list.c | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c
> > index 9f464c7996c6..4ad4bf87fa78 100644
> > --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c
> > +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c
> > @@ -50,6 +50,8 @@ bool filter_reg(__u64 reg)
> > case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIFENCEI:
> > case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHPM:
> > case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SMSTATEEN:
> > + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_XVENTANACONDOPS:
> > + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICOND:
> > return true;
> > /* AIA registers are always available when Ssaia can't be disabled */
> > case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siselect):
> > @@ -360,6 +362,8 @@ static const char *isa_ext_id_to_str(__u64 id)
> > "KVM_RISCV_ISA_EXT_ZIFENCEI",
> > "KVM_RISCV_ISA_EXT_ZIHPM",
> > "KVM_RISCV_ISA_EXT_SMSTATEEN",
> > + "KVM_RISCV_ISA_EXT_XVENTANACONDOPS",
> > + "KVM_RISCV_ISA_EXT_ZICOND",
> > };
> >
> > if (reg_off >= ARRAY_SIZE(kvm_isa_ext_reg_name)) {
> > --
> > 2.34.1
> >
>
> Don't we want to add test configs for these?
Okay, I will update.
Regards,
Anup
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 1/7] RISC-V: Detect XVentanaCondOps from ISA string
2023-09-19 3:53 ` [PATCH 1/7] RISC-V: Detect XVentanaCondOps from ISA string Anup Patel
2023-09-19 7:26 ` Conor Dooley
2023-09-20 7:38 ` Andrew Jones
@ 2023-10-02 6:27 ` Christoph Hellwig
2023-10-02 15:36 ` Anup Patel
2 siblings, 1 reply; 24+ messages in thread
From: Christoph Hellwig @ 2023-10-02 6:27 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Atish Patra, Palmer Dabbelt, Paul Walmsley,
Conor Dooley, Rob Herring, Krzysztof Kozlowski, Shuah Khan,
Andrew Jones, Mayuresh Chitale, devicetree, kvm, kvm-riscv,
linux-riscv, linux-kernel, linux-kselftest
On Tue, Sep 19, 2023 at 09:23:37AM +0530, Anup Patel wrote:
> The Veyron-V1 CPU supports custom conditional arithmetic and
> conditional-select/move operations referred to as XVentanaCondOps
> extension. In fact, QEMU RISC-V also has support for emulating
> XVentanaCondOps extension.
>
> Let us detect XVentanaCondOps extension from ISA string available
> through DT or ACPI.
Umm, I though Linux/riscv would never support vendor specific
extensions?
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 1/7] RISC-V: Detect XVentanaCondOps from ISA string
2023-10-02 6:27 ` Christoph Hellwig
@ 2023-10-02 15:36 ` Anup Patel
2023-10-05 6:49 ` Christoph Hellwig
0 siblings, 1 reply; 24+ messages in thread
From: Anup Patel @ 2023-10-02 15:36 UTC (permalink / raw)
To: Christoph Hellwig
Cc: Paolo Bonzini, Atish Patra, Palmer Dabbelt, Paul Walmsley,
Conor Dooley, Rob Herring, Krzysztof Kozlowski, Shuah Khan,
Andrew Jones, Mayuresh Chitale, devicetree, kvm, kvm-riscv,
linux-riscv, linux-kernel, linux-kselftest
On Mon, Oct 2, 2023 at 11:57 AM Christoph Hellwig <hch@infradead.org> wrote:
>
> On Tue, Sep 19, 2023 at 09:23:37AM +0530, Anup Patel wrote:
> > The Veyron-V1 CPU supports custom conditional arithmetic and
> > conditional-select/move operations referred to as XVentanaCondOps
> > extension. In fact, QEMU RISC-V also has support for emulating
> > XVentanaCondOps extension.
> >
> > Let us detect XVentanaCondOps extension from ISA string available
> > through DT or ACPI.
>
> Umm, I though Linux/riscv would never support vendor specific
> extensions?
>
We already have few T-Head specific extensions so Linux RISC-V
does allow vendor extensions.
Regards,
Anup
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 1/7] RISC-V: Detect XVentanaCondOps from ISA string
2023-10-02 15:36 ` Anup Patel
@ 2023-10-05 6:49 ` Christoph Hellwig
0 siblings, 0 replies; 24+ messages in thread
From: Christoph Hellwig @ 2023-10-05 6:49 UTC (permalink / raw)
To: Anup Patel
Cc: Christoph Hellwig, Paolo Bonzini, Atish Patra, Palmer Dabbelt,
Paul Walmsley, Conor Dooley, Rob Herring, Krzysztof Kozlowski,
Shuah Khan, Andrew Jones, Mayuresh Chitale, devicetree, kvm,
kvm-riscv, linux-riscv, linux-kernel, linux-kselftest
On Mon, Oct 02, 2023 at 09:06:08PM +0530, Anup Patel wrote:
> > extensions?
> >
>
> We already have few T-Head specific extensions so Linux RISC-V
> does allow vendor extensions.
Only for kernel internal operation and to actually boot the
chip. IMHO still the wrong tradeoff, but very different from actually
user visible extensions that will lead to fragmentation of the
ecoysystem.
^ permalink raw reply [flat|nested] 24+ messages in thread
end of thread, other threads:[~2023-10-05 14:26 UTC | newest]
Thread overview: 24+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-09-19 3:53 [PATCH 0/7] KVM RISC-V Conditional Operations Anup Patel
2023-09-19 3:53 ` [PATCH 1/7] RISC-V: Detect XVentanaCondOps from ISA string Anup Patel
2023-09-19 7:26 ` Conor Dooley
2023-09-25 13:30 ` Anup Patel
2023-09-20 7:38 ` Andrew Jones
2023-10-02 6:27 ` Christoph Hellwig
2023-10-02 15:36 ` Anup Patel
2023-10-05 6:49 ` Christoph Hellwig
2023-09-19 3:53 ` [PATCH 2/7] RISC-V: Detect Zicond " Anup Patel
2023-09-19 7:27 ` Conor Dooley
2023-09-25 13:31 ` Anup Patel
2023-09-20 7:44 ` Andrew Jones
2023-09-25 13:31 ` Anup Patel
2023-09-19 3:53 ` [PATCH 3/7] RISC-V: KVM: Allow XVentanaCondOps extension for Guest/VM Anup Patel
2023-09-20 7:46 ` Andrew Jones
2023-09-19 3:53 ` [PATCH 4/7] RISC-V: KVM: Allow Zicond " Anup Patel
2023-09-20 7:46 ` Andrew Jones
2023-09-19 3:53 ` [PATCH 5/7] KVM: riscv: selftests: Add senvcfg register to get-reg-list test Anup Patel
2023-09-20 7:50 ` Andrew Jones
2023-09-19 3:53 ` [PATCH 6/7] KVM: riscv: selftests: Add smstateen registers " Anup Patel
2023-09-20 8:13 ` Andrew Jones
2023-09-19 3:53 ` [PATCH 7/7] KVM: riscv: selftests: Add condops extensions " Anup Patel
2023-09-20 8:18 ` Andrew Jones
2023-09-25 13:32 ` Anup Patel
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