From: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
To: patrick@stwcx.xyz, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>, Joel Stanley <joel@jms.id.au>,
Andrew Jeffery <andrew@codeconstruct.com.au>
Cc: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org
Subject: [PATCH v2 10/14] ARM: dts: aspeed: yosemite4: Initialize bmc gpio state
Date: Mon, 11 Dec 2023 10:49:41 +0800 [thread overview]
Message-ID: <20231211024947.3990898-11-Delphine_CC_Chiu@wiwynn.com> (raw)
In-Reply-To: <20231211024947.3990898-1-Delphine_CC_Chiu@wiwynn.com>
Initialize bmc gpio state
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
.../aspeed/aspeed-bmc-facebook-yosemite4.dts | 195 ++++++++++++++++++
1 file changed, 195 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index ed2b1200603d..eb3687bfd632 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -1271,6 +1271,7 @@ temperature-sensor@1f {
};
};
+
&adc0 {
ref_voltage = <2500>;
status = "okay";
@@ -1298,3 +1299,197 @@ &ehci1 {
&uhci {
status = "okay";
};
+
+&sgpiom0 {
+ status = "okay";
+ ngpios = <128>;
+ bus-frequency = <48000>;
+};
+
+&gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpiu2_default &pinctrl_gpiu3_default
+ &pinctrl_gpiu4_default &pinctrl_gpiu5_default
+ &pinctrl_gpiu6_default>;
+ gpio-line-names =
+ /*A0-A7*/ "","","","","","","","",
+ /*B0-B7*/ "FLT_HSC_SERVER_SLOT8_N","AC_ON_OFF_BTN_CPLD_SLOT5_N",
+ "PWRGD_SLOT1_STBY","PWRGD_SLOT2_STBY",
+ "PWRGD_SLOT3_STBY","PWRGD_SLOT4_STBY","","",
+ /*C0-C7*/ "PRSNT_NIC3_N","","","","FM_NIC0_WAKE_N",
+ "FM_NIC1_WAKE_N","","RST_PCIE_SLOT2_N",
+ /*D0-D7*/ "","","","","","","","",
+ /*E0-E7*/ "PRSNT_NIC1_N","PRSNT_NIC2_N","","RST_PCIE_SLOT1_N",
+ "","","","",
+ /*F0-F7*/ "FM_RESBTN_SLOT1_BMC_N","FM_RESBTN_SLOT2_BMC_N",
+ "FM_RESBTN_SLOT3_BMC_N","FM_RESBTN_SLOT4_BMC_N",
+ "PRSNT_SB_SLOT1_N","PRSNT_SB_SLOT2_N",
+ "PRSNT_SB_SLOT3_N","PRSNT_SB_SLOT4_N",
+ /*G0-G7*/ "","","","","","","","",
+ /*H0-H7*/ "","","","","","","","",
+ /*I0-I7*/ "","","","","","ALT_MEDUSA_ADC_N",
+ "ALT_SMB_BMC_CPLD2_N",
+ "INT_SPIDER_ADC_R_N",
+ /*J0-J7*/ "","","","","","","","",
+ /*K0-K7*/ "","","","","","","","",
+ /*L0-L7*/ "","","","","","","ALT_MEDUSA_P12V_EFUSE_N","",
+ /*M0-M7*/ "EN_NIC0_POWER_BMC_R","EN_NIC1_POWER_BMC_R",
+ "INT_MEDUSA_IOEXP_TEMP_N","FLT_P12V_NIC0_N",
+ "INT_SMB_BMC_SLOT1_4_BMC_N",
+ "AC_ON_OFF_BTN_CPLD_SLOT6_N","","",
+ /*N0-N7*/ "FLT_HSC_SERVER_SLOT1_N","FLT_HSC_SERVER_SLOT2_N",
+ "FLT_HSC_SERVER_SLOT3_N","FLT_HSC_SERVER_SLOT4_N",
+ "FM_BMC_READY_R2","FLT_P12V_STBY_BMC_N","","",
+ /*O0-O7*/ "AC_ON_OFF_BTN_CPLD_SLOT8_N","RST_SMB_NIC1_R_N",
+ "RST_SMB_NIC2_R_N","RST_SMB_NIC3_R_N",
+ "FLT_P3V3_NIC2_N","FLT_P3V3_NIC3_N",
+ "","",
+ /*P0-P7*/ "ALT_SMB_BMC_CPLD1_N","'BTN_BMC_R2_N",
+ "EN_P3V_BAT_SCALED_R","PWRGD_P5V_USB_BMC",
+ "FM_BMC_RTCRST_R","RST_USB_HUB_R_N",
+ "FLAG_P5V_USB_BMC_N","",
+ /*Q0-Q7*/ "AC_ON_OFF_BTN_CPLD_SLOT1_N","AC_ON_OFF_BTN_CPLD_SLOT2_N",
+ "AC_ON_OFF_BTN_CPLD_SLOT3_N","AC_ON_OFF_BTN_CPLD_SLOT4_N",
+ "PRSNT_SB_SLOT5_N","PRSNT_SB_SLOT6_N",
+ "PRSNT_SB_SLOT7_N","PRSNT_SB_SLOT8_N",
+ /*R0-R7*/ "AC_ON_OFF_BTN_CPLD_SLOT7_N","INT_SMB_BMC_SLOT5_8_BMC_N",
+ "FM_PWRBRK_NIC_BMC_R2","RST_PCIE_SLOT4_N",
+ "RST_PCIE_SLOT5_N","RST_PCIE_SLOT6_N",
+ "RST_PCIE_SLOT7_N","RST_PCIE_SLOT8_N",
+ /*S0-S7*/ "FM_NIC2_WAKE_N","FM_NIC3_WAKE_N",
+ "EN_NIC3_POWER_BMC_R","SEL_BMC_JTAG_MUX_R",
+ "","ALT_P12V_AUX_N","FAST_PROCHOT_N",
+ "SPI_WP_DISABLE_STATUS_R_N",
+ /*T0-T7*/ "","","","","","","","",
+ /*U0-U7*/ "","","FLT_P3V3_NIC1_N","FLT_P12V_NIC1_N",
+ "FLT_P12V_NIC2_N","FLT_P12V_NIC3_N",
+ "FLT_P3V3_NIC0_N","",
+ /*V0-V7*/ "FM_RESBTN_SLOT5_BMC_N","FM_RESBTN_SLOT6_BMC_N",
+ "FM_RESBTN_SLOT7_BMC_N","FM_RESBTN_SLOT8_BMC_N",
+ "","","","",
+ /*W0-W7*/ "PRSNT_TPM_BMC_N","PRSNT_OCP_DEBUG_BMC_N","ALT_TEMP_BMC_N","ALT_RTC_BMC_N",
+ "","","","",
+ /*X0-X7*/ "","LT_HSC_SERVER_SLOT6_N","FLT_HSC_SERVER_SLOT7_N","","","",
+ "PWRGD_SLOT5_STBY","PWRGD_SLOT6_STBY",
+ /*Y0-Y7*/ "","","SPI_LOCK_REQ_BMC_N","PWRGD_SLOT7_STBY",
+ "","","EN_NIC2_POWER_BMC_R","",
+ /*Z0-Z7*/ "EN_P5V_USB_CPLD_R","'FLT_HSC_SERVER_SLOT5_N",
+ "PWRGD_SLOT8_STBY","","","","","";
+
+ pin_gpio_b4 {
+ gpios = <ASPEED_GPIO(B, 4) GPIO_ACTIVE_HIGH>;
+ input;
+ };
+ pin_gpio_b5 {
+ gpios = <ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>;
+ input;
+ };
+ pin_gpio_f0 {
+ gpios = <ASPEED_GPIO(F, 0) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_f1 {
+ gpios = <ASPEED_GPIO(F, 1) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_f2 {
+ gpios = <ASPEED_GPIO(F, 2) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_f3 {
+ gpios = <ASPEED_GPIO(F, 3) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_f4 {
+ gpios = <ASPEED_GPIO(F, 4) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_f5 {
+ gpios = <ASPEED_GPIO(F, 5) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_f6 {
+ gpios = <ASPEED_GPIO(F, 6) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_f7 {
+ gpios = <ASPEED_GPIO(F, 7) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_l6 {
+ gpios = <ASPEED_GPIO(L, 6) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_l7 {
+ gpios = <ASPEED_GPIO(L, 7) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_s0 {
+ gpios = <ASPEED_GPIO(S, 0) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_s1 {
+ gpios = <ASPEED_GPIO(S, 1) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_v0 {
+ gpios = <ASPEED_GPIO(V, 0) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_v1 {
+ gpios = <ASPEED_GPIO(V, 1) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_v2 {
+ gpios = <ASPEED_GPIO(V, 2) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_v3 {
+ gpios = <ASPEED_GPIO(V, 3) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_w0 {
+ gpios = <ASPEED_GPIO(W, 0) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_w1 {
+ gpios = <ASPEED_GPIO(W, 1) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_w2 {
+ gpios = <ASPEED_GPIO(W, 2) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_w3 {
+ gpios = <ASPEED_GPIO(W, 3) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_w4 {
+ gpios = <ASPEED_GPIO(W, 4) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_w5 {
+ gpios = <ASPEED_GPIO(W, 5) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_w6 {
+ gpios = <ASPEED_GPIO(W, 6) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_w7 {
+ gpios = <ASPEED_GPIO(W, 7) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_z3 {
+ gpios = <ASPEED_GPIO(Z, 3) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_z4 {
+ gpios = <ASPEED_GPIO(Z, 4) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_z5 {
+ gpios = <ASPEED_GPIO(Z, 5) GPIO_ACTIVE_LOW>;
+ input;
+ };
+};
--
2.25.1
next prev parent reply other threads:[~2023-12-11 2:51 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-11 2:49 [PATCH v2 00/14] Add i2c-mux and eeprom devices for Meta Yosemite 4 Delphine CC Chiu
2023-12-11 2:49 ` [PATCH v2 01/14] ARM: dts: aspeed: yosemite4: Revise i2c-mux devices Delphine CC Chiu
2023-12-11 2:49 ` [PATCH v2 02/14] ARM: dts: aspeed: yosemite4: Enable adc15 Delphine CC Chiu
2023-12-11 2:49 ` [PATCH v2 03/14] ARM: dts: aspeed: yosemite4: Enable spi-gpio setting Delphine CC Chiu
2023-12-11 2:49 ` [PATCH v2 04/14] ARM: dts: aspeed: yosemite4: Enable watchdog2 Delphine CC Chiu
2023-12-11 2:49 ` [PATCH v2 05/14] ARM: dts: aspeed: yosemite4: Revise quad mode to dual mode Delphine CC Chiu
2023-12-11 2:49 ` [PATCH v2 06/14] ARM: dts: aspeed: yosemite4: Revise power sensor adm1281 for schematic change Delphine CC Chiu
2023-12-11 2:49 ` [PATCH v2 07/14] ARM: dts: aspeed: yosemite4: Add gpio pca9506 Delphine CC Chiu
2023-12-11 2:49 ` [PATCH v2 08/14] ARM: dts: aspeed: yosemite4: Revise i2c11 and i2c12 schematic change Delphine CC Chiu
2023-12-11 8:04 ` Krzysztof Kozlowski
2023-12-11 2:49 ` [PATCH v2 09/14] ARM: dts: aspeed: yosemite4: Revise i2c14 and i2c15 " Delphine CC Chiu
2023-12-11 2:49 ` Delphine CC Chiu [this message]
2023-12-11 8:05 ` [PATCH v2 10/14] ARM: dts: aspeed: yosemite4: Initialize bmc gpio state Krzysztof Kozlowski
2023-12-11 2:49 ` [PATCH v2 11/14] ARM: dts: aspeed: yosemite4: Revise mx31790 fan tach config Delphine CC Chiu
2023-12-11 2:49 ` [PATCH v2 12/14] ARM: dts: aspeed: yosemite4: add mctp config for NIC Delphine CC Chiu
2023-12-11 8:05 ` Krzysztof Kozlowski
2023-12-11 2:49 ` [PATCH v2 13/14] ARM: dts: aspeed: yosemite4: support mux to cpld Delphine CC Chiu
2023-12-11 2:49 ` [PATCH v2 14/14] ARM: dts: aspeed: yosemite4: Revise gpio name Delphine CC Chiu
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