From: Borislav Petkov <bp@alien8.de>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: LKML <linux-kernel@vger.kernel.org>,
x86@kernel.org, Tom Lendacky <thomas.lendacky@amd.com>,
Andrew Cooper <andrew.cooper3@citrix.com>,
Arjan van de Ven <arjan@linux.intel.com>,
Huang Rui <ray.huang@amd.com>, Juergen Gross <jgross@suse.com>,
Dimitri Sivanich <dimitri.sivanich@hpe.com>,
Sohil Mehta <sohil.mehta@intel.com>,
K Prateek Nayak <kprateek.nayak@amd.com>,
Kan Liang <kan.liang@linux.intel.com>,
Zhang Rui <rui.zhang@intel.com>,
"Paul E. McKenney" <paulmck@kernel.org>,
Feng Tang <feng.tang@intel.com>,
Andy Shevchenko <andy@infradead.org>,
Michael Kelley <mhklinux@outlook.com>,
"Peter Zijlstra (Intel)" <peterz@infradead.org>
Subject: Re: [patch v5 09/19] x86/cpu: Provide an AMD/HYGON specific topology parser
Date: Fri, 2 Feb 2024 13:30:11 +0100 [thread overview]
Message-ID: <20240202123011.GAZbzgU8jqAYiTe8bH@fat_crate.local> (raw)
In-Reply-To: <20240117115908.880472059@linutronix.de>
On Tue, Jan 23, 2024 at 01:53:43PM +0100, Thomas Gleixner wrote:
> +static bool parse_8000_0008(struct topo_scan *tscan)
> +{
> + struct {
> + u32 ncores : 8,
Yeah, so there was some confusion what this field actually means. It is
documented correctly in the latest APM:
"NT: number of physical threads - 1. The number of threads in the
processor is NT+1 (e.g., if NT = 0, then there is one thread). See
“Legacy Method” on page 645."
> + __rsvd0 : 4,
> + apicidsize : 4,
> + perftscsize : 2,
> + __rsvd1 : 14;
> + } ecx;
> + unsigned int sft;
> +
> + if (tscan->c->extended_cpuid_level < 0x80000008)
> + return false;
> +
> + cpuid_leaf_reg(0x80000008, CPUID_ECX, &ecx);
> +
> + /* If the APIC ID size is 0, then get the shift value from ecx.ncores */
> + sft = ecx.apicidsize;
> + if (!sft)
> + sft = get_count_order(ecx.ncores + 1);
> +
> + topology_set_dom(tscan, TOPO_CORE_DOMAIN, sft, ecx.ncores + 1);
So yeah, this should be TOPO_SMT_DOMAIN.
Thx.
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
next prev parent reply other threads:[~2024-02-02 12:30 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-23 12:53 [patch v5 00/19] x86/cpu: Rework topology evaluation Thomas Gleixner
2024-01-23 12:53 ` [patch v5 01/19] x86/cpu: Provide cpuid_read() et al Thomas Gleixner
2024-01-24 12:25 ` Borislav Petkov
2024-01-24 20:02 ` Borislav Petkov
2024-02-12 13:57 ` Thomas Gleixner
2024-01-23 12:53 ` [patch v5 02/19] x86/cpu: Provide cpu_init/parse_topology() Thomas Gleixner
2024-02-01 22:16 ` Sohil Mehta
2024-01-23 12:53 ` [patch v5 03/19] x86/cpu: Add legacy topology parser Thomas Gleixner
2024-01-24 20:12 ` Borislav Petkov
2024-01-23 12:53 ` [patch v5 04/19] x86/cpu: Use common topology code for Centaur and Zhaoxin Thomas Gleixner
2024-01-30 19:09 ` Borislav Petkov
2024-01-23 12:53 ` [patch v5 05/19] x86/cpu: Move __max_die_per_package to common.c Thomas Gleixner
2024-01-23 12:53 ` [patch v5 06/19] x86/cpu: Provide a sane leaf 0xb/0x1f parser Thomas Gleixner
2024-01-30 19:31 ` Borislav Petkov
2024-02-12 14:17 ` Thomas Gleixner
2024-02-12 15:00 ` Borislav Petkov
2024-02-12 15:08 ` Thomas Gleixner
2024-02-12 15:43 ` Borislav Petkov
2024-02-12 23:02 ` Thomas Gleixner
2024-02-12 15:03 ` Thomas Gleixner
2024-02-12 15:05 ` Borislav Petkov
2024-02-13 14:30 ` [tip: x86/misc] Documentation/maintainer-tip: Add C++ tail comments exception tip-bot2 for Borislav Petkov (AMD)
2024-01-23 12:53 ` [patch v5 07/19] x86/cpu: Use common topology code for Intel Thomas Gleixner
2024-02-01 15:07 ` Borislav Petkov
2024-01-23 12:53 ` [patch v5 08/19] x86/cpu/amd: Provide a separate accessor for Node ID Thomas Gleixner
2024-02-01 15:19 ` Borislav Petkov
2024-01-23 12:53 ` [patch v5 09/19] x86/cpu: Provide an AMD/HYGON specific topology parser Thomas Gleixner
2024-02-01 15:55 ` Borislav Petkov
2024-02-02 12:30 ` Borislav Petkov [this message]
2024-01-23 12:53 ` [patch v5 10/19] x86/smpboot: Teach it about topo.amd_node_id Thomas Gleixner
2024-02-06 15:48 ` Borislav Petkov
2024-01-23 12:53 ` [patch v5 11/19] x86/cpu: Use common topology code for AMD Thomas Gleixner
2024-02-06 15:58 ` Borislav Petkov
2024-02-12 14:50 ` Thomas Gleixner
2024-02-12 15:06 ` Borislav Petkov
2024-01-23 12:53 ` [patch v5 12/19] x86/cpu: Use common topology code for HYGON Thomas Gleixner
2024-01-23 12:53 ` [patch v5 13/19] x86/mm/numa: Use core domain size on AMD Thomas Gleixner
2024-02-12 15:56 ` Borislav Petkov
2024-01-23 12:53 ` [patch v5 14/19] x86/cpu: Make topology_amd_node_id() use the actual node info Thomas Gleixner
2024-01-23 12:53 ` [patch v5 15/19] x86/cpu: Remove topology.c Thomas Gleixner
2024-01-23 12:53 ` [patch v5 16/19] x86/cpu: Remove x86_coreid_bits Thomas Gleixner
2024-01-23 12:53 ` [patch v5 17/19] x86/apic: Remove unused phys_pkg_id() callback Thomas Gleixner
2024-01-23 12:53 ` [patch v5 18/19] x86/xen/smp_pv: Remove cpudata fiddling Thomas Gleixner
2024-01-23 12:53 ` [patch v5 19/19] x86/apic/uv: Remove the private leaf 0xb parser Thomas Gleixner
2024-01-31 7:40 ` [patch v5 00/19] x86/cpu: Rework topology evaluation Zhang, Rui
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