From: Ard Biesheuvel <ardb+git@google.com>
To: linux-kernel@vger.kernel.org
Cc: Ard Biesheuvel <ardb@kernel.org>,
Kevin Loughlin <kevinloughlin@google.com>,
Tom Lendacky <thomas.lendacky@amd.com>,
Dionna Glaze <dionnaglaze@google.com>,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>,
Andy Lutomirski <luto@kernel.org>, Arnd Bergmann <arnd@arndb.de>,
Nathan Chancellor <nathan@kernel.org>,
Nick Desaulniers <ndesaulniers@google.com>,
Justin Stitt <justinstitt@google.com>,
Kees Cook <keescook@chromium.org>,
Brian Gerst <brgerst@gmail.com>,
linux-arch@vger.kernel.org, llvm@lists.linux.dev
Subject: [PATCH v5 09/16] x86/startup_64: Simplify calculation of initial page table address
Date: Wed, 21 Feb 2024 12:35:16 +0100 [thread overview]
Message-ID: <20240221113506.2565718-27-ardb+git@google.com> (raw)
In-Reply-To: <20240221113506.2565718-18-ardb+git@google.com>
From: Ard Biesheuvel <ardb@kernel.org>
Determining the address of the initial page table to program into CR3
involves:
- taking the physical address
- adding the SME encryption mask
On the primary entry path, the code is mapped using a 1:1 virtual to
physical translation, so the physical address can be taken directly
using a RIP-relative LEA instruction.
On the secondary entry path, the address can be obtained by taking the
offset from the virtual kernel base (__START_kernel_map) and adding the
physical kernel base.
This is implemented in a slightly confusing way, so clean this up.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
---
arch/x86/kernel/head_64.S | 25 ++++++--------------
1 file changed, 7 insertions(+), 18 deletions(-)
diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S
index 426f6fdc0075..b92031d7e006 100644
--- a/arch/x86/kernel/head_64.S
+++ b/arch/x86/kernel/head_64.S
@@ -111,13 +111,11 @@ SYM_CODE_START_NOALIGN(startup_64)
call __startup_64
/* Form the CR3 value being sure to include the CR3 modifier */
- addq $(early_top_pgt - __START_KERNEL_map), %rax
+ leaq early_top_pgt(%rip), %rcx
+ addq %rcx, %rax
#ifdef CONFIG_AMD_MEM_ENCRYPT
mov %rax, %rdi
- mov %rax, %r14
-
- addq phys_base(%rip), %rdi
/*
* For SEV guests: Verify that the C-bit is correct. A malicious
@@ -126,12 +124,6 @@ SYM_CODE_START_NOALIGN(startup_64)
* the next RET instruction.
*/
call sev_verify_cbit
-
- /*
- * Restore CR3 value without the phys_base which will be added
- * below, before writing %cr3.
- */
- mov %r14, %rax
#endif
jmp 1f
@@ -171,18 +163,18 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_GLOBAL)
/* Clear %R15 which holds the boot_params pointer on the boot CPU */
xorq %r15, %r15
+ /* Derive the runtime physical address of init_top_pgt[] */
+ movq phys_base(%rip), %rax
+ addq $(init_top_pgt - __START_KERNEL_map), %rax
+
/*
* Retrieve the modifier (SME encryption mask if SME is active) to be
* added to the initial pgdir entry that will be programmed into CR3.
*/
#ifdef CONFIG_AMD_MEM_ENCRYPT
- movq sme_me_mask, %rax
-#else
- xorq %rax, %rax
+ addq sme_me_mask(%rip), %rax
#endif
- /* Form the CR3 value being sure to include the CR3 modifier */
- addq $(init_top_pgt - __START_KERNEL_map), %rax
1:
/* Create a mask of CR4 bits to preserve */
@@ -204,9 +196,6 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_GLOBAL)
btsl $X86_CR4_PSE_BIT, %ecx
movq %rcx, %cr4
- /* Setup early boot stage 4-/5-level pagetables. */
- addq phys_base(%rip), %rax
-
/*
* Switch to new page-table
*
--
2.44.0.rc0.258.g7320e95886-goog
next prev parent reply other threads:[~2024-02-21 11:35 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-21 11:35 [PATCH v5 00/16] x86: Confine early 1:1 mapped startup code Ard Biesheuvel
2024-02-21 11:35 ` [PATCH v5 01/16] x86/startup_64: Simplify global variable accesses in GDT/IDT programming Ard Biesheuvel
2024-02-26 12:12 ` [tip: x86/boot] x86/boot/64: " tip-bot2 for Ard Biesheuvel
2024-02-21 11:35 ` [PATCH v5 02/16] x86/startup_64: Use RIP_REL_REF() to assign phys_base Ard Biesheuvel
2024-02-26 12:12 ` [tip: x86/boot] x86/boot/64: Use RIP_REL_REF() to assign 'phys_base' tip-bot2 for Ard Biesheuvel
2024-02-21 11:35 ` [PATCH v5 03/16] x86/startup_64: Use RIP_REL_REF() to access early_dynamic_pgts[] Ard Biesheuvel
2024-02-26 12:12 ` [tip: x86/boot] x86/boot/64: " tip-bot2 for Ard Biesheuvel
2024-02-21 11:35 ` [PATCH v5 04/16] x86/startup_64: Use RIP_REL_REF() to access __supported_pte_mask Ard Biesheuvel
2024-02-26 12:12 ` [tip: x86/boot] x86/boot/64: Use RIP_REL_REF() to access '__supported_pte_mask' tip-bot2 for Ard Biesheuvel
2024-02-21 11:35 ` [PATCH v5 05/16] x86/startup_64: Use RIP_REL_REF() to access early page tables Ard Biesheuvel
2024-02-26 12:12 ` [tip: x86/boot] x86/boot/64: " tip-bot2 for Ard Biesheuvel
2024-02-21 11:35 ` [PATCH v5 06/16] x86/startup_64: Use RIP_REL_REF() to access early_top_pgt[] Ard Biesheuvel
2024-02-26 12:12 ` [tip: x86/boot] x86/boot/64: " tip-bot2 for Ard Biesheuvel
2024-02-21 11:35 ` [PATCH v5 07/16] x86/startup_64: Simplify CR4 handling in startup code Ard Biesheuvel
2024-02-21 14:52 ` Brian Gerst
2024-02-21 11:35 ` [PATCH v5 08/16] x86/startup_64: Defer assignment of 5-level paging global variables Ard Biesheuvel
2024-02-21 11:35 ` Ard Biesheuvel [this message]
2024-02-21 11:35 ` [PATCH v5 10/16] x86/startup_64: Simplify virtual switch on primary boot Ard Biesheuvel
2024-02-23 13:11 ` Ard Biesheuvel
2024-02-21 11:35 ` [PATCH v5 11/16] x86/sme: Avoid SME/SVE related checks on non-SME/SVE platforms Ard Biesheuvel
2024-02-21 11:35 ` [PATCH v5 12/16] efi/libstub: Add generic support for parsing mem_encrypt= Ard Biesheuvel
2024-02-21 11:35 ` [PATCH v5 13/16] x86/boot: Move mem_encrypt= parsing to the decompressor Ard Biesheuvel
2024-02-21 11:35 ` [PATCH v5 14/16] x86/sme: Move early SME kernel encryption handling into .head.text Ard Biesheuvel
2024-02-21 11:35 ` [PATCH v5 15/16] x86/sev: Move early startup code into .head.text section Ard Biesheuvel
2024-02-21 11:35 ` [PATCH v5 16/16] x86/startup_64: Drop global variables keeping track of LA57 state Ard Biesheuvel
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