From: Brian Gerst <brgerst@gmail.com>
To: Ard Biesheuvel <ardb+git@google.com>
Cc: linux-kernel@vger.kernel.org, Ard Biesheuvel <ardb@kernel.org>,
Kevin Loughlin <kevinloughlin@google.com>,
Tom Lendacky <thomas.lendacky@amd.com>,
Dionna Glaze <dionnaglaze@google.com>,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>,
Andy Lutomirski <luto@kernel.org>, Arnd Bergmann <arnd@arndb.de>,
Nathan Chancellor <nathan@kernel.org>,
Nick Desaulniers <ndesaulniers@google.com>,
Justin Stitt <justinstitt@google.com>,
Kees Cook <keescook@chromium.org>,
linux-arch@vger.kernel.org, llvm@lists.linux.dev
Subject: Re: [PATCH v5 07/16] x86/startup_64: Simplify CR4 handling in startup code
Date: Wed, 21 Feb 2024 09:52:53 -0500 [thread overview]
Message-ID: <CAMzpN2iu52yJWv3w1SgDXXGdvbfGi8cHRkip_qqrAO_89-4+sQ@mail.gmail.com> (raw)
In-Reply-To: <20240221113506.2565718-25-ardb+git@google.com>
On Wed, Feb 21, 2024 at 6:35 AM Ard Biesheuvel <ardb+git@google.com> wrote:
>
> From: Ard Biesheuvel <ardb@kernel.org>
>
> When paging is enabled, the CR4.PAE and CR4.LA57 control bits cannot be
> changed, and so they can simply be preserved rather than reason about
> whether or not they need to be set. CR4.MCE should be preserved unless
> the kernel was built without CONFIG_X86_MCE, in which case it must be
> cleared.
>
> CR4.PSE should be set explicitly, regardless of whether or not it was
> set before.
>
> CR4.PGE is set explicitly, and then cleared and set again after
> programming CR3 in order to flush TLB entries based on global
> translations. This makes the first assignment redundant, and can
> therefore be omitted.
>
> Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
> ---
> arch/x86/kernel/head_64.S | 24 +++++++-------------
> 1 file changed, 8 insertions(+), 16 deletions(-)
>
> diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S
> index fb2a98c29094..426f6fdc0075 100644
> --- a/arch/x86/kernel/head_64.S
> +++ b/arch/x86/kernel/head_64.S
> @@ -185,6 +185,8 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_GLOBAL)
> addq $(init_top_pgt - __START_KERNEL_map), %rax
> 1:
>
> + /* Create a mask of CR4 bits to preserve */
> + movl $(X86_CR4_PAE | X86_CR4_LA57), %edx
> #ifdef CONFIG_X86_MCE
> /*
> * Preserve CR4.MCE if the kernel will enable #MC support.
> @@ -193,20 +195,13 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_GLOBAL)
> * configured will crash the system regardless of the CR4.MCE value set
> * here.
> */
> - movq %cr4, %rcx
> - andl $X86_CR4_MCE, %ecx
> -#else
> - movl $0, %ecx
> + orl $X86_CR4_MCE, %edx
> #endif
> + movq %cr4, %rcx
> + andl %edx, %ecx
>
> - /* Enable PAE mode, PSE, PGE and LA57 */
> - orl $(X86_CR4_PAE | X86_CR4_PSE | X86_CR4_PGE), %ecx
> -#ifdef CONFIG_X86_5LEVEL
> - testb $1, __pgtable_l5_enabled(%rip)
> - jz 1f
> - orl $X86_CR4_LA57, %ecx
> -1:
> -#endif
> + /* Even if ignored in long mode, set PSE uniformly on all logical CPUs. */
> + btsl $X86_CR4_PSE_BIT, %ecx
> movq %rcx, %cr4
This CR4 write now does the global flush - see below.
>
> /* Setup early boot stage 4-/5-level pagetables. */
> @@ -226,11 +221,8 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_GLOBAL)
> * Do a global TLB flush after the CR3 switch to make sure the TLB
> * entries from the identity mapping are flushed.
> */
This comment is misleading now since it's the first CR4 write above
(with PGE clear) that actually does the global flush.
> - movq %cr4, %rcx
> - movq %rcx, %rax
> - xorq $X86_CR4_PGE, %rcx
> + btsl $X86_CR4_PGE_BIT, %ecx
> movq %rcx, %cr4
> - movq %rax, %cr4
>
> /* Ensure I am executing from virtual addresses */
> movq $1f, %rax
> --
> 2.44.0.rc0.258.g7320e95886-goog
>
Brian Gerst
next prev parent reply other threads:[~2024-02-21 14:53 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-21 11:35 [PATCH v5 00/16] x86: Confine early 1:1 mapped startup code Ard Biesheuvel
2024-02-21 11:35 ` [PATCH v5 01/16] x86/startup_64: Simplify global variable accesses in GDT/IDT programming Ard Biesheuvel
2024-02-26 12:12 ` [tip: x86/boot] x86/boot/64: " tip-bot2 for Ard Biesheuvel
2024-02-21 11:35 ` [PATCH v5 02/16] x86/startup_64: Use RIP_REL_REF() to assign phys_base Ard Biesheuvel
2024-02-26 12:12 ` [tip: x86/boot] x86/boot/64: Use RIP_REL_REF() to assign 'phys_base' tip-bot2 for Ard Biesheuvel
2024-02-21 11:35 ` [PATCH v5 03/16] x86/startup_64: Use RIP_REL_REF() to access early_dynamic_pgts[] Ard Biesheuvel
2024-02-26 12:12 ` [tip: x86/boot] x86/boot/64: " tip-bot2 for Ard Biesheuvel
2024-02-21 11:35 ` [PATCH v5 04/16] x86/startup_64: Use RIP_REL_REF() to access __supported_pte_mask Ard Biesheuvel
2024-02-26 12:12 ` [tip: x86/boot] x86/boot/64: Use RIP_REL_REF() to access '__supported_pte_mask' tip-bot2 for Ard Biesheuvel
2024-02-21 11:35 ` [PATCH v5 05/16] x86/startup_64: Use RIP_REL_REF() to access early page tables Ard Biesheuvel
2024-02-26 12:12 ` [tip: x86/boot] x86/boot/64: " tip-bot2 for Ard Biesheuvel
2024-02-21 11:35 ` [PATCH v5 06/16] x86/startup_64: Use RIP_REL_REF() to access early_top_pgt[] Ard Biesheuvel
2024-02-26 12:12 ` [tip: x86/boot] x86/boot/64: " tip-bot2 for Ard Biesheuvel
2024-02-21 11:35 ` [PATCH v5 07/16] x86/startup_64: Simplify CR4 handling in startup code Ard Biesheuvel
2024-02-21 14:52 ` Brian Gerst [this message]
2024-02-21 11:35 ` [PATCH v5 08/16] x86/startup_64: Defer assignment of 5-level paging global variables Ard Biesheuvel
2024-02-21 11:35 ` [PATCH v5 09/16] x86/startup_64: Simplify calculation of initial page table address Ard Biesheuvel
2024-02-21 11:35 ` [PATCH v5 10/16] x86/startup_64: Simplify virtual switch on primary boot Ard Biesheuvel
2024-02-23 13:11 ` Ard Biesheuvel
2024-02-21 11:35 ` [PATCH v5 11/16] x86/sme: Avoid SME/SVE related checks on non-SME/SVE platforms Ard Biesheuvel
2024-02-21 11:35 ` [PATCH v5 12/16] efi/libstub: Add generic support for parsing mem_encrypt= Ard Biesheuvel
2024-02-21 11:35 ` [PATCH v5 13/16] x86/boot: Move mem_encrypt= parsing to the decompressor Ard Biesheuvel
2024-02-21 11:35 ` [PATCH v5 14/16] x86/sme: Move early SME kernel encryption handling into .head.text Ard Biesheuvel
2024-02-21 11:35 ` [PATCH v5 15/16] x86/sev: Move early startup code into .head.text section Ard Biesheuvel
2024-02-21 11:35 ` [PATCH v5 16/16] x86/startup_64: Drop global variables keeping track of LA57 state Ard Biesheuvel
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