* [PATCH v6 RESEND 0/4] arm64: qcom: add AIM300 AIoT board support
@ 2024-04-01 9:38 Tengfei Fan
2024-04-01 9:38 ` [PATCH v6 RESEND 1/4] dt-bindings: arm: qcom: Document QCS8550 SoC and the AIM300 AIoT board Tengfei Fan
` (4 more replies)
0 siblings, 5 replies; 10+ messages in thread
From: Tengfei Fan @ 2024-04-01 9:38 UTC (permalink / raw)
To: andersson, konrad.dybcio, robh, krzysztof.kozlowski+dt, conor+dt
Cc: keescook, tony.luck, gpiccoli, linux-arm-msm, devicetree,
linux-kernel, linux-hardening, kernel, Tengfei Fan
Add AIM300 AIoT support along with usb, ufs, regulators, serial, PCIe,
and PMIC functions.
AIM300 Series is a highly optimized family of modules designed to
support AIoT applications. It integrates QCS8550 SoC, UFS and PMIC
chip etc.
Here is a diagram of AIM300 AIoT Carrie Board and SoM
+--------------------------------------------------+
| AIM300 AIOT Carrie Board |
| |
| +-----------------+ |
|power----->| Fixed regulator |---------+ |
| +-----------------+ | |
| | |
| v VPH_PWR |
| +----------------------------------------------+ |
| | AIM300 SOM | | |
| | |VPH_PWR | |
| | v | |
| | +-------+ +--------+ +------+ | |
| | | UFS | | QCS8550| |PMIC | | |
| | +-------+ +--------+ +------+ | |
| | | |
| +----------------------------------------------+ |
| |
| +----+ +------+ |
| |USB | | UART | |
| +----+ +------+ |
+--------------------------------------------------+
The following functions have been verified:
- uart
- usb
- ufs
- PCIe
- PMIC
- display
- adsp
- cdsp
- tlmm
Documentation for qcs8550[1] and sm8550[2]
[1] https://docs.qualcomm.com/bundle/publicresource/87-61717-1_REV_A_Qualcomm_QCS8550_QCM8550_Processors_Product_Brief.pdf
[2] https://www.qualcomm.com/content/dam/qcomm-martech/dm-assets/documents/Snapdragon-8-Gen-2-Product-Brief.pdf
Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
v5 -> v6:
- move qcs8550 board info bebind sm8550 boards info in qcom.yaml
v4 -> v5:
- "2023-2024" instead of "2023~2024" for License
- update patch commit message to previous comments and with an updated
board diagram
- use qcs8550.dtsi instead of qcm8550.dtsi
- remove the reserved memory regions which will be handled by
bootloader
- remove pm8550_flash, pm8550_pwm nodes, Type-C USB/DP function node,
remoteproc_mpss function node, audio sound DTS node, new patch will
be updated after respective team's end to end full verification
- address comments to vph_pwr, move vph_pwr node and related
references to qcs8550-aim300-aiot.dts
- use "regulator-vph-pwr" instead of "vph_pwr_regulator"
- add pcie0I AND pcie1 support together
- the following patches were applied, so remove these patches from new
patch series:
- https://lore.kernel.org/linux-arm-msm/20240119100621.11788-3-quic_tengfan@quicinc.com
- https://lore.kernel.org/linux-arm-msm/20240119100621.11788-4-quic_tengfan@quicinc.com
- verified with dtb check, and result is expected, because those
warnings are not introduced by current patch series.
DTC_CHK arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dtb
arch/arm64/boot/dts/qcom/sm8550.dtsi:3015.27-3070.6: Warning
(avoid_unnecessary_addr_size): /soc@0/display-subsystem@ae00000/dsi@ae96000: unnecessary
#address-cells/#size-cells without "ranges" or child "reg" property
arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dtb:
opp-table: opp-75000000:opp-hz:0: [75000000, 0, 0, 75000000, 0, 0, 0, 0] is too long
from schema $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dtb:
opp-table: opp-150000000:opp-hz:0: [150000000, 0, 0, 150000000, 0, 0, 0, 0] is too long
from schema $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dtb:
opp-table: opp-300000000:opp-hz:0: [300000000, 0, 0, 300000000, 0, 0, 0, 0] is too long
from schema $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dtb:
opp-table: Unevaluated properties are not allowed ('opp-150000000', 'opp-300000000', 'opp-75000000' were unexpected)
from schema $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
v3 -> v4:
- use qcm8550.dtsi instead of qcs8550.dtsi, qcs8550 is a QCS version
of qcm8550, another board with qcm8550 will be added later
- add AIM300 AIoT board string in qcom.yaml file
- add sm8550 and qcm8550 fallback compatible
- add qcm8550 SoC id
- add reserved memory map codes in qcm8550.dtsi
- pm8010 and pmr73d are splited into carrier board DTS file. Because
the regulators which in pm8550, pm8550ve and pm8550vs are present
on the SoM. The regulators which in pm8010 and pmr73d are present
on the carrier board.
- stay VPH_PWR at qcs8550-aim300.dtsi file
VPH_PWR is obtained by vonverting 12v voltage into 3.7 voltage
with a 3.7v buck. VPH_PWR is power supply for regulators in AIM300
SOM. VPH_PWR regulator is defined in AIM300 SOM dtsi file.
v2 -> v3:
- introduce qcs8550.dtsi
- separate fix dtc W=1 warning patch to another patch series
v1 -> v2:
- merge the splited dts patches into one patch
- update dts file name from qcom8550-aim300.dts to qcs8550-aim300 dts
- drop PCIe1 dts node due to it is not enabled
- update display node name for drop sde characters
previous discussion here:
[1] v5: https://lore.kernel.org/linux-arm-msm/20240301134113.14423-1-quic_tengfan@quicinc.com
[2] v4: https://lore.kernel.org/linux-arm-msm/20240119100621.11788-1-quic_tengfan@quicinc.com
[3] v3: https://lore.kernel.org/linux-arm-msm/20231219005007.11644-1-quic_tengfan@quicinc.com
[4] v2: https://lore.kernel.org/linux-arm-msm/20231207092801.7506-1-quic_tengfan@quicinc.com
[5] v1: https://lore.kernel.org/linux-arm-msm/20231117101817.4401-1-quic_tengfan@quicinc.com
Tengfei Fan (4):
dt-bindings: arm: qcom: Document QCS8550 SoC and the AIM300 AIoT board
arm64: dts: qcom: qcs8550: introduce qcs8550 dtsi
arm64: dts: qcom: add base AIM300 dtsi
arm64: dts: qcom: aim300: add AIM300 AIoT
.../devicetree/bindings/arm/qcom.yaml | 8 +
arch/arm64/boot/dts/qcom/Makefile | 1 +
.../boot/dts/qcom/qcs8550-aim300-aiot.dts | 384 ++++++++++++++++++
arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi | 345 ++++++++++++++++
arch/arm64/boot/dts/qcom/qcs8550.dtsi | 169 ++++++++
5 files changed, 907 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts
create mode 100644 arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/qcs8550.dtsi
base-commit: a6bd6c9333397f5a0e2667d4d82fef8c970108f2
--
2.25.1
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v6 RESEND 1/4] dt-bindings: arm: qcom: Document QCS8550 SoC and the AIM300 AIoT board
2024-04-01 9:38 [PATCH v6 RESEND 0/4] arm64: qcom: add AIM300 AIoT board support Tengfei Fan
@ 2024-04-01 9:38 ` Tengfei Fan
2024-04-01 9:38 ` [PATCH v6 RESEND 2/4] arm64: dts: qcom: qcs8550: introduce qcs8550 dtsi Tengfei Fan
` (3 subsequent siblings)
4 siblings, 0 replies; 10+ messages in thread
From: Tengfei Fan @ 2024-04-01 9:38 UTC (permalink / raw)
To: andersson, konrad.dybcio, robh, krzysztof.kozlowski+dt, conor+dt
Cc: keescook, tony.luck, gpiccoli, linux-arm-msm, devicetree,
linux-kernel, linux-hardening, kernel, Tengfei Fan,
Krzysztof Kozlowski
Document QCS8550 SoC and the AIM300 AIoT board bindings.
QCS8550 is derived from SM8550. The difference between SM8550 and
QCS8550 is QCS8550 doesn't have modem RF system. QCS8550 is mainly used
in IoT scenarios.
AIM300 Series is a highly optimized family of modules designed to
support AIoT applications. It integrates QCS8550 SoC, UFS and PMIC chip
etc.
AIM stands for Artificial Intelligence Module. AIoT stands for AI IoT.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
Documentation/devicetree/bindings/arm/qcom.yaml | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 66beaac60e1d..8115088a6076 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -42,6 +42,7 @@ description: |
msm8996
msm8998
qcs404
+ qcs8550
qcm2290
qcm6490
qdu1000
@@ -1005,6 +1006,13 @@ properties:
- qcom,sm8550-qrd
- const: qcom,sm8550
+ - items:
+ - enum:
+ - qcom,qcs8550-aim300-aiot
+ - const: qcom,qcs8550-aim300
+ - const: qcom,qcs8550
+ - const: qcom,sm8550
+
- items:
- enum:
- qcom,sm8650-mtp
--
2.25.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v6 RESEND 2/4] arm64: dts: qcom: qcs8550: introduce qcs8550 dtsi
2024-04-01 9:38 [PATCH v6 RESEND 0/4] arm64: qcom: add AIM300 AIoT board support Tengfei Fan
2024-04-01 9:38 ` [PATCH v6 RESEND 1/4] dt-bindings: arm: qcom: Document QCS8550 SoC and the AIM300 AIoT board Tengfei Fan
@ 2024-04-01 9:38 ` Tengfei Fan
2024-04-01 19:13 ` Dmitry Baryshkov
2024-04-01 9:38 ` [PATCH v6 RESEND 3/4] arm64: dts: qcom: add base AIM300 dtsi Tengfei Fan
` (2 subsequent siblings)
4 siblings, 1 reply; 10+ messages in thread
From: Tengfei Fan @ 2024-04-01 9:38 UTC (permalink / raw)
To: andersson, konrad.dybcio, robh, krzysztof.kozlowski+dt, conor+dt
Cc: keescook, tony.luck, gpiccoli, linux-arm-msm, devicetree,
linux-kernel, linux-hardening, kernel, Tengfei Fan
QCS8550 is derived from SM8550. The differnece between SM8550 and
QCS8550 is QCS8550 doesn't have modem RF system. QCS8550 is mainly used
in IoT scenarios.
QCS8550 firmware has different memory map with SM8550 firmware. The
memory map will be runtime added through bootloader.
There are 3 types of reserved memory regions here:
1. Firmware related regions which aren't shared with kernel.
The device tree source in kernel doesn't need to have node to indicate
the firmware related reserved information. OS bootloader conveys the
information by update device tree in runtime.
This will be described as: UEFI saves the physical address of the
UEFI System Table to dts file's chosen node. Kernel read this table and
add reserved memory regions to efi config table. Current reserved memory
region may have reserved region which was not yet used, release note of
the firmware have such kind of information.
2. Firmware related memory regions which are shared with Kernel
Each region has a specific node with specific label name for later
phandle reference from other driver dt node.
3. PIL regions.
PIL regions will be reserved and then assigned to subsystem firmware
later.
Here is a reserved memory map for this platform:
0x100000000 +------------------+
| |
| Firmware Related |
| |
0xd4d00000 +------------------+
| |
| Kernel Available |
| |
0xa7000000 +------------------+
| |
| PIL Region |
| |
0x8a800000 +------------------+
| |
| Firmware Related |
| |
0x80000000 +------------------+
Note that:
0xa7000000..0xA8000000 is used by bootloader, when kernel boot up,
it is available for kernel usage. This region is not suggested to be
used by kernel features like ramoops, suspend resume etc.
Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
arch/arm64/boot/dts/qcom/qcs8550.dtsi | 169 ++++++++++++++++++++++++++
1 file changed, 169 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/qcs8550.dtsi
diff --git a/arch/arm64/boot/dts/qcom/qcs8550.dtsi b/arch/arm64/boot/dts/qcom/qcs8550.dtsi
new file mode 100644
index 000000000000..a3ebf3d4e16d
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs8550.dtsi
@@ -0,0 +1,169 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "sm8550.dtsi"
+
+/delete-node/ &reserved_memory;
+
+/ {
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+
+ /* These are 3 types of reserved memory regions here:
+ * 1. Firmware related regions which aren't shared with kernel.
+ * The device tree source in kernel doesn't need to have node to
+ * indicate the firmware related reserved information. OS bootloader
+ * conveys the information by update device tree in runtime.
+ * This will be described as: UEFI saves the physical address of
+ * the UEFI System Table to dts file's chosen node. Kernel read this
+ * table and add reserved memory regions to efi config table. Current
+ * reserved memory region may have reserved region which was not yet
+ * used, release note of the firmware have such kind of information.
+ * 2. Firmware related memory regions which are shared with Kernel.
+ * Each region has a specific node with specific label name for
+ * later phandle reference from other driver dt node.
+ * 3. PIL regions.
+ * PIL regions will be reserved and then assigned to subsystem
+ * firmware later.
+ * Here is a reserved memory map for this platform:
+ * 0x100000000 +------------------+
+ * | |
+ * | Firmware Related |
+ * | |
+ * 0xd4d00000 +------------------+
+ * | |
+ * | Kernel Available |
+ * | |
+ * 0xa7000000 +------------------+
+ * | |
+ * | PIL Region |
+ * | |
+ * 0x8a800000 +------------------+
+ * | |
+ * | Firmware Related |
+ * | |
+ * 0x80000000 +------------------+
+ * Note that:
+ * 0xa7000000..0xA8000000 is used by bootloader, when kernel boot up,
+ * it is available for kernel usage. This region is not suggested to
+ * be used by kernel features like ramoops, suspend resume etc.
+ */
+
+ /*
+ * Firmware related regions, bootlader will possible reserve parts of
+ * region from 0x80000000..0x8a800000.
+ */
+ aop_image_mem: aop-image-region@81c00000 {
+ reg = <0x0 0x81c00000 0x0 0x60000>;
+ no-map;
+ };
+
+ aop_cmd_db_mem: aop-cmd-db-region@81c60000 {
+ compatible = "qcom,cmd-db";
+ reg = <0x0 0x81c60000 0x0 0x20000>;
+ no-map;
+ };
+
+ aop_config_mem: aop-config-region@81c80000 {
+ no-map;
+ reg = <0x0 0x81c80000 0x0 0x20000>;
+ };
+
+ smem_mem: smem-region@81d00000 {
+ compatible = "qcom,smem";
+ reg = <0x0 0x81d00000 0x0 0x200000>;
+ hwlocks = <&tcsr_mutex 3>;
+ no-map;
+ };
+
+ adsp_mhi_mem: adsp-mhi-region@81f00000 {
+ reg = <0x0 0x81f00000 0x0 0x20000>;
+ no-map;
+ };
+
+ /* PIL region */
+ mpss_mem: mpss-region@8a800000 {
+ reg = <0x0 0x8a800000 0x0 0x10800000>;
+ no-map;
+ };
+
+ q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 {
+ reg = <0x0 0x9b000000 0x0 0x80000>;
+ no-map;
+ };
+
+ ipa_fw_mem: ipa-fw-region@9b080000 {
+ reg = <0x0 0x9b080000 0x0 0x10000>;
+ no-map;
+ };
+
+ ipa_gsi_mem: ipa-gsi-region@9b090000 {
+ reg = <0x0 0x9b090000 0x0 0xa000>;
+ no-map;
+ };
+
+ gpu_micro_code_mem: gpu-micro-code-region@9b09a000 {
+ reg = <0x0 0x9b09a000 0x0 0x2000>;
+ no-map;
+ };
+
+ spss_region_mem: spss-region@9b100000 {
+ reg = <0x0 0x9b100000 0x0 0x180000>;
+ no-map;
+ };
+
+ spu_secure_shared_memory_mem: spu-secure-shared-memory-region@9b280000 {
+ reg = <0x0 0x9b280000 0x0 0x80000>;
+ no-map;
+ };
+
+ camera_mem: camera-region@9b300000 {
+ reg = <0x0 0x9b300000 0x0 0x800000>;
+ no-map;
+ };
+
+ video_mem: video-region@9bb00000 {
+ reg = <0x0 0x9bb00000 0x0 0x700000>;
+ no-map;
+ };
+
+ cvp_mem: cvp-region@9c200000 {
+ reg = <0x0 0x9c200000 0x0 0x700000>;
+ no-map;
+ };
+
+ cdsp_mem: cdsp-region@9c900000 {
+ reg = <0x0 0x9c900000 0x0 0x2000000>;
+ no-map;
+ };
+
+ q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 {
+ reg = <0x0 0x9e900000 0x0 0x80000>;
+ no-map;
+ };
+
+ q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 {
+ reg = <0x0 0x9e980000 0x0 0x80000>;
+ no-map;
+ };
+
+ adspslpi_mem: adspslpi-region@9ea00000 {
+ reg = <0x0 0x9ea00000 0x0 0x4080000>;
+ no-map;
+ };
+
+ /*
+ * Firmware related regions, bootlader will possible reserve parts of
+ * region from 0xd8000000..0x100000000.
+ */
+ mpss_dsm_mem: mpss_dsm_region@d4d00000 {
+ reg = <0x0 0xd4d00000 0x0 0x3300000>;
+ no-map;
+ };
+ };
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v6 RESEND 3/4] arm64: dts: qcom: add base AIM300 dtsi
2024-04-01 9:38 [PATCH v6 RESEND 0/4] arm64: qcom: add AIM300 AIoT board support Tengfei Fan
2024-04-01 9:38 ` [PATCH v6 RESEND 1/4] dt-bindings: arm: qcom: Document QCS8550 SoC and the AIM300 AIoT board Tengfei Fan
2024-04-01 9:38 ` [PATCH v6 RESEND 2/4] arm64: dts: qcom: qcs8550: introduce qcs8550 dtsi Tengfei Fan
@ 2024-04-01 9:38 ` Tengfei Fan
2024-04-01 9:38 ` [PATCH v6 RESEND 4/4] arm64: dts: qcom: aim300: add AIM300 AIoT Tengfei Fan
2024-04-01 15:54 ` [PATCH v6 RESEND 0/4] arm64: qcom: add AIM300 AIoT board support Trilok Soni
4 siblings, 0 replies; 10+ messages in thread
From: Tengfei Fan @ 2024-04-01 9:38 UTC (permalink / raw)
To: andersson, konrad.dybcio, robh, krzysztof.kozlowski+dt, conor+dt
Cc: keescook, tony.luck, gpiccoli, linux-arm-msm, devicetree,
linux-kernel, linux-hardening, kernel, Tengfei Fan, Fenglin Wu
AIM300 Series is a highly optimized family of modules designed to
support AIoT applications. It integrates QCS8550 SoC, UFS and PMIC
chip etc.
Here is a diagram of AIM300 SoM:
+----------------------------------------+
|AIM300 SoM |
| |
| +-----+ |
| |--->| UFS | |
| | +-----+ |
| | |
| | |
3.7v | +-----------------+ | +---------+ |
---------->| PMIC |----->| QCS8550 | |
| +-----------------+ +---------+ |
| | |
| | |
| | +-----+ |
| |--->| ... | |
| +-----+ |
| |
+----------------------------------------+
Co-developed-by: Fenglin Wu <quic_fenglinw@quicinc.com>
Signed-off-by: Fenglin Wu <quic_fenglinw@quicinc.com>
Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi | 345 +++++++++++++++++++
1 file changed, 345 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi
diff --git a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi
new file mode 100644
index 000000000000..43dde67df136
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi
@@ -0,0 +1,345 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "qcs8550.dtsi"
+#include "pm8550.dtsi"
+#include "pm8550b.dtsi"
+#define PMK8550VE_SID 5
+#include "pm8550ve.dtsi"
+#include "pm8550vs.dtsi"
+#include "pmk8550.dtsi"
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm8550-rpmh-regulators";
+ qcom,pmic-id = "b";
+
+ vdd-l1-l4-l10-supply = <&vreg_s6g_1p86>;
+ vdd-l2-l13-l14-supply = <&vreg_bob1>;
+ vdd-l3-supply = <&vreg_s4g_1p25>;
+ vdd-l5-l16-supply = <&vreg_bob1>;
+ vdd-l6-l7-supply = <&vreg_bob1>;
+ vdd-l8-l9-supply = <&vreg_bob1>;
+ vdd-l11-supply = <&vreg_s4g_1p25>;
+ vdd-l12-supply = <&vreg_s6g_1p86>;
+ vdd-l15-supply = <&vreg_s6g_1p86>;
+ vdd-l17-supply = <&vreg_bob2>;
+
+ vreg_bob1: bob1 {
+ regulator-name = "vreg_bob1";
+ regulator-min-microvolt = <3296000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_bob2: bob2 {
+ regulator-name = "vreg_bob2";
+ regulator-min-microvolt = <2720000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1b_1p8: ldo1 {
+ regulator-name = "vreg_l1b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2b_3p0: ldo2 {
+ regulator-name = "vreg_l2b_3p0";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5b_3p1: ldo5 {
+ regulator-name = "vreg_l5b_3p1";
+ regulator-min-microvolt = <3104000>;
+ regulator-max-microvolt = <3104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6b_1p8: ldo6 {
+ regulator-name = "vreg_l6b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7b_1p8: ldo7 {
+ regulator-name = "vreg_l7b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8b_1p8: ldo8 {
+ regulator-name = "vreg_l8b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9b_2p9: ldo9 {
+ regulator-name = "vreg_l9b_2p9";
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11b_1p2: ldo11 {
+ regulator-name = "vreg_l11b_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12b_1p8: ldo12 {
+ regulator-name = "vreg_l12b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13b_3p0: ldo13 {
+ regulator-name = "vreg_l13b_3p0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l14b_3p2: ldo14 {
+ regulator-name = "vreg_l14b_3p2";
+ regulator-min-microvolt = <3200000>;
+ regulator-max-microvolt = <3200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15b_1p8: ldo15 {
+ regulator-name = "vreg_l15b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16b_2p8: ldo16 {
+ regulator-name = "vreg_l16b_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17b_2p5: ldo17 {
+ regulator-name = "vreg_l17b_2p5";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vdd-l1-supply = <&vreg_s4g_1p25>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-l3-supply = <&vreg_s4e_0p95>;
+
+ vreg_l3c_0p9: ldo3 {
+ regulator-name = "vreg_l3c_0p9";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-2 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "d";
+
+ vdd-l1-supply = <&vreg_s4e_0p95>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-l3-supply = <&vreg_s4e_0p95>;
+
+ vreg_l1d_0p88: ldo1 {
+ regulator-name = "vreg_l1d_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-3 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "e";
+
+ vdd-l1-supply = <&vreg_s4e_0p95>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-l3-supply = <&vreg_s4g_1p25>;
+
+ vreg_s4e_0p95: smps4 {
+ regulator-name = "vreg_s4e_0p95";
+ regulator-min-microvolt = <904000>;
+ regulator-max-microvolt = <984000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5e_1p08: smps5 {
+ regulator-name = "vreg_s5e_1p08";
+ regulator-min-microvolt = <1010000>;
+ regulator-max-microvolt = <1120000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1e_0p88: ldo1 {
+ regulator-name = "vreg_l1e_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2e_0p9: ldo2 {
+ regulator-name = "vreg_l2e_0p9";
+ regulator-min-microvolt = <870000>;
+ regulator-max-microvolt = <970000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3e_1p2: ldo3 {
+ regulator-name = "vreg_l3e_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-4 {
+ compatible = "qcom,pm8550ve-rpmh-regulators";
+ qcom,pmic-id = "f";
+
+ vdd-l1-supply = <&vreg_s4e_0p95>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-l3-supply = <&vreg_s4e_0p95>;
+
+ vreg_s4f_0p5: smps4 {
+ regulator-name = "vreg_s4f_0p5";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <700000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1f_0p9: ldo1 {
+ regulator-name = "vreg_l1f_0p9";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2f_0p88: ldo2 {
+ regulator-name = "vreg_l2f_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3f_0p88: ldo3 {
+ regulator-name = "vreg_l3f_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-5 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "g";
+ vdd-l1-supply = <&vreg_s4g_1p25>;
+ vdd-l2-supply = <&vreg_s4g_1p25>;
+ vdd-l3-supply = <&vreg_s4g_1p25>;
+
+ vreg_s1g_1p25: smps1 {
+ regulator-name = "vreg_s1g_1p25";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s2g_0p85: smps2 {
+ regulator-name = "vreg_s2g_0p85";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1036000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s3g_0p8: smps3 {
+ regulator-name = "vreg_s3g_0p8";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1004000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s4g_1p25: smps4 {
+ regulator-name = "vreg_s4g_1p25";
+ regulator-min-microvolt = <1256000>;
+ regulator-max-microvolt = <1408000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5g_0p85: smps5 {
+ regulator-name = "vreg_s5g_0p85";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1004000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s6g_1p86: smps6 {
+ regulator-name = "vreg_s6g_1p86";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1g_1p2: ldo1 {
+ regulator-name = "vreg_l1g_1p2";
+ regulator-min-microvolt = <1128000>;
+ regulator-max-microvolt = <1272000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2g_1p2: ldo2 {
+ regulator-name = "vreg_l2g_1p2";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3g_1p2: ldo3 {
+ regulator-name = "vreg_l3g_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
+
+&ufs_mem_hc {
+ reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
+ vcc-supply = <&vreg_l17b_2p5>;
+ vcc-max-microamp = <1300000>;
+ vccq-supply = <&vreg_l1g_1p2>;
+ vccq-max-microamp = <1200000>;
+ vdd-hba-supply = <&vreg_l3g_1p2>;
+
+ status = "okay";
+};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l1d_0p88>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v6 RESEND 4/4] arm64: dts: qcom: aim300: add AIM300 AIoT
2024-04-01 9:38 [PATCH v6 RESEND 0/4] arm64: qcom: add AIM300 AIoT board support Tengfei Fan
` (2 preceding siblings ...)
2024-04-01 9:38 ` [PATCH v6 RESEND 3/4] arm64: dts: qcom: add base AIM300 dtsi Tengfei Fan
@ 2024-04-01 9:38 ` Tengfei Fan
2024-04-01 19:22 ` Dmitry Baryshkov
2024-04-01 15:54 ` [PATCH v6 RESEND 0/4] arm64: qcom: add AIM300 AIoT board support Trilok Soni
4 siblings, 1 reply; 10+ messages in thread
From: Tengfei Fan @ 2024-04-01 9:38 UTC (permalink / raw)
To: andersson, konrad.dybcio, robh, krzysztof.kozlowski+dt, conor+dt
Cc: keescook, tony.luck, gpiccoli, linux-arm-msm, devicetree,
linux-kernel, linux-hardening, kernel, Tengfei Fan, Qiang Yu,
Ziyue Zhang
Add AIM300 AIoT Carrier board DTS support, including usb, UART, PCIe,
I2C functions support.
Here is a diagram of AIM300 AIoT Carrie Board and SoM
+--------------------------------------------------+
| AIM300 AIOT Carrie Board |
| |
| +-----------------+ |
|power----->| Fixed regulator |---------+ |
| +-----------------+ | |
| | |
| v VPH_PWR |
| +----------------------------------------------+ |
| | AIM300 SOM | | |
| | |VPH_PWR | |
| | v | |
| | +-------+ +--------+ +------+ | |
| | | UFS | | QCS8550| |PMIC | | |
| | +-------+ +--------+ +------+ | |
| | | |
| +----------------------------------------------+ |
| |
| +----+ +------+ |
| |USB | | UART | |
| +----+ +------+ |
+--------------------------------------------------+
Co-developed-by: Qiang Yu <quic_qianyu@quicinc.com>
Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
Co-developed-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
.../boot/dts/qcom/qcs8550-aim300-aiot.dts | 384 ++++++++++++++++++
2 files changed, 385 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 7d40ec5e7d21..02d9bc3bfce7 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -96,6 +96,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qcm6490-idp.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb
+dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb
dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb
dtb-$(CONFIG_ARCH_QCOM) += qrb2210-rb1.dtb
dtb-$(CONFIG_ARCH_QCOM) += qrb4210-rb2.dtb
diff --git a/arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts b/arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts
new file mode 100644
index 000000000000..8188766c3d84
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts
@@ -0,0 +1,384 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include "qcs8550-aim300.dtsi"
+#include "pm8010.dtsi"
+#include "pmr735d_a.dtsi"
+#include "pmr735d_b.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. QCS8550 AIM300 AIOT";
+ compatible = "qcom,qcs8550-aim300-aiot", "qcom,qcs8550-aim300", "qcom,qcs8550",
+ "qcom,sm8550";
+
+ aliases {
+ serial0 = &uart7;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&volume_up_n>;
+ pinctrl-names = "default";
+
+ key-volume-up {
+ label = "Volume Up";
+ debounce-interval = <15>;
+ gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ linux,can-disable;
+ wakeup-source;
+ };
+ };
+
+ pmic-glink {
+ compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ orientation-gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
+
+ connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pmic_glink_hs_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ pmic_glink_ss_in: endpoint {
+ remote-endpoint = <&redriver_ss_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ pmic_glink_sbu: endpoint {
+ remote-endpoint = <&fsa4480_sbu_mux>;
+ };
+ };
+ };
+ };
+ };
+
+ vph_pwr: regulator-vph-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ vdd-bob1-supply = <&vph_pwr>;
+ vdd-bob2-supply = <&vph_pwr>;
+ };
+
+ regulators-3 {
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ };
+
+ regulators-4 {
+ vdd-s4-supply = <&vph_pwr>;
+ };
+
+ regulators-5 {
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ };
+};
+
+&i2c_hub_2 {
+ status = "okay";
+
+ typec-mux@42 {
+ compatible = "fcs,fsa4480";
+ reg = <0x42>;
+
+ vcc-supply = <&vreg_bob1>;
+
+ mode-switch;
+ orientation-switch;
+
+ port {
+ fsa4480_sbu_mux: endpoint {
+ remote-endpoint = <&pmic_glink_sbu>;
+ };
+ };
+ };
+
+ typec-retimer@1c {
+ compatible = "onnn,nb7vpq904m";
+ reg = <0x1c>;
+
+ vcc-supply = <&vreg_l15b_1p8>;
+
+ orientation-switch;
+ retimer-switch;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ redriver_ss_out: endpoint {
+ remote-endpoint = <&pmic_glink_ss_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ redriver_ss_in: endpoint {
+ data-lanes = <3 2 1 0>;
+ remote-endpoint = <&usb_dp_qmpphy_out>;
+ };
+ };
+ };
+ };
+};
+
+&mdss_dsi0 {
+ vdda-supply = <&vreg_l3e_1p2>;
+ status = "okay";
+
+ panel@0 {
+ compatible = "visionox,vtdr6130";
+ reg = <0>;
+
+ pinctrl-0 = <&dsi_active>, <&te_active>;
+ pinctrl-1 = <&dsi_suspend>, <&te_suspend>;
+ pinctrl-names = "default", "sleep";
+
+ reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>;
+
+ vci-supply = <&vreg_l13b_3p0>;
+ vdd-supply = <&vreg_l11b_1p2>;
+ vddio-supply = <&vreg_l12b_1p8>;
+
+ port {
+ panel0_in: endpoint {
+ remote-endpoint = <&mdss_dsi0_out>;
+ };
+ };
+ };
+};
+
+&mdss_dsi0_out {
+ remote-endpoint = <&panel0_in>;
+ data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi0_phy {
+ vdds-supply = <&vreg_l1e_0p88>;
+ status = "okay";
+};
+
+&pcie0 {
+ perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-0 = <&pcie0_default_state>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pcie0_phy {
+ vdda-phy-supply = <&vreg_l1e_0p88>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&pcie_1_phy_aux_clk {
+ clock-frequency = <1000>;
+};
+
+&pcie1 {
+ perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-0 = <&pcie1_default_state>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pcie1_phy {
+ vdda-phy-supply = <&vreg_l3c_0p9>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+ vdda-qref-supply = <&vreg_l1e_0p88>;
+
+ status = "okay";
+};
+
+&pm8550_gpios {
+ volume_up_n: volume-up-n-state {
+ pins = "gpio6";
+ function = "normal";
+ power-source = <1>;
+ bias-pull-up;
+ input-enable;
+ };
+};
+
+&pm8550b_eusb2_repeater {
+ vdd18-supply = <&vreg_l15b_1p8>;
+ vdd3-supply = <&vreg_l5b_3p1>;
+};
+
+
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+
+ status = "okay";
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&remoteproc_adsp {
+ firmware-name = "qcom/qcs8550/adsp.mbn",
+ "qcom/qcs8550/adsp_dtbs.elf";
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/qcs8550/cdsp.mbn",
+ "qcom/qcs8550/cdsp_dtbs.elf";
+ status = "okay";
+};
+
+&sleep_clk {
+ clock-frequency = <32000>;
+};
+
+&swr1 {
+ status = "okay";
+};
+
+&swr2 {
+ status = "okay";
+};
+
+&tlmm {
+ gpio-reserved-ranges = <32 8>;
+
+ dsi_active: dsi-active-state {
+ pins = "gpio133";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ dsi_suspend: dsi-suspend-state {
+ pins = "gpio133";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ te_active: te-active-state {
+ pins = "gpio86";
+ function = "mdp_vsync";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ te_suspend: te-suspend-state {
+ pins = "gpio86";
+ function = "mdp_vsync";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+};
+
+&uart7 {
+ status = "okay";
+};
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3 {
+ dr_mode = "otg";
+ usb-role-switch;
+};
+
+&usb_1_dwc3_hs {
+ remote-endpoint = <&pmic_glink_hs_in>;
+};
+
+&usb_1_dwc3_ss {
+ remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
+};
+
+&usb_1_hsphy {
+ phys = <&pm8550b_eusb2_repeater>;
+
+ vdd-supply = <&vreg_l1e_0p88>;
+ vdda12-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&usb_dp_qmpphy {
+ vdda-phy-supply = <&vreg_l3e_1p2>;
+ vdda-pll-supply = <&vreg_l3f_0p88>;
+
+ orientation-switch;
+
+ status = "okay";
+};
+
+&usb_dp_qmpphy_out {
+ remote-endpoint = <&redriver_ss_in>;
+};
+
+&usb_dp_qmpphy_usb_ss_in {
+ remote-endpoint = <&usb_1_dwc3_ss>;
+};
+
+&xo_board {
+ clock-frequency = <76800000>;
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v6 RESEND 0/4] arm64: qcom: add AIM300 AIoT board support
2024-04-01 9:38 [PATCH v6 RESEND 0/4] arm64: qcom: add AIM300 AIoT board support Tengfei Fan
` (3 preceding siblings ...)
2024-04-01 9:38 ` [PATCH v6 RESEND 4/4] arm64: dts: qcom: aim300: add AIM300 AIoT Tengfei Fan
@ 2024-04-01 15:54 ` Trilok Soni
2024-04-02 2:29 ` Tengfei Fan
4 siblings, 1 reply; 10+ messages in thread
From: Trilok Soni @ 2024-04-01 15:54 UTC (permalink / raw)
To: Tengfei Fan, andersson, konrad.dybcio, robh,
krzysztof.kozlowski+dt, conor+dt
Cc: keescook, tony.luck, gpiccoli, linux-arm-msm, devicetree,
linux-kernel, linux-hardening, kernel
On 4/1/2024 2:38 AM, Tengfei Fan wrote:
> Here is a diagram of AIM300 AIoT Carrie Board and SoM
> +--------------------------------------------------+
> | AIM300 AIOT Carrie Board |
spellcheck
s/Carrie/Carrier ?
--
---Trilok Soni
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v6 RESEND 2/4] arm64: dts: qcom: qcs8550: introduce qcs8550 dtsi
2024-04-01 9:38 ` [PATCH v6 RESEND 2/4] arm64: dts: qcom: qcs8550: introduce qcs8550 dtsi Tengfei Fan
@ 2024-04-01 19:13 ` Dmitry Baryshkov
0 siblings, 0 replies; 10+ messages in thread
From: Dmitry Baryshkov @ 2024-04-01 19:13 UTC (permalink / raw)
To: Tengfei Fan
Cc: andersson, konrad.dybcio, robh, krzysztof.kozlowski+dt, conor+dt,
keescook, tony.luck, gpiccoli, linux-arm-msm, devicetree,
linux-kernel, linux-hardening, kernel
On Mon, 1 Apr 2024 at 12:40, Tengfei Fan <quic_tengfan@quicinc.com> wrote:
>
> QCS8550 is derived from SM8550. The differnece between SM8550 and
> QCS8550 is QCS8550 doesn't have modem RF system. QCS8550 is mainly used
> in IoT scenarios.
> QCS8550 firmware has different memory map with SM8550 firmware. The
> memory map will be runtime added through bootloader.
> There are 3 types of reserved memory regions here:
> 1. Firmware related regions which aren't shared with kernel.
> The device tree source in kernel doesn't need to have node to indicate
> the firmware related reserved information. OS bootloader conveys the
> information by update device tree in runtime.
> This will be described as: UEFI saves the physical address of the
> UEFI System Table to dts file's chosen node. Kernel read this table and
> add reserved memory regions to efi config table. Current reserved memory
> region may have reserved region which was not yet used, release note of
> the firmware have such kind of information.
> 2. Firmware related memory regions which are shared with Kernel
> Each region has a specific node with specific label name for later
> phandle reference from other driver dt node.
> 3. PIL regions.
> PIL regions will be reserved and then assigned to subsystem firmware
> later.
> Here is a reserved memory map for this platform:
> 0x100000000 +------------------+
> | |
> | Firmware Related |
> | |
> 0xd4d00000 +------------------+
> | |
> | Kernel Available |
> | |
> 0xa7000000 +------------------+
> | |
> | PIL Region |
> | |
> 0x8a800000 +------------------+
> | |
> | Firmware Related |
> | |
> 0x80000000 +------------------+
> Note that:
> 0xa7000000..0xA8000000 is used by bootloader, when kernel boot up,
> it is available for kernel usage. This region is not suggested to be
> used by kernel features like ramoops, suspend resume etc.
>
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/qcs8550.dtsi | 169 ++++++++++++++++++++++++++
> 1 file changed, 169 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/qcs8550.dtsi
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Minor nit below.
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs8550.dtsi b/arch/arm64/boot/dts/qcom/qcs8550.dtsi
> new file mode 100644
> index 000000000000..a3ebf3d4e16d
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/qcs8550.dtsi
> @@ -0,0 +1,169 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include "sm8550.dtsi"
> +
> +/delete-node/ &reserved_memory;
> +
> +/ {
> + reserved_memory: reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> +
> + /* These are 3 types of reserved memory regions here:
> + * 1. Firmware related regions which aren't shared with kernel.
> + * The device tree source in kernel doesn't need to have node to
> + * indicate the firmware related reserved information. OS bootloader
> + * conveys the information by update device tree in runtime.
> + * This will be described as: UEFI saves the physical address of
> + * the UEFI System Table to dts file's chosen node. Kernel read this
> + * table and add reserved memory regions to efi config table. Current
> + * reserved memory region may have reserved region which was not yet
> + * used, release note of the firmware have such kind of information.
> + * 2. Firmware related memory regions which are shared with Kernel.
> + * Each region has a specific node with specific label name for
> + * later phandle reference from other driver dt node.
> + * 3. PIL regions.
> + * PIL regions will be reserved and then assigned to subsystem
> + * firmware later.
> + * Here is a reserved memory map for this platform:
> + * 0x100000000 +------------------+
> + * | |
> + * | Firmware Related |
> + * | |
> + * 0xd4d00000 +------------------+
> + * | |
> + * | Kernel Available |
> + * | |
> + * 0xa7000000 +------------------+
> + * | |
> + * | PIL Region |
> + * | |
> + * 0x8a800000 +------------------+
> + * | |
> + * | Firmware Related |
> + * | |
> + * 0x80000000 +------------------+
> + * Note that:
> + * 0xa7000000..0xA8000000 is used by bootloader, when kernel boot up,
> + * it is available for kernel usage. This region is not suggested to
> + * be used by kernel features like ramoops, suspend resume etc.
> + */
> +
> + /*
> + * Firmware related regions, bootlader will possible reserve parts of
> + * region from 0x80000000..0x8a800000.
> + */
> + aop_image_mem: aop-image-region@81c00000 {
> + reg = <0x0 0x81c00000 0x0 0x60000>;
> + no-map;
> + };
> +
> + aop_cmd_db_mem: aop-cmd-db-region@81c60000 {
> + compatible = "qcom,cmd-db";
> + reg = <0x0 0x81c60000 0x0 0x20000>;
> + no-map;
> + };
> +
> + aop_config_mem: aop-config-region@81c80000 {
> + no-map;
> + reg = <0x0 0x81c80000 0x0 0x20000>;
> + };
> +
> + smem_mem: smem-region@81d00000 {
> + compatible = "qcom,smem";
> + reg = <0x0 0x81d00000 0x0 0x200000>;
> + hwlocks = <&tcsr_mutex 3>;
> + no-map;
> + };
> +
> + adsp_mhi_mem: adsp-mhi-region@81f00000 {
> + reg = <0x0 0x81f00000 0x0 0x20000>;
> + no-map;
> + };
> +
> + /* PIL region */
> + mpss_mem: mpss-region@8a800000 {
> + reg = <0x0 0x8a800000 0x0 0x10800000>;
> + no-map;
> + };
> +
> + q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 {
> + reg = <0x0 0x9b000000 0x0 0x80000>;
> + no-map;
> + };
> +
> + ipa_fw_mem: ipa-fw-region@9b080000 {
> + reg = <0x0 0x9b080000 0x0 0x10000>;
> + no-map;
> + };
> +
> + ipa_gsi_mem: ipa-gsi-region@9b090000 {
> + reg = <0x0 0x9b090000 0x0 0xa000>;
> + no-map;
> + };
> +
> + gpu_micro_code_mem: gpu-micro-code-region@9b09a000 {
> + reg = <0x0 0x9b09a000 0x0 0x2000>;
> + no-map;
> + };
> +
> + spss_region_mem: spss-region@9b100000 {
> + reg = <0x0 0x9b100000 0x0 0x180000>;
> + no-map;
> + };
> +
> + spu_secure_shared_memory_mem: spu-secure-shared-memory-region@9b280000 {
> + reg = <0x0 0x9b280000 0x0 0x80000>;
> + no-map;
> + };
> +
> + camera_mem: camera-region@9b300000 {
> + reg = <0x0 0x9b300000 0x0 0x800000>;
> + no-map;
> + };
> +
> + video_mem: video-region@9bb00000 {
> + reg = <0x0 0x9bb00000 0x0 0x700000>;
> + no-map;
> + };
> +
> + cvp_mem: cvp-region@9c200000 {
> + reg = <0x0 0x9c200000 0x0 0x700000>;
> + no-map;
> + };
> +
> + cdsp_mem: cdsp-region@9c900000 {
> + reg = <0x0 0x9c900000 0x0 0x2000000>;
> + no-map;
> + };
> +
> + q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 {
> + reg = <0x0 0x9e900000 0x0 0x80000>;
> + no-map;
> + };
> +
> + q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 {
> + reg = <0x0 0x9e980000 0x0 0x80000>;
> + no-map;
> + };
> +
> + adspslpi_mem: adspslpi-region@9ea00000 {
> + reg = <0x0 0x9ea00000 0x0 0x4080000>;
> + no-map;
> + };
> +
> + /*
> + * Firmware related regions, bootlader will possible reserve parts of
Nit: bootloader will possibly...
> + * region from 0xd8000000..0x100000000.
> + */
> + mpss_dsm_mem: mpss_dsm_region@d4d00000 {
> + reg = <0x0 0xd4d00000 0x0 0x3300000>;
> + no-map;
> + };
> + };
> +};
> --
> 2.25.1
>
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v6 RESEND 4/4] arm64: dts: qcom: aim300: add AIM300 AIoT
2024-04-01 9:38 ` [PATCH v6 RESEND 4/4] arm64: dts: qcom: aim300: add AIM300 AIoT Tengfei Fan
@ 2024-04-01 19:22 ` Dmitry Baryshkov
2024-04-02 2:26 ` Tengfei Fan
0 siblings, 1 reply; 10+ messages in thread
From: Dmitry Baryshkov @ 2024-04-01 19:22 UTC (permalink / raw)
To: Tengfei Fan
Cc: andersson, konrad.dybcio, robh, krzysztof.kozlowski+dt, conor+dt,
keescook, tony.luck, gpiccoli, linux-arm-msm, devicetree,
linux-kernel, linux-hardening, kernel, Qiang Yu, Ziyue Zhang
On Mon, 1 Apr 2024 at 12:40, Tengfei Fan <quic_tengfan@quicinc.com> wrote:
>
> Add AIM300 AIoT Carrier board DTS support, including usb, UART, PCIe,
> I2C functions support.
> Here is a diagram of AIM300 AIoT Carrie Board and SoM
> +--------------------------------------------------+
> | AIM300 AIOT Carrie Board |
> | |
> | +-----------------+ |
> |power----->| Fixed regulator |---------+ |
> | +-----------------+ | |
> | | |
> | v VPH_PWR |
> | +----------------------------------------------+ |
> | | AIM300 SOM | | |
> | | |VPH_PWR | |
> | | v | |
> | | +-------+ +--------+ +------+ | |
> | | | UFS | | QCS8550| |PMIC | | |
> | | +-------+ +--------+ +------+ | |
> | | | |
> | +----------------------------------------------+ |
> | |
> | +----+ +------+ |
> | |USB | | UART | |
> | +----+ +------+ |
> +--------------------------------------------------+
>
> Co-developed-by: Qiang Yu <quic_qianyu@quicinc.com>
> Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
> Co-developed-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
> Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> .../boot/dts/qcom/qcs8550-aim300-aiot.dts | 384 ++++++++++++++++++
> 2 files changed, 385 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index 7d40ec5e7d21..02d9bc3bfce7 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -96,6 +96,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qcm6490-idp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb
> dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb
> dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb
> dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += qrb2210-rb1.dtb
> dtb-$(CONFIG_ARCH_QCOM) += qrb4210-rb2.dtb
> diff --git a/arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts b/arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts
> new file mode 100644
> index 000000000000..8188766c3d84
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts
> @@ -0,0 +1,384 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/leds/common.h>
> +#include "qcs8550-aim300.dtsi"
> +#include "pm8010.dtsi"
> +#include "pmr735d_a.dtsi"
> +#include "pmr735d_b.dtsi"
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. QCS8550 AIM300 AIOT";
> + compatible = "qcom,qcs8550-aim300-aiot", "qcom,qcs8550-aim300", "qcom,qcs8550",
> + "qcom,sm8550";
> +
> + aliases {
> + serial0 = &uart7;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> +
> + pinctrl-0 = <&volume_up_n>;
> + pinctrl-names = "default";
> +
> + key-volume-up {
> + label = "Volume Up";
> + debounce-interval = <15>;
> + gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>;
> + linux,code = <KEY_VOLUMEUP>;
> + linux,can-disable;
> + wakeup-source;
> + };
> + };
> +
> + pmic-glink {
> + compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + orientation-gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
> +
> + connector@0 {
> + compatible = "usb-c-connector";
> + reg = <0>;
> + power-role = "dual";
> + data-role = "dual";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + pmic_glink_hs_in: endpoint {
> + remote-endpoint = <&usb_1_dwc3_hs>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + pmic_glink_ss_in: endpoint {
> + remote-endpoint = <&redriver_ss_out>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> +
> + pmic_glink_sbu: endpoint {
> + remote-endpoint = <&fsa4480_sbu_mux>;
> + };
> + };
> + };
> + };
> + };
> +
> + vph_pwr: regulator-vph-pwr {
> + compatible = "regulator-fixed";
> + regulator-name = "vph_pwr";
> + regulator-min-microvolt = <3700000>;
> + regulator-max-microvolt = <3700000>;
> +
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +};
> +
> +&apps_rsc {
> + regulators-0 {
> + vdd-bob1-supply = <&vph_pwr>;
> + vdd-bob2-supply = <&vph_pwr>;
> + };
> +
> + regulators-3 {
> + vdd-s4-supply = <&vph_pwr>;
> + vdd-s5-supply = <&vph_pwr>;
> + };
> +
> + regulators-4 {
> + vdd-s4-supply = <&vph_pwr>;
> + };
> +
> + regulators-5 {
> + vdd-s1-supply = <&vph_pwr>;
> + vdd-s2-supply = <&vph_pwr>;
> + vdd-s3-supply = <&vph_pwr>;
> + vdd-s4-supply = <&vph_pwr>;
> + vdd-s5-supply = <&vph_pwr>;
> + vdd-s6-supply = <&vph_pwr>;
> + };
> +};
> +
> +&i2c_hub_2 {
> + status = "okay";
> +
> + typec-mux@42 {
> + compatible = "fcs,fsa4480";
> + reg = <0x42>;
> +
> + vcc-supply = <&vreg_bob1>;
> +
> + mode-switch;
> + orientation-switch;
> +
> + port {
> + fsa4480_sbu_mux: endpoint {
> + remote-endpoint = <&pmic_glink_sbu>;
> + };
> + };
> + };
> +
> + typec-retimer@1c {
> + compatible = "onnn,nb7vpq904m";
> + reg = <0x1c>;
> +
> + vcc-supply = <&vreg_l15b_1p8>;
> +
> + orientation-switch;
> + retimer-switch;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + redriver_ss_out: endpoint {
> + remote-endpoint = <&pmic_glink_ss_in>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + redriver_ss_in: endpoint {
> + data-lanes = <3 2 1 0>;
> + remote-endpoint = <&usb_dp_qmpphy_out>;
> + };
> + };
> + };
> + };
> +};
> +
> +&mdss_dsi0 {
> + vdda-supply = <&vreg_l3e_1p2>;
Is this wired on the carrier board or on the AIC300 SoM?
> + status = "okay";
> +
> + panel@0 {
> + compatible = "visionox,vtdr6130";
> + reg = <0>;
> +
> + pinctrl-0 = <&dsi_active>, <&te_active>;
> + pinctrl-1 = <&dsi_suspend>, <&te_suspend>;
> + pinctrl-names = "default", "sleep";
> +
> + reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>;
> +
> + vci-supply = <&vreg_l13b_3p0>;
> + vdd-supply = <&vreg_l11b_1p2>;
> + vddio-supply = <&vreg_l12b_1p8>;
> +
> + port {
> + panel0_in: endpoint {
> + remote-endpoint = <&mdss_dsi0_out>;
> + };
> + };
> + };
> +};
> +
> +&mdss_dsi0_out {
> + remote-endpoint = <&panel0_in>;
> + data-lanes = <0 1 2 3>;
> +};
> +
> +&mdss_dsi0_phy {
> + vdds-supply = <&vreg_l1e_0p88>;
This too
> + status = "okay";
> +};
> +
> +&pcie0 {
> + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
> + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
And this
> +
> + pinctrl-0 = <&pcie0_default_state>;
> + pinctrl-names = "default";
> +
> + status = "okay";
> +};
> +
> +&pcie0_phy {
> + vdda-phy-supply = <&vreg_l1e_0p88>;
> + vdda-pll-supply = <&vreg_l3e_1p2>;
You guess the question. I think I'll stop here. Please review your
changes here, which are really specific to the carrier board and which
apply to the SoM.
> +
> + status = "okay";
> +};
> +
> +&pcie_1_phy_aux_clk {
> + clock-frequency = <1000>;
> +};
> +
> +&pcie1 {
> + perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
> + wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
> +
> + pinctrl-0 = <&pcie1_default_state>;
> + pinctrl-names = "default";
> +
> + status = "okay";
> +};
> +
> +&pcie1_phy {
> + vdda-phy-supply = <&vreg_l3c_0p9>;
> + vdda-pll-supply = <&vreg_l3e_1p2>;
> + vdda-qref-supply = <&vreg_l1e_0p88>;
> +
> + status = "okay";
> +};
> +
> +&pm8550_gpios {
> + volume_up_n: volume-up-n-state {
> + pins = "gpio6";
> + function = "normal";
> + power-source = <1>;
> + bias-pull-up;
> + input-enable;
> + };
> +};
> +
> +&pm8550b_eusb2_repeater {
> + vdd18-supply = <&vreg_l15b_1p8>;
> + vdd3-supply = <&vreg_l5b_3p1>;
> +};
> +
> +
> +&pon_pwrkey {
> + status = "okay";
> +};
> +
> +&pon_resin {
> + linux,code = <KEY_VOLUMEDOWN>;
> +
> + status = "okay";
> +};
> +
> +&qupv3_id_0 {
> + status = "okay";
> +};
> +
> +&remoteproc_adsp {
> + firmware-name = "qcom/qcs8550/adsp.mbn",
> + "qcom/qcs8550/adsp_dtbs.elf";
> + status = "okay";
> +};
> +
> +&remoteproc_cdsp {
> + firmware-name = "qcom/qcs8550/cdsp.mbn",
> + "qcom/qcs8550/cdsp_dtbs.elf";
> + status = "okay";
> +};
> +
> +&sleep_clk {
> + clock-frequency = <32000>;
> +};
> +
> +&swr1 {
> + status = "okay";
> +};
> +
> +&swr2 {
> + status = "okay";
> +};
> +
> +&tlmm {
> + gpio-reserved-ranges = <32 8>;
> +
> + dsi_active: dsi-active-state {
> + pins = "gpio133";
> + function = "gpio";
> + drive-strength = <8>;
> + bias-disable;
> + };
> +
> + dsi_suspend: dsi-suspend-state {
> + pins = "gpio133";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + te_active: te-active-state {
> + pins = "gpio86";
> + function = "mdp_vsync";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + te_suspend: te-suspend-state {
> + pins = "gpio86";
> + function = "mdp_vsync";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +};
> +
> +&uart7 {
> + status = "okay";
> +};
> +
> +&usb_1 {
> + status = "okay";
> +};
> +
> +&usb_1_dwc3 {
> + dr_mode = "otg";
> + usb-role-switch;
> +};
> +
> +&usb_1_dwc3_hs {
> + remote-endpoint = <&pmic_glink_hs_in>;
> +};
> +
> +&usb_1_dwc3_ss {
> + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
> +};
> +
> +&usb_1_hsphy {
> + phys = <&pm8550b_eusb2_repeater>;
> +
> + vdd-supply = <&vreg_l1e_0p88>;
> + vdda12-supply = <&vreg_l3e_1p2>;
> +
> + status = "okay";
> +};
> +
> +&usb_dp_qmpphy {
> + vdda-phy-supply = <&vreg_l3e_1p2>;
> + vdda-pll-supply = <&vreg_l3f_0p88>;
> +
> + orientation-switch;
> +
> + status = "okay";
> +};
> +
> +&usb_dp_qmpphy_out {
> + remote-endpoint = <&redriver_ss_in>;
> +};
> +
> +&usb_dp_qmpphy_usb_ss_in {
> + remote-endpoint = <&usb_1_dwc3_ss>;
> +};
> +
> +&xo_board {
> + clock-frequency = <76800000>;
> +};
> --
> 2.25.1
>
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v6 RESEND 4/4] arm64: dts: qcom: aim300: add AIM300 AIoT
2024-04-01 19:22 ` Dmitry Baryshkov
@ 2024-04-02 2:26 ` Tengfei Fan
0 siblings, 0 replies; 10+ messages in thread
From: Tengfei Fan @ 2024-04-02 2:26 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: andersson, konrad.dybcio, robh, krzysztof.kozlowski+dt, conor+dt,
keescook, tony.luck, gpiccoli, linux-arm-msm, devicetree,
linux-kernel, linux-hardening, kernel, Qiang Yu, Ziyue Zhang
On 4/2/2024 3:22 AM, Dmitry Baryshkov wrote:
> On Mon, 1 Apr 2024 at 12:40, Tengfei Fan <quic_tengfan@quicinc.com> wrote:
>>
>> Add AIM300 AIoT Carrier board DTS support, including usb, UART, PCIe,
>> I2C functions support.
>> Here is a diagram of AIM300 AIoT Carrie Board and SoM
>> +--------------------------------------------------+
>> | AIM300 AIOT Carrie Board |
>> | |
>> | +-----------------+ |
>> |power----->| Fixed regulator |---------+ |
>> | +-----------------+ | |
>> | | |
>> | v VPH_PWR |
>> | +----------------------------------------------+ |
>> | | AIM300 SOM | | |
>> | | |VPH_PWR | |
>> | | v | |
>> | | +-------+ +--------+ +------+ | |
>> | | | UFS | | QCS8550| |PMIC | | |
>> | | +-------+ +--------+ +------+ | |
>> | | | |
>> | +----------------------------------------------+ |
>> | |
>> | +----+ +------+ |
>> | |USB | | UART | |
>> | +----+ +------+ |
>> +--------------------------------------------------+
>>
>> Co-developed-by: Qiang Yu <quic_qianyu@quicinc.com>
>> Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
>> Co-developed-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
>> Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/Makefile | 1 +
>> .../boot/dts/qcom/qcs8550-aim300-aiot.dts | 384 ++++++++++++++++++
>> 2 files changed, 385 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts
>>
>> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
>> index 7d40ec5e7d21..02d9bc3bfce7 100644
>> --- a/arch/arm64/boot/dts/qcom/Makefile
>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>> @@ -96,6 +96,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qcm6490-idp.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb
>> +dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += qrb2210-rb1.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += qrb4210-rb2.dtb
>> diff --git a/arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts b/arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts
>> new file mode 100644
>> index 000000000000..8188766c3d84
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts
>> @@ -0,0 +1,384 @@
>> +// SPDX-License-Identifier: BSD-3-Clause
>> +/*
>> + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include <dt-bindings/leds/common.h>
>> +#include "qcs8550-aim300.dtsi"
>> +#include "pm8010.dtsi"
>> +#include "pmr735d_a.dtsi"
>> +#include "pmr735d_b.dtsi"
>> +
>> +/ {
>> + model = "Qualcomm Technologies, Inc. QCS8550 AIM300 AIOT";
>> + compatible = "qcom,qcs8550-aim300-aiot", "qcom,qcs8550-aim300", "qcom,qcs8550",
>> + "qcom,sm8550";
>> +
>> + aliases {
>> + serial0 = &uart7;
>> + };
>> +
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> + };
>> +
>> + gpio-keys {
>> + compatible = "gpio-keys";
>> +
>> + pinctrl-0 = <&volume_up_n>;
>> + pinctrl-names = "default";
>> +
>> + key-volume-up {
>> + label = "Volume Up";
>> + debounce-interval = <15>;
>> + gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>;
>> + linux,code = <KEY_VOLUMEUP>;
>> + linux,can-disable;
>> + wakeup-source;
>> + };
>> + };
>> +
>> + pmic-glink {
>> + compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + orientation-gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
>> +
>> + connector@0 {
>> + compatible = "usb-c-connector";
>> + reg = <0>;
>> + power-role = "dual";
>> + data-role = "dual";
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> +
>> + pmic_glink_hs_in: endpoint {
>> + remote-endpoint = <&usb_1_dwc3_hs>;
>> + };
>> + };
>> +
>> + port@1 {
>> + reg = <1>;
>> +
>> + pmic_glink_ss_in: endpoint {
>> + remote-endpoint = <&redriver_ss_out>;
>> + };
>> + };
>> +
>> + port@2 {
>> + reg = <2>;
>> +
>> + pmic_glink_sbu: endpoint {
>> + remote-endpoint = <&fsa4480_sbu_mux>;
>> + };
>> + };
>> + };
>> + };
>> + };
>> +
>> + vph_pwr: regulator-vph-pwr {
>> + compatible = "regulator-fixed";
>> + regulator-name = "vph_pwr";
>> + regulator-min-microvolt = <3700000>;
>> + regulator-max-microvolt = <3700000>;
>> +
>> + regulator-always-on;
>> + regulator-boot-on;
>> + };
>> +};
>> +
>> +&apps_rsc {
>> + regulators-0 {
>> + vdd-bob1-supply = <&vph_pwr>;
>> + vdd-bob2-supply = <&vph_pwr>;
>> + };
>> +
>> + regulators-3 {
>> + vdd-s4-supply = <&vph_pwr>;
>> + vdd-s5-supply = <&vph_pwr>;
>> + };
>> +
>> + regulators-4 {
>> + vdd-s4-supply = <&vph_pwr>;
>> + };
>> +
>> + regulators-5 {
>> + vdd-s1-supply = <&vph_pwr>;
>> + vdd-s2-supply = <&vph_pwr>;
>> + vdd-s3-supply = <&vph_pwr>;
>> + vdd-s4-supply = <&vph_pwr>;
>> + vdd-s5-supply = <&vph_pwr>;
>> + vdd-s6-supply = <&vph_pwr>;
>> + };
>> +};
>> +
>> +&i2c_hub_2 {
>> + status = "okay";
>> +
>> + typec-mux@42 {
>> + compatible = "fcs,fsa4480";
>> + reg = <0x42>;
>> +
>> + vcc-supply = <&vreg_bob1>;
>> +
>> + mode-switch;
>> + orientation-switch;
>> +
>> + port {
>> + fsa4480_sbu_mux: endpoint {
>> + remote-endpoint = <&pmic_glink_sbu>;
>> + };
>> + };
>> + };
>> +
>> + typec-retimer@1c {
>> + compatible = "onnn,nb7vpq904m";
>> + reg = <0x1c>;
>> +
>> + vcc-supply = <&vreg_l15b_1p8>;
>> +
>> + orientation-switch;
>> + retimer-switch;
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> +
>> + redriver_ss_out: endpoint {
>> + remote-endpoint = <&pmic_glink_ss_in>;
>> + };
>> + };
>> +
>> + port@1 {
>> + reg = <1>;
>> +
>> + redriver_ss_in: endpoint {
>> + data-lanes = <3 2 1 0>;
>> + remote-endpoint = <&usb_dp_qmpphy_out>;
>> + };
>> + };
>> + };
>> + };
>> +};
>> +
>> +&mdss_dsi0 {
>> + vdda-supply = <&vreg_l3e_1p2>;
>
> Is this wired on the carrier board or on the AIC300 SoM?
I checked schematic diagram, this should be on the AIM300 SoM.
>
>> + status = "okay";
>> +
>> + panel@0 {
>> + compatible = "visionox,vtdr6130";
>> + reg = <0>;
>> +
>> + pinctrl-0 = <&dsi_active>, <&te_active>;
>> + pinctrl-1 = <&dsi_suspend>, <&te_suspend>;
>> + pinctrl-names = "default", "sleep";
>> +
>> + reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>;
>> +
>> + vci-supply = <&vreg_l13b_3p0>;
>> + vdd-supply = <&vreg_l11b_1p2>;
>> + vddio-supply = <&vreg_l12b_1p8>;
>> +
>> + port {
>> + panel0_in: endpoint {
>> + remote-endpoint = <&mdss_dsi0_out>;
>> + };
>> + };
>> + };
>> +};
>> +
>> +&mdss_dsi0_out {
>> + remote-endpoint = <&panel0_in>;
>> + data-lanes = <0 1 2 3>;
>> +};
>> +
>> +&mdss_dsi0_phy {
>> + vdds-supply = <&vreg_l1e_0p88>;
>
> This too
This also should be on the AIM300 SoM.
>
>> + status = "okay";
>> +};
>> +
>> +&pcie0 {
>> + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
>> + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
>
> And this
I checked schematic diagram, this should be on the AIM300 SoM.
>
>> +
>> + pinctrl-0 = <&pcie0_default_state>;
>> + pinctrl-names = "default";
>> +
>> + status = "okay";
>> +};
>> +
>> +&pcie0_phy {
>> + vdda-phy-supply = <&vreg_l1e_0p88>;
>> + vdda-pll-supply = <&vreg_l3e_1p2>;
>
> You guess the question. I think I'll stop here. Please review your
> changes here, which are really specific to the carrier board and which
> apply to the SoM.
I will review this change totally, then I will distinguish all these
nodes which are on the carrier board and which are on the AIM300 SoM.
Then I will update change series.
>
>> +
>> + status = "okay";
>> +};
>> +
>> +&pcie_1_phy_aux_clk {
>> + clock-frequency = <1000>;
>> +};
>> +
>> +&pcie1 {
>> + perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
>> + wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
>> +
>> + pinctrl-0 = <&pcie1_default_state>;
>> + pinctrl-names = "default";
>> +
>> + status = "okay";
>> +};
>> +
>> +&pcie1_phy {
>> + vdda-phy-supply = <&vreg_l3c_0p9>;
>> + vdda-pll-supply = <&vreg_l3e_1p2>;
>> + vdda-qref-supply = <&vreg_l1e_0p88>;
>> +
>> + status = "okay";
>> +};
>> +
>> +&pm8550_gpios {
>> + volume_up_n: volume-up-n-state {
>> + pins = "gpio6";
>> + function = "normal";
>> + power-source = <1>;
>> + bias-pull-up;
>> + input-enable;
>> + };
>> +};
>> +
>> +&pm8550b_eusb2_repeater {
>> + vdd18-supply = <&vreg_l15b_1p8>;
>> + vdd3-supply = <&vreg_l5b_3p1>;
>> +};
>> +
>> +
>> +&pon_pwrkey {
>> + status = "okay";
>> +};
>> +
>> +&pon_resin {
>> + linux,code = <KEY_VOLUMEDOWN>;
>> +
>> + status = "okay";
>> +};
>> +
>> +&qupv3_id_0 {
>> + status = "okay";
>> +};
>> +
>> +&remoteproc_adsp {
>> + firmware-name = "qcom/qcs8550/adsp.mbn",
>> + "qcom/qcs8550/adsp_dtbs.elf";
>> + status = "okay";
>> +};
>> +
>> +&remoteproc_cdsp {
>> + firmware-name = "qcom/qcs8550/cdsp.mbn",
>> + "qcom/qcs8550/cdsp_dtbs.elf";
>> + status = "okay";
>> +};
>> +
>> +&sleep_clk {
>> + clock-frequency = <32000>;
>> +};
>> +
>> +&swr1 {
>> + status = "okay";
>> +};
>> +
>> +&swr2 {
>> + status = "okay";
>> +};
>> +
>> +&tlmm {
>> + gpio-reserved-ranges = <32 8>;
>> +
>> + dsi_active: dsi-active-state {
>> + pins = "gpio133";
>> + function = "gpio";
>> + drive-strength = <8>;
>> + bias-disable;
>> + };
>> +
>> + dsi_suspend: dsi-suspend-state {
>> + pins = "gpio133";
>> + function = "gpio";
>> + drive-strength = <2>;
>> + bias-pull-down;
>> + };
>> +
>> + te_active: te-active-state {
>> + pins = "gpio86";
>> + function = "mdp_vsync";
>> + drive-strength = <2>;
>> + bias-pull-down;
>> + };
>> +
>> + te_suspend: te-suspend-state {
>> + pins = "gpio86";
>> + function = "mdp_vsync";
>> + drive-strength = <2>;
>> + bias-pull-down;
>> + };
>> +};
>> +
>> +&uart7 {
>> + status = "okay";
>> +};
>> +
>> +&usb_1 {
>> + status = "okay";
>> +};
>> +
>> +&usb_1_dwc3 {
>> + dr_mode = "otg";
>> + usb-role-switch;
>> +};
>> +
>> +&usb_1_dwc3_hs {
>> + remote-endpoint = <&pmic_glink_hs_in>;
>> +};
>> +
>> +&usb_1_dwc3_ss {
>> + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
>> +};
>> +
>> +&usb_1_hsphy {
>> + phys = <&pm8550b_eusb2_repeater>;
>> +
>> + vdd-supply = <&vreg_l1e_0p88>;
>> + vdda12-supply = <&vreg_l3e_1p2>;
>> +
>> + status = "okay";
>> +};
>> +
>> +&usb_dp_qmpphy {
>> + vdda-phy-supply = <&vreg_l3e_1p2>;
>> + vdda-pll-supply = <&vreg_l3f_0p88>;
>> +
>> + orientation-switch;
>> +
>> + status = "okay";
>> +};
>> +
>> +&usb_dp_qmpphy_out {
>> + remote-endpoint = <&redriver_ss_in>;
>> +};
>> +
>> +&usb_dp_qmpphy_usb_ss_in {
>> + remote-endpoint = <&usb_1_dwc3_ss>;
>> +};
>> +
>> +&xo_board {
>> + clock-frequency = <76800000>;
>> +};
>> --
>> 2.25.1
>>
>>
>
>
--
Thx and BRs,
Tengfei Fan
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v6 RESEND 0/4] arm64: qcom: add AIM300 AIoT board support
2024-04-01 15:54 ` [PATCH v6 RESEND 0/4] arm64: qcom: add AIM300 AIoT board support Trilok Soni
@ 2024-04-02 2:29 ` Tengfei Fan
0 siblings, 0 replies; 10+ messages in thread
From: Tengfei Fan @ 2024-04-02 2:29 UTC (permalink / raw)
To: Trilok Soni, andersson, konrad.dybcio, robh,
krzysztof.kozlowski+dt, conor+dt
Cc: keescook, tony.luck, gpiccoli, linux-arm-msm, devicetree,
linux-kernel, linux-hardening, kernel
On 4/1/2024 11:54 PM, Trilok Soni wrote:
> On 4/1/2024 2:38 AM, Tengfei Fan wrote:
>> Here is a diagram of AIM300 AIoT Carrie Board and SoM
>> +--------------------------------------------------+
>> | AIM300 AIOT Carrie Board |
>
> spellcheck
>
> s/Carrie/Carrier ?
Thanks Trilok for pointing out the problem here, I will correct this
typo in next version patch series.
>
--
Thx and BRs,
Tengfei Fan
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2024-04-02 2:29 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-04-01 9:38 [PATCH v6 RESEND 0/4] arm64: qcom: add AIM300 AIoT board support Tengfei Fan
2024-04-01 9:38 ` [PATCH v6 RESEND 1/4] dt-bindings: arm: qcom: Document QCS8550 SoC and the AIM300 AIoT board Tengfei Fan
2024-04-01 9:38 ` [PATCH v6 RESEND 2/4] arm64: dts: qcom: qcs8550: introduce qcs8550 dtsi Tengfei Fan
2024-04-01 19:13 ` Dmitry Baryshkov
2024-04-01 9:38 ` [PATCH v6 RESEND 3/4] arm64: dts: qcom: add base AIM300 dtsi Tengfei Fan
2024-04-01 9:38 ` [PATCH v6 RESEND 4/4] arm64: dts: qcom: aim300: add AIM300 AIoT Tengfei Fan
2024-04-01 19:22 ` Dmitry Baryshkov
2024-04-02 2:26 ` Tengfei Fan
2024-04-01 15:54 ` [PATCH v6 RESEND 0/4] arm64: qcom: add AIM300 AIoT board support Trilok Soni
2024-04-02 2:29 ` Tengfei Fan
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