Re: [PATCH v5 15/19] clk: mediatek: Add MT8188 vppsys0 clock support

Re: [PATCH v5 15/19] clk: mediatek: Add MT8188 vppsys0 clock support

[Matthias Brugger]

On 19/01/2023 13:48, Garmin.Chang wrote:
> Add MT8188 vppsys0 clock controller which provides clock gate
> controller for Video Processor Pipe.
> 
> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>

Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>

> ---
>   drivers/clk/mediatek/Makefile          |   3 +-
>   drivers/clk/mediatek/clk-mt8188-vpp0.c | 143 +++++++++++++++++++++++++
>   2 files changed, 145 insertions(+), 1 deletion(-)
>   create mode 100644 drivers/clk/mediatek/clk-mt8188-vpp0.c
> 
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index 22a3840160fc..48deecc6b520 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -87,7 +87,8 @@ obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o
>   				   clk-mt8188-peri_ao.o clk-mt8188-infra_ao.o \
>   				   clk-mt8188-cam.o clk-mt8188-ccu.o clk-mt8188-img.o \
>   				   clk-mt8188-ipe.o clk-mt8188-mfg.o clk-mt8188-vdec.o \
> -				   clk-mt8188-vdo0.o clk-mt8188-vdo1.o clk-mt8188-venc.o
> +				   clk-mt8188-vdo0.o clk-mt8188-vdo1.o clk-mt8188-venc.o \
> +				   clk-mt8188-vpp0.o
>   obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
>   obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
>   obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> diff --git a/drivers/clk/mediatek/clk-mt8188-vpp0.c b/drivers/clk/mediatek/clk-mt8188-vpp0.c
> new file mode 100644
> index 000000000000..e7b46142d653
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8188-vpp0.c
> @@ -0,0 +1,143 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +//
> +// Copyright (c) 2022 MediaTek Inc.
> +// Author: Garmin Chang <garmin.chang@mediatek.com>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> +
> +#include "clk-gate.h"
> +#include "clk-mtk.h"
> +
> +static const struct mtk_gate_regs vpp0_0_cg_regs = {
> +	.set_ofs = 0x24,
> +	.clr_ofs = 0x28,
> +	.sta_ofs = 0x20,
> +};
> +
> +static const struct mtk_gate_regs vpp0_1_cg_regs = {
> +	.set_ofs = 0x30,
> +	.clr_ofs = 0x34,
> +	.sta_ofs = 0x2c,
> +};
> +
> +static const struct mtk_gate_regs vpp0_2_cg_regs = {
> +	.set_ofs = 0x3c,
> +	.clr_ofs = 0x40,
> +	.sta_ofs = 0x38,
> +};
> +
> +#define GATE_VPP0_0(_id, _name, _parent, _shift)			\
> +	GATE_MTK(_id, _name, _parent, &vpp0_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +#define GATE_VPP0_1(_id, _name, _parent, _shift)			\
> +	GATE_MTK(_id, _name, _parent, &vpp0_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +#define GATE_VPP0_2(_id, _name, _parent, _shift)			\
> +	GATE_MTK(_id, _name, _parent, &vpp0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +static const struct mtk_gate vpp0_clks[] = {
> +	/* VPP0_0 */
> +	GATE_VPP0_0(CLK_VPP0_MDP_FG, "vpp0_mdp_fg", "top_vpp", 1),
> +	GATE_VPP0_0(CLK_VPP0_STITCH, "vpp0_stitch", "top_vpp", 2),
> +	GATE_VPP0_0(CLK_VPP0_PADDING, "vpp0_padding", "top_vpp", 7),
> +	GATE_VPP0_0(CLK_VPP0_MDP_TCC, "vpp0_mdp_tcc", "top_vpp", 8),
> +	GATE_VPP0_0(CLK_VPP0_WARP0_ASYNC_TX, "vpp0_warp0_async_tx", "top_vpp", 10),
> +	GATE_VPP0_0(CLK_VPP0_WARP1_ASYNC_TX, "vpp0_warp1_async_tx", "top_vpp", 11),
> +	GATE_VPP0_0(CLK_VPP0_MUTEX, "vpp0_mutex", "top_vpp", 13),
> +	GATE_VPP0_0(CLK_VPP02VPP1_RELAY, "vpp02vpp1_relay", "top_vpp", 14),
> +	GATE_VPP0_0(CLK_VPP0_VPP12VPP0_ASYNC, "vpp0_vpp12vpp0_async", "top_vpp", 15),
> +	GATE_VPP0_0(CLK_VPP0_MMSYSRAM_TOP, "vpp0_mmsysram_top", "top_vpp", 16),
> +	GATE_VPP0_0(CLK_VPP0_MDP_AAL, "vpp0_mdp_aal", "top_vpp", 17),
> +	GATE_VPP0_0(CLK_VPP0_MDP_RSZ, "vpp0_mdp_rsz", "top_vpp", 18),
> +	/* VPP0_1 */
> +	GATE_VPP0_1(CLK_VPP0_SMI_COMMON_MMSRAM, "vpp0_smi_common_mmsram", "top_vpp", 0),
> +	GATE_VPP0_1(CLK_VPP0_GALS_VDO0_LARB0_MMSRAM, "vpp0_gals_vdo0_larb0_mmsram", "top_vpp", 1),
> +	GATE_VPP0_1(CLK_VPP0_GALS_VDO0_LARB1_MMSRAM, "vpp0_gals_vdo0_larb1_mmsram", "top_vpp", 2),
> +	GATE_VPP0_1(CLK_VPP0_GALS_VENCSYS_MMSRAM, "vpp0_gals_vencsys_mmsram", "top_vpp", 3),
> +	GATE_VPP0_1(CLK_VPP0_GALS_VENCSYS_CORE1_MMSRAM,
> +		    "vpp0_gals_vencsys_core1_mmsram", "top_vpp", 4),
> +	GATE_VPP0_1(CLK_VPP0_GALS_INFRA_MMSRAM, "vpp0_gals_infra_mmsram", "top_vpp", 5),
> +	GATE_VPP0_1(CLK_VPP0_GALS_CAMSYS_MMSRAM, "vpp0_gals_camsys_mmsram", "top_vpp", 6),
> +	GATE_VPP0_1(CLK_VPP0_GALS_VPP1_LARB5_MMSRAM, "vpp0_gals_vpp1_larb5_mmsram", "top_vpp", 7),
> +	GATE_VPP0_1(CLK_VPP0_GALS_VPP1_LARB6_MMSRAM, "vpp0_gals_vpp1_larb6_mmsram", "top_vpp", 8),
> +	GATE_VPP0_1(CLK_VPP0_SMI_REORDER_MMSRAM, "vpp0_smi_reorder_mmsram", "top_vpp", 9),
> +	GATE_VPP0_1(CLK_VPP0_SMI_IOMMU, "vpp0_smi_iommu", "top_vpp", 10),
> +	GATE_VPP0_1(CLK_VPP0_GALS_IMGSYS_CAMSYS, "vpp0_gals_imgsys_camsys", "top_vpp", 11),
> +	GATE_VPP0_1(CLK_VPP0_MDP_RDMA, "vpp0_mdp_rdma", "top_vpp", 12),
> +	GATE_VPP0_1(CLK_VPP0_MDP_WROT, "vpp0_mdp_wrot", "top_vpp", 13),
> +	GATE_VPP0_1(CLK_VPP0_GALS_EMI0_EMI1, "vpp0_gals_emi0_emi1", "top_vpp", 16),
> +	GATE_VPP0_1(CLK_VPP0_SMI_SUB_COMMON_REORDER, "vpp0_smi_sub_common_reorder", "top_vpp", 17),
> +	GATE_VPP0_1(CLK_VPP0_SMI_RSI, "vpp0_smi_rsi", "top_vpp", 18),
> +	GATE_VPP0_1(CLK_VPP0_SMI_COMMON_LARB4, "vpp0_smi_common_larb4", "top_vpp", 19),
> +	GATE_VPP0_1(CLK_VPP0_GALS_VDEC_VDEC_CORE1, "vpp0_gals_vdec_vdec_core1", "top_vpp", 20),
> +	GATE_VPP0_1(CLK_VPP0_GALS_VPP1_WPESYS, "vpp0_gals_vpp1_wpesys", "top_vpp", 21),
> +	GATE_VPP0_1(CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1,
> +		    "vpp0_gals_vdo0_vdo1_vencsys_core1", "top_vpp", 22),
> +	GATE_VPP0_1(CLK_VPP0_FAKE_ENG, "vpp0_fake_eng", "top_vpp", 23),
> +	GATE_VPP0_1(CLK_VPP0_MDP_HDR, "vpp0_mdp_hdr", "top_vpp", 24),
> +	GATE_VPP0_1(CLK_VPP0_MDP_TDSHP, "vpp0_mdp_tdshp", "top_vpp", 25),
> +	GATE_VPP0_1(CLK_VPP0_MDP_COLOR, "vpp0_mdp_color", "top_vpp", 26),
> +	GATE_VPP0_1(CLK_VPP0_MDP_OVL, "vpp0_mdp_ovl", "top_vpp", 27),
> +	GATE_VPP0_1(CLK_VPP0_DSIP_RDMA, "vpp0_dsip_rdma", "top_vpp", 28),
> +	GATE_VPP0_1(CLK_VPP0_DISP_WDMA, "vpp0_disp_wdma", "top_vpp", 29),
> +	GATE_VPP0_1(CLK_VPP0_MDP_HMS, "vpp0_mdp_hms", "top_vpp", 30),
> +	/* VPP0_2 */
> +	GATE_VPP0_2(CLK_VPP0_WARP0_RELAY, "vpp0_warp0_relay", "top_wpe_vpp", 0),
> +	GATE_VPP0_2(CLK_VPP0_WARP0_ASYNC, "vpp0_warp0_async", "top_wpe_vpp", 1),
> +	GATE_VPP0_2(CLK_VPP0_WARP1_RELAY, "vpp0_warp1_relay", "top_wpe_vpp", 2),
> +	GATE_VPP0_2(CLK_VPP0_WARP1_ASYNC, "vpp0_warp1_async", "top_wpe_vpp", 3),
> +};
> +
> +static int clk_mt8188_vpp0_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct device_node *node = dev->parent->of_node;
> +	struct clk_hw_onecell_data *clk_data;
> +	int r;
> +
> +	clk_data = mtk_alloc_clk_data(CLK_VPP0_NR_CLK);
> +	if (!clk_data)
> +		return -ENOMEM;
> +
> +	r = mtk_clk_register_gates(node, vpp0_clks, ARRAY_SIZE(vpp0_clks), clk_data);
> +	if (r)
> +		goto free_vpp0_data;
> +
> +	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
> +	if (r)
> +		goto unregister_gates;
> +
> +	platform_set_drvdata(pdev, clk_data);
> +
> +	return r;
> +
> +unregister_gates:
> +	mtk_clk_unregister_gates(vpp0_clks, ARRAY_SIZE(vpp0_clks), clk_data);
> +free_vpp0_data:
> +	mtk_free_clk_data(clk_data);
> +	return r;
> +}
> +
> +static int clk_mt8188_vpp0_remove(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct device_node *node = dev->parent->of_node;
> +	struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
> +
> +	of_clk_del_provider(node);
> +	mtk_clk_unregister_gates(vpp0_clks, ARRAY_SIZE(vpp0_clks), clk_data);
> +	mtk_free_clk_data(clk_data);
> +
> +	return 0;
> +}
> +
> +static struct platform_driver clk_mt8188_vpp0_drv = {
> +	.probe = clk_mt8188_vpp0_probe,
> +	.remove = clk_mt8188_vpp0_remove,
> +	.driver = {
> +		.name = "clk-mt8188-vpp0",
> +	},
> +};
> +builtin_platform_driver(clk_mt8188_vpp0_drv);

Re: [PATCH v5 16/19] clk: mediatek: Add MT8188 vppsys1 clock support

[Matthias Brugger]

On 19/01/2023 13:48, Garmin.Chang wrote:
> Add MT8188 vppsys1 clock controller which provides clock gate
> controller for Video Processor Pipe.
> 
> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>

Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>

> ---
>   drivers/clk/mediatek/Makefile          |   2 +-
>   drivers/clk/mediatek/clk-mt8188-vpp1.c | 138 +++++++++++++++++++++++++
>   2 files changed, 139 insertions(+), 1 deletion(-)
>   create mode 100644 drivers/clk/mediatek/clk-mt8188-vpp1.c
> 
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index 48deecc6b520..37663de293bf 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -88,7 +88,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o
>   				   clk-mt8188-cam.o clk-mt8188-ccu.o clk-mt8188-img.o \
>   				   clk-mt8188-ipe.o clk-mt8188-mfg.o clk-mt8188-vdec.o \
>   				   clk-mt8188-vdo0.o clk-mt8188-vdo1.o clk-mt8188-venc.o \
> -				   clk-mt8188-vpp0.o
> +				   clk-mt8188-vpp0.o clk-mt8188-vpp1.o
>   obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
>   obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
>   obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> diff --git a/drivers/clk/mediatek/clk-mt8188-vpp1.c b/drivers/clk/mediatek/clk-mt8188-vpp1.c
> new file mode 100644
> index 000000000000..2bff3a52c93f
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8188-vpp1.c
> @@ -0,0 +1,138 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +//
> +// Copyright (c) 2022 MediaTek Inc.
> +// Author: Garmin Chang <garmin.chang@mediatek.com>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> +
> +#include "clk-gate.h"
> +#include "clk-mtk.h"
> +
> +static const struct mtk_gate_regs vpp1_0_cg_regs = {
> +	.set_ofs = 0x104,
> +	.clr_ofs = 0x108,
> +	.sta_ofs = 0x100,
> +};
> +
> +static const struct mtk_gate_regs vpp1_1_cg_regs = {
> +	.set_ofs = 0x114,
> +	.clr_ofs = 0x118,
> +	.sta_ofs = 0x110,
> +};
> +
> +#define GATE_VPP1_0(_id, _name, _parent, _shift)			\
> +	GATE_MTK(_id, _name, _parent, &vpp1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +#define GATE_VPP1_1(_id, _name, _parent, _shift)			\
> +	GATE_MTK(_id, _name, _parent, &vpp1_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +static const struct mtk_gate vpp1_clks[] = {
> +	/* VPP1_0 */
> +	GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_OVL, "vpp1_svpp1_mdp_ovl", "top_vpp", 0),
> +	GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_TCC, "vpp1_svpp1_mdp_tcc", "top_vpp", 1),
> +	GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_WROT, "vpp1_svpp1_mdp_wrot", "top_vpp", 2),
> +	GATE_VPP1_0(CLK_VPP1_SVPP1_VPP_PAD, "vpp1_svpp1_vpp_pad", "top_vpp", 3),
> +	GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_WROT, "vpp1_svpp2_mdp_wrot", "top_vpp", 4),
> +	GATE_VPP1_0(CLK_VPP1_SVPP2_VPP_PAD, "vpp1_svpp2_vpp_pad", "top_vpp", 5),
> +	GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_WROT, "vpp1_svpp3_mdp_wrot", "top_vpp", 6),
> +	GATE_VPP1_0(CLK_VPP1_SVPP3_VPP_PAD, "vpp1_svpp3_vpp_pad", "top_vpp", 7),
> +	GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_RDMA, "vpp1_svpp1_mdp_rdma", "top_vpp", 8),
> +	GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_FG, "vpp1_svpp1_mdp_fg", "top_vpp", 9),
> +	GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_RDMA, "vpp1_svpp2_mdp_rdma", "top_vpp", 10),
> +	GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_FG, "vpp1_svpp2_mdp_fg", "top_vpp", 11),
> +	GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_RDMA, "vpp1_svpp3_mdp_rdma", "top_vpp", 12),
> +	GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_FG, "vpp1_svpp3_mdp_fg", "top_vpp", 13),
> +	GATE_VPP1_0(CLK_VPP1_VPP_SPLIT, "vpp1_vpp_split", "top_vpp", 14),
> +	GATE_VPP1_0(CLK_VPP1_SVPP2_VDO0_DL_RELAY, "vpp1_svpp2_vdo0_dl_relay", "top_vpp", 15),
> +	GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_RSZ, "vpp1_svpp1_mdp_rsz", "top_vpp", 16),
> +	GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_TDSHP, "vpp1_svpp1_mdp_tdshp", "top_vpp", 17),
> +	GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_COLOR, "vpp1_svpp1_mdp_color", "top_vpp", 18),
> +	GATE_VPP1_0(CLK_VPP1_SVPP3_VDO1_DL_RELAY, "vpp1_svpp3_vdo1_dl_relay", "top_vpp", 19),
> +	GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_RSZ, "vpp1_svpp2_mdp_rsz", "top_vpp", 20),
> +	GATE_VPP1_0(CLK_VPP1_SVPP2_VPP_MERGE, "vpp1_svpp2_vpp_merge", "top_vpp", 21),
> +	GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_TDSHP, "vpp1_svpp2_mdp_tdshp", "top_vpp", 22),
> +	GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_COLOR, "vpp1_svpp2_mdp_color", "top_vpp", 23),
> +	GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_RSZ, "vpp1_svpp3_mdp_rsz", "top_vpp", 24),
> +	GATE_VPP1_0(CLK_VPP1_SVPP3_VPP_MERGE, "vpp1_svpp3_vpp_merge", "top_vpp", 25),
> +	GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_TDSHP, "vpp1_svpp3_mdp_tdshp", "top_vpp", 26),
> +	GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_COLOR, "vpp1_svpp3_mdp_color", "top_vpp", 27),
> +	GATE_VPP1_0(CLK_VPP1_GALS5, "vpp1_gals5", "top_vpp", 28),
> +	GATE_VPP1_0(CLK_VPP1_GALS6, "vpp1_gals6", "top_vpp", 29),
> +	GATE_VPP1_0(CLK_VPP1_LARB5, "vpp1_larb5", "top_vpp", 30),
> +	GATE_VPP1_0(CLK_VPP1_LARB6, "vpp1_larb6", "top_vpp", 31),
> +	/* VPP1_1 */
> +	GATE_VPP1_1(CLK_VPP1_SVPP1_MDP_HDR, "vpp1_svpp1_mdp_hdr", "top_vpp", 0),
> +	GATE_VPP1_1(CLK_VPP1_SVPP1_MDP_AAL, "vpp1_svpp1_mdp_aal", "top_vpp", 1),
> +	GATE_VPP1_1(CLK_VPP1_SVPP2_MDP_HDR, "vpp1_svpp2_mdp_hdr", "top_vpp", 2),
> +	GATE_VPP1_1(CLK_VPP1_SVPP2_MDP_AAL, "vpp1_svpp2_mdp_aal", "top_vpp", 3),
> +	GATE_VPP1_1(CLK_VPP1_SVPP3_MDP_HDR, "vpp1_svpp3_mdp_hdr", "top_vpp", 4),
> +	GATE_VPP1_1(CLK_VPP1_SVPP3_MDP_AAL, "vpp1_svpp3_mdp_aal", "top_vpp", 5),
> +	GATE_VPP1_1(CLK_VPP1_DISP_MUTEX, "vpp1_disp_mutex", "top_vpp", 7),
> +	GATE_VPP1_1(CLK_VPP1_SVPP2_VDO1_DL_RELAY, "vpp1_svpp2_vdo1_dl_relay", "top_vpp", 8),
> +	GATE_VPP1_1(CLK_VPP1_SVPP3_VDO0_DL_RELAY, "vpp1_svpp3_vdo0_dl_relay", "top_vpp", 9),
> +	GATE_VPP1_1(CLK_VPP1_VPP0_DL_ASYNC, "vpp1_vpp0_dl_async", "top_vpp", 10),
> +	GATE_VPP1_1(CLK_VPP1_VPP0_DL1_RELAY, "vpp1_vpp0_dl1_relay", "top_vpp", 11),
> +	GATE_VPP1_1(CLK_VPP1_LARB5_FAKE_ENG, "vpp1_larb5_fake_eng", "top_vpp", 12),
> +	GATE_VPP1_1(CLK_VPP1_LARB6_FAKE_ENG, "vpp1_larb6_fake_eng", "top_vpp", 13),
> +	GATE_VPP1_1(CLK_VPP1_HDMI_META, "vpp1_hdmi_meta", "top_vpp", 16),
> +	GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_HDMI, "vpp1_vpp_split_hdmi", "top_vpp", 17),
> +	GATE_VPP1_1(CLK_VPP1_DGI_IN, "vpp1_dgi_in", "top_vpp", 18),
> +	GATE_VPP1_1(CLK_VPP1_DGI_OUT, "vpp1_dgi_out", "top_vpp", 19),
> +	GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_DGI, "vpp1_vpp_split_dgi", "top_vpp", 20),
> +	GATE_VPP1_1(CLK_VPP1_DL_CON_OCC, "vpp1_dl_con_occ", "top_vpp", 21),
> +	GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_26M, "vpp1_vpp_split_26m", "top_vpp", 26),
> +};
> +
> +static int clk_mt8188_vpp1_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct device_node *node = dev->parent->of_node;
> +	struct clk_hw_onecell_data *clk_data;
> +	int r;
> +
> +	clk_data = mtk_alloc_clk_data(CLK_VPP1_NR_CLK);
> +	if (!clk_data)
> +		return -ENOMEM;
> +
> +	r = mtk_clk_register_gates(node, vpp1_clks, ARRAY_SIZE(vpp1_clks), clk_data);
> +	if (r)
> +		goto free_vpp1_data;
> +
> +	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
> +	if (r)
> +		goto unregister_gates;
> +
> +	platform_set_drvdata(pdev, clk_data);
> +
> +	return r;
> +
> +unregister_gates:
> +	mtk_clk_unregister_gates(vpp1_clks, ARRAY_SIZE(vpp1_clks), clk_data);
> +free_vpp1_data:
> +	mtk_free_clk_data(clk_data);
> +	return r;
> +}
> +
> +static int clk_mt8188_vpp1_remove(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct device_node *node = dev->parent->of_node;
> +	struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
> +
> +	of_clk_del_provider(node);
> +	mtk_clk_unregister_gates(vpp1_clks, ARRAY_SIZE(vpp1_clks), clk_data);
> +	mtk_free_clk_data(clk_data);
> +
> +	return 0;
> +}
> +
> +static struct platform_driver clk_mt8188_vpp1_drv = {
> +	.probe = clk_mt8188_vpp1_probe,
> +	.remove = clk_mt8188_vpp1_remove,
> +	.driver = {
> +		.name = "clk-mt8188-vpp1",
> +	},
> +};
> +builtin_platform_driver(clk_mt8188_vpp1_drv);

Re: [PATCH v5 01/19] dt-bindings: clock: mediatek: Add new MT8188 clock

[Krzysztof Kozlowski]

On 19/01/2023 13:48, Garmin.Chang wrote:
> Add the new binding documentation for system clock
> and functional clock on MediaTek MT8188.
> 
> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
> ---
>  .../bindings/clock/mediatek,mt8188-clock.yaml |  71 ++
>  .../clock/mediatek,mt8188-sys-clock.yaml      |  55 ++
>  .../dt-bindings/clock/mediatek,mt8188-clk.h   | 733 ++++++++++++++++++
>  3 files changed, 859 insertions(+)


Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH v5 00/19] MediaTek MT8188 clock support

[Chen-Yu Tsai]

On Thu, Jan 19, 2023 at 8:49 PM Garmin.Chang <Garmin.Chang@mediatek.com> wrote:
>
> Base on tag: next-20230119, linux-next/master

There are some recent changes to the MediaTek clk driver library
that makes this series incompatible. Could you rebase onto next-202302xx
and send a new version?

Thanks

Re: [PATCH v5 04/19] clk: mediatek: Add MT8188 peripheral clock support

[Chen-Yu Tsai]

On Thu, Jan 19, 2023 at 8:51 PM Garmin.Chang <Garmin.Chang@mediatek.com> wrote:
>
> Add MT8188 peripheral clock controller which provides clock
> gate control for ethernet/flashif/pcie/ssusb.
>
> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>

Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>

Re: [PATCH v5 05/19] clk: mediatek: Add MT8188 infrastructure clock support

[Chen-Yu Tsai]

On Thu, Jan 19, 2023 at 8:51 PM Garmin.Chang <Garmin.Chang@mediatek.com> wrote:
>
> Add MT8188 infrastructure clock controller which provides
> clock gate control for basic IP like pwm, uart, spi and so on.
>
> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>

Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>

Re: [PATCH v5 06/19] clk: mediatek: Add MT8188 camsys clock support

[Chen-Yu Tsai]

On Thu, Jan 19, 2023 at 8:50 PM Garmin.Chang <Garmin.Chang@mediatek.com> wrote:
>
> Add MT8188 camsys clock controllers which provide clock gate
> control for camera IP blocks.
>
> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>

Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>

Re: [PATCH v5 07/19] clk: mediatek: Add MT8188 ccusys clock support

[Chen-Yu Tsai]

On Thu, Jan 19, 2023 at 8:50 PM Garmin.Chang <Garmin.Chang@mediatek.com> wrote:
>
> Add MT8188 ccusys clock controller which provides clock gate
> control in Camera Computing Unit.

If this is also for camera related functions, could you fold this into
the previous CAM clock driver? That would save a bit of space.

The code looks OK.

Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>

> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
> ---
>  drivers/clk/mediatek/Makefile         |  2 +-
>  drivers/clk/mediatek/clk-mt8188-ccu.c | 48 +++++++++++++++++++++++++++
>  2 files changed, 49 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/clk/mediatek/clk-mt8188-ccu.c
>
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index dc247bf67e8b..dbd140b81763 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -85,7 +85,7 @@ obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt
>                                    clk-mt8186-cam.o clk-mt8186-mdp.o clk-mt8186-ipe.o
>  obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o \
>                                    clk-mt8188-peri_ao.o clk-mt8188-infra_ao.o \
> -                                  clk-mt8188-cam.o
> +                                  clk-mt8188-cam.o clk-mt8188-ccu.o
>  obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
>  obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
>  obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> diff --git a/drivers/clk/mediatek/clk-mt8188-ccu.c b/drivers/clk/mediatek/clk-mt8188-ccu.c
> new file mode 100644
> index 000000000000..b7380060f906
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8188-ccu.c
> @@ -0,0 +1,48 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +//
> +// Copyright (c) 2022 MediaTek Inc.
> +// Author: Garmin Chang <garmin.chang@mediatek.com>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> +
> +#include "clk-gate.h"
> +#include "clk-mtk.h"
> +
> +static const struct mtk_gate_regs ccu_cg_regs = {
> +       .set_ofs = 0x4,
> +       .clr_ofs = 0x8,
> +       .sta_ofs = 0x0,
> +};
> +
> +#define GATE_CCU(_id, _name, _parent, _shift)                  \
> +       GATE_MTK(_id, _name, _parent, &ccu_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +static const struct mtk_gate ccu_clks[] = {
> +       GATE_CCU(CLK_CCU_LARB27, "ccu_larb27", "top_ccu", 0),
> +       GATE_CCU(CLK_CCU_AHB, "ccu_ahb", "top_ccu", 1),
> +       GATE_CCU(CLK_CCU_CCU0, "ccu_ccu0", "top_ccu", 2),
> +};
> +
> +static const struct mtk_clk_desc ccu_desc = {
> +       .clks = ccu_clks,
> +       .num_clks = ARRAY_SIZE(ccu_clks),
> +};
> +
> +static const struct of_device_id of_match_clk_mt8188_ccu[] = {
> +       { .compatible = "mediatek,mt8188-ccusys", .data = &ccu_desc},
> +       { /* sentinel */ }
> +};
> +
> +static struct platform_driver clk_mt8188_ccu_drv = {
> +       .probe = mtk_clk_simple_probe,
> +       .remove = mtk_clk_simple_remove,
> +       .driver = {
> +               .name = "clk-mt8188-ccu",
> +               .of_match_table = of_match_clk_mt8188_ccu,
> +       },
> +};
> +
> +builtin_platform_driver(clk_mt8188_ccu_drv);
> +MODULE_LICENSE("GPL");
> --
> 2.18.0
>
>

Re: [PATCH v5 08/19] clk: mediatek: Add MT8188 imgsys clock support

[Chen-Yu Tsai]

On Thu, Jan 19, 2023 at 8:55 PM Garmin.Chang <Garmin.Chang@mediatek.com> wrote:
>
> Add MT8188 imgsys clock controllers which provide clock gate
> control for image IP blocks.
>
> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>

Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>

Re: [PATCH v5 09/19] clk: mediatek: Add MT8188 ipesys clock support

[Chen-Yu Tsai]

On Thu, Jan 19, 2023 at 8:54 PM Garmin.Chang <Garmin.Chang@mediatek.com> wrote:
>
> Add MT8188 ipesys clock controller which provides clock gate
> control for Image Process Engine.
>
> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>

Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>

Re: [PATCH v5 10/19] clk: mediatek: Add MT8188 mfgcfg clock support

[Chen-Yu Tsai]

On Thu, Jan 19, 2023 at 8:50 PM Garmin.Chang <Garmin.Chang@mediatek.com> wrote:
>
> Add MT8188 mfg clock controller which provides clock gate
> control for GPU.
>
> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
> ---
>  drivers/clk/mediatek/Makefile         |  2 +-
>  drivers/clk/mediatek/clk-mt8188-mfg.c | 47 +++++++++++++++++++++++++++
>  2 files changed, 48 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/clk/mediatek/clk-mt8188-mfg.c
>
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index 4a599122f761..a0fd87a882b5 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -86,7 +86,7 @@ obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt
>  obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o \
>                                    clk-mt8188-peri_ao.o clk-mt8188-infra_ao.o \
>                                    clk-mt8188-cam.o clk-mt8188-ccu.o clk-mt8188-img.o \
> -                                  clk-mt8188-ipe.o
> +                                  clk-mt8188-ipe.o clk-mt8188-mfg.o
>  obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
>  obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
>  obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> diff --git a/drivers/clk/mediatek/clk-mt8188-mfg.c b/drivers/clk/mediatek/clk-mt8188-mfg.c
> new file mode 100644
> index 000000000000..57b0afb5f4df
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8188-mfg.c
> @@ -0,0 +1,47 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +//
> +// Copyright (c) 2022 MediaTek Inc.
> +// Author: Garmin Chang <garmin.chang@mediatek.com>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> +
> +#include "clk-gate.h"
> +#include "clk-mtk.h"
> +
> +static const struct mtk_gate_regs mfgcfg_cg_regs = {
> +       .set_ofs = 0x4,
> +       .clr_ofs = 0x8,
> +       .sta_ofs = 0x0,
> +};
> +
> +#define GATE_MFG(_id, _name, _parent, _shift)                          \
> +       GATE_MTK_FLAGS(_id, _name, _parent, &mfgcfg_cg_regs, _shift,    \
> +                      &mtk_clk_gate_ops_setclr, CLK_SET_RATE_PARENT)
> +
> +static const struct mtk_gate mfgcfg_clks[] = {
> +       GATE_MFG(CLK_MFGCFG_BG3D, "mfgcfg_bg3d", "top_mfg_core_tmp", 0),

Are you sure the parent isn't "mfg_ck_fast_ref"?

ChenYu

Re: [PATCH v5 11/19] clk: mediatek: Add MT8188 vdecsys clock support

[Chen-Yu Tsai]

On Thu, Jan 19, 2023 at 8:49 PM Garmin.Chang <Garmin.Chang@mediatek.com> wrote:
>
> Add MT8188 vdec clock controllers which provide clock gate
> control for video decoder.
>
> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
> ---
>  drivers/clk/mediatek/Makefile          |  2 +-
>  drivers/clk/mediatek/clk-mt8188-vdec.c | 90 ++++++++++++++++++++++++++
>  2 files changed, 91 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/clk/mediatek/clk-mt8188-vdec.c
>
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index a0fd87a882b5..7d09e9fc6538 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -86,7 +86,7 @@ obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt
>  obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o \
>                                    clk-mt8188-peri_ao.o clk-mt8188-infra_ao.o \
>                                    clk-mt8188-cam.o clk-mt8188-ccu.o clk-mt8188-img.o \
> -                                  clk-mt8188-ipe.o clk-mt8188-mfg.o
> +                                  clk-mt8188-ipe.o clk-mt8188-mfg.o clk-mt8188-vdec.o
>  obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
>  obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
>  obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> diff --git a/drivers/clk/mediatek/clk-mt8188-vdec.c b/drivers/clk/mediatek/clk-mt8188-vdec.c
> new file mode 100644
> index 000000000000..e05a27957136
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8188-vdec.c
> @@ -0,0 +1,90 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +//
> +// Copyright (c) 2022 MediaTek Inc.
> +// Author: Garmin Chang <garmin.chang@mediatek.com>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> +
> +#include "clk-gate.h"
> +#include "clk-mtk.h"
> +
> +static const struct mtk_gate_regs vde0_cg_regs = {

Could you replace all instances of "vde" (both upper and lower case)
with "vdec" to be consistent with usages elsewhere?

> +       .set_ofs = 0x0,
> +       .clr_ofs = 0x4,
> +       .sta_ofs = 0x0,
> +};
> +
> +static const struct mtk_gate_regs vde1_cg_regs = {
> +       .set_ofs = 0x200,
> +       .clr_ofs = 0x204,
> +       .sta_ofs = 0x200,
> +};
> +
> +static const struct mtk_gate_regs vde2_cg_regs = {
> +       .set_ofs = 0x8,
> +       .clr_ofs = 0xc,
> +       .sta_ofs = 0x8,
> +};
> +
> +#define GATE_VDE0(_id, _name, _parent, _shift)                 \
> +       GATE_MTK(_id, _name, _parent, &vde0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
> +
> +#define GATE_VDE1(_id, _name, _parent, _shift)                 \
> +       GATE_MTK(_id, _name, _parent, &vde1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
> +
> +#define GATE_VDE2(_id, _name, _parent, _shift)                 \
> +       GATE_MTK(_id, _name, _parent, &vde2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
> +
> +static const struct mtk_gate vde1_clks[] = {
> +       /* VDE1_0 */
> +       GATE_VDE0(CLK_VDE1_SOC_VDEC, "vde1_soc_vdec", "top_vdec", 0),
> +       GATE_VDE0(CLK_VDE1_SOC_VDEC_ACTIVE, "vde1_soc_vdec_active", "top_vdec", 4),
> +       GATE_VDE0(CLK_VDE1_SOC_VDEC_ENG, "vde1_soc_vdec_eng", "top_vdec", 8),
> +       /* VDE1_1 */
> +       GATE_VDE1(CLK_VDE1_SOC_LAT, "vde1_soc_lat", "top_vdec", 0),
> +       GATE_VDE1(CLK_VDE1_SOC_LAT_ACTIVE, "vde1_soc_lat_active", "top_vdec", 4),
> +       GATE_VDE1(CLK_VDE1_SOC_LAT_ENG, "vde1_soc_lat_eng", "top_vdec", 8),
> +       /* VDE12 */

Add an underscore like the above?

ChenYu

> +       GATE_VDE2(CLK_VDE1_SOC_LARB1, "vde1_soc_larb1", "top_vdec", 0),
> +};
> +
> +static const struct mtk_gate vde2_clks[] = {
> +       /* VDE2_0 */
> +       GATE_VDE0(CLK_VDE2_VDEC, "vde2_vdec", "top_vdec", 0),
> +       GATE_VDE0(CLK_VDE2_VDEC_ACTIVE, "vde2_vdec_active", "top_vdec", 4),
> +       GATE_VDE0(CLK_VDE2_VDEC_ENG, "vde2_vdec_eng", "top_vdec", 8),
> +       /* VDE2_1 */
> +       GATE_VDE1(CLK_VDE2_LAT, "vde2_lat", "top_vdec", 0),
> +       /* VDE2_2 */
> +       GATE_VDE2(CLK_VDE2_LARB1, "vde2_larb1", "top_vdec", 0),
> +};
> +
> +static const struct mtk_clk_desc vde1_desc = {
> +       .clks = vde1_clks,
> +       .num_clks = ARRAY_SIZE(vde1_clks),
> +};
> +
> +static const struct mtk_clk_desc vde2_desc = {
> +       .clks = vde2_clks,
> +       .num_clks = ARRAY_SIZE(vde2_clks),
> +};
> +
> +static const struct of_device_id of_match_clk_mt8188_vde[] = {
> +       { .compatible = "mediatek,mt8188-vdecsys-soc", .data = &vde1_desc },
> +       { .compatible = "mediatek,mt8188-vdecsys", .data = &vde2_desc },
> +       { /* sentinel */ }
> +};
> +
> +static struct platform_driver clk_mt8188_vde_drv = {
> +       .probe = mtk_clk_simple_probe,
> +       .remove = mtk_clk_simple_remove,
> +       .driver = {
> +               .name = "clk-mt8188-vde",
> +               .of_match_table = of_match_clk_mt8188_vde,
> +       },
> +};
> +
> +builtin_platform_driver(clk_mt8188_vde_drv);
> +MODULE_LICENSE("GPL");
> --
> 2.18.0
>
>

Re: [PATCH v5 12/19] clk: mediatek: Add MT8188 vdosys0 clock support

[Chen-Yu Tsai]

On Thu, Jan 19, 2023 at 8:54 PM Garmin.Chang <Garmin.Chang@mediatek.com> wrote:
>
> Add MT8188 vdosys0 clock controller which provides clock gate
> control in video system. This is integrated with mtk-mmsys
> driver which will populate device by platform_device_register_data
> to start vdosys clock driver.
>
> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
> ---
>  drivers/clk/mediatek/Makefile          |   3 +-
>  drivers/clk/mediatek/clk-mt8188-vdo0.c | 134 +++++++++++++++++++++++++
>  2 files changed, 136 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/clk/mediatek/clk-mt8188-vdo0.c
>
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index 7d09e9fc6538..df78c0777fef 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -86,7 +86,8 @@ obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt
>  obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o \
>                                    clk-mt8188-peri_ao.o clk-mt8188-infra_ao.o \
>                                    clk-mt8188-cam.o clk-mt8188-ccu.o clk-mt8188-img.o \
> -                                  clk-mt8188-ipe.o clk-mt8188-mfg.o clk-mt8188-vdec.o
> +                                  clk-mt8188-ipe.o clk-mt8188-mfg.o clk-mt8188-vdec.o \
> +                                  clk-mt8188-vdo0.o
>  obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
>  obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
>  obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> diff --git a/drivers/clk/mediatek/clk-mt8188-vdo0.c b/drivers/clk/mediatek/clk-mt8188-vdo0.c
> new file mode 100644
> index 000000000000..30dd64374ace
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8188-vdo0.c
> @@ -0,0 +1,134 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +//
> +// Copyright (c) 2022 MediaTek Inc.
> +// Author: Garmin Chang <garmin.chang@mediatek.com>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> +
> +#include "clk-gate.h"
> +#include "clk-mtk.h"
> +
> +static const struct mtk_gate_regs vdo0_0_cg_regs = {
> +       .set_ofs = 0x104,
> +       .clr_ofs = 0x108,
> +       .sta_ofs = 0x100,
> +};
> +
> +static const struct mtk_gate_regs vdo0_1_cg_regs = {
> +       .set_ofs = 0x114,
> +       .clr_ofs = 0x118,
> +       .sta_ofs = 0x110,
> +};
> +
> +static const struct mtk_gate_regs vdo0_2_cg_regs = {
> +       .set_ofs = 0x124,
> +       .clr_ofs = 0x128,
> +       .sta_ofs = 0x120,
> +};
> +
> +#define GATE_VDO0_0(_id, _name, _parent, _shift)                       \
> +       GATE_MTK(_id, _name, _parent, &vdo0_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +#define GATE_VDO0_1(_id, _name, _parent, _shift)                       \
> +       GATE_MTK(_id, _name, _parent, &vdo0_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +#define GATE_VDO0_2(_id, _name, _parent, _shift)                       \
> +       GATE_MTK(_id, _name, _parent, &vdo0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +#define GATE_VDO0_2_FLAGS(_id, _name, _parent, _shift, _flags)         \
> +       GATE_MTK_FLAGS(_id, _name, _parent, &vdo0_2_cg_regs, _shift,    \
> +       &mtk_clk_gate_ops_setclr, _flags)
> +
> +static const struct mtk_gate vdo0_clks[] = {
> +       /* VDO0_0 */
> +       GATE_VDO0_0(CLK_VDO0_DISP_OVL0, "vdo0_disp_ovl0", "top_vpp", 0),
> +       GATE_VDO0_0(CLK_VDO0_FAKE_ENG0, "vdo0_fake_eng0", "top_vpp", 2),
> +       GATE_VDO0_0(CLK_VDO0_DISP_CCORR0, "vdo0_disp_ccorr0", "top_vpp", 4),
> +       GATE_VDO0_0(CLK_VDO0_DISP_MUTEX0, "vdo0_disp_mutex0", "top_vpp", 6),
> +       GATE_VDO0_0(CLK_VDO0_DISP_GAMMA0, "vdo0_disp_gamma0", "top_vpp", 8),
> +       GATE_VDO0_0(CLK_VDO0_DISP_DITHER0, "vdo0_disp_dither0", "top_vpp", 10),
> +       GATE_VDO0_0(CLK_VDO0_DISP_WDMA0, "vdo0_disp_wdma0", "top_vpp", 17),
> +       GATE_VDO0_0(CLK_VDO0_DISP_RDMA0, "vdo0_disp_rdma0", "top_vpp", 19),
> +       GATE_VDO0_0(CLK_VDO0_DSI0, "vdo0_dsi0", "top_vpp", 21),
> +       GATE_VDO0_0(CLK_VDO0_DSI1, "vdo0_dsi1", "top_vpp", 22),
> +       GATE_VDO0_0(CLK_VDO0_DSC_WRAP0, "vdo0_dsc_wrap0", "top_vpp", 23),
> +       GATE_VDO0_0(CLK_VDO0_VPP_MERGE0, "vdo0_vpp_merge0", "top_vpp", 24),
> +       GATE_VDO0_0(CLK_VDO0_DP_INTF0, "vdo0_dp_intf0", "top_vpp", 25),
> +       GATE_VDO0_0(CLK_VDO0_DISP_AAL0, "vdo0_disp_aal0", "top_vpp", 26),
> +       GATE_VDO0_0(CLK_VDO0_INLINEROT0, "vdo0_inlinerot0", "top_vpp", 27),
> +       GATE_VDO0_0(CLK_VDO0_APB_BUS, "vdo0_apb_bus", "top_vpp", 28),
> +       GATE_VDO0_0(CLK_VDO0_DISP_COLOR0, "vdo0_disp_color0", "top_vpp", 29),
> +       GATE_VDO0_0(CLK_VDO0_MDP_WROT0, "vdo0_mdp_wrot0", "top_vpp", 30),
> +       GATE_VDO0_0(CLK_VDO0_DISP_RSZ0, "vdo0_disp_rsz0", "top_vpp", 31),
> +       /* VDO0_1 */
> +       GATE_VDO0_1(CLK_VDO0_DISP_POSTMASK0, "vdo0_disp_postmask0", "top_vpp", 0),
> +       GATE_VDO0_1(CLK_VDO0_FAKE_ENG1, "vdo0_fake_eng1", "top_vpp", 1),
> +       GATE_VDO0_1(CLK_VDO0_DL_ASYNC2, "vdo0_dl_async2", "top_vpp", 5),
> +       GATE_VDO0_1(CLK_VDO0_DL_RELAY3, "vdo0_dl_relay3", "top_vpp", 6),
> +       GATE_VDO0_1(CLK_VDO0_DL_RELAY4, "vdo0_dl_relay4", "top_vpp", 7),
> +       GATE_VDO0_1(CLK_VDO0_SMI_GALS, "vdo0_smi_gals", "top_vpp", 10),
> +       GATE_VDO0_1(CLK_VDO0_SMI_COMMON, "vdo0_smi_common", "top_vpp", 11),
> +       GATE_VDO0_1(CLK_VDO0_SMI_EMI, "vdo0_smi_emi", "top_vpp", 12),
> +       GATE_VDO0_1(CLK_VDO0_SMI_IOMMU, "vdo0_smi_iommu", "top_vpp", 13),
> +       GATE_VDO0_1(CLK_VDO0_SMI_LARB, "vdo0_smi_larb", "top_vpp", 14),
> +       GATE_VDO0_1(CLK_VDO0_SMI_RSI, "vdo0_smi_rsi", "top_vpp", 15),
> +       /* VDO0_2 */
> +       GATE_VDO0_2(CLK_VDO0_DSI0_DSI, "vdo0_dsi0_dsi", "top_dsi_occ", 0),
> +       GATE_VDO0_2(CLK_VDO0_DSI1_DSI, "vdo0_dsi1_dsi", "top_dsi_occ", 8),
> +       GATE_VDO0_2_FLAGS(CLK_VDO0_DP_INTF0_DP_INTF, "vdo0_dp_intf0_dp_intf",
> +               "top_edp", 16, CLK_SET_RATE_PARENT),
> +};
> +
> +static int clk_mt8188_vdo0_probe(struct platform_device *pdev)
> +{
> +       struct device *dev = &pdev->dev;
> +       struct device_node *node = dev->parent->of_node;
> +       struct clk_hw_onecell_data *clk_data;
> +       int r;
> +
> +       clk_data = mtk_alloc_clk_data(CLK_VDO0_NR_CLK);
> +       if (!clk_data)
> +               return -ENOMEM;
> +
> +       r = mtk_clk_register_gates(node, vdo0_clks, ARRAY_SIZE(vdo0_clks), clk_data);

This API was changed. Please rebase onto the latest -next and update.

Angelo (CC-ed) also mentioned a new simple probe variant for non-DT
clock drivers is being developed. He didn't mention a timeline though.

Re: [PATCH v5 14/19] clk: mediatek: Add MT8188 vencsys clock support

[Chen-Yu Tsai]

On Thu, Jan 19, 2023 at 8:55 PM Garmin.Chang <Garmin.Chang@mediatek.com> wrote:
>
> Add MT8188 vencsys clock controllers which provide clock gate
> control for video encoder.
>
> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
> ---
>  drivers/clk/mediatek/Makefile          |  2 +-
>  drivers/clk/mediatek/clk-mt8188-venc.c | 52 ++++++++++++++++++++++++++
>  2 files changed, 53 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/clk/mediatek/clk-mt8188-venc.c
>
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index c654f4288e09..22a3840160fc 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -87,7 +87,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o
>                                    clk-mt8188-peri_ao.o clk-mt8188-infra_ao.o \
>                                    clk-mt8188-cam.o clk-mt8188-ccu.o clk-mt8188-img.o \
>                                    clk-mt8188-ipe.o clk-mt8188-mfg.o clk-mt8188-vdec.o \
> -                                  clk-mt8188-vdo0.o clk-mt8188-vdo1.o
> +                                  clk-mt8188-vdo0.o clk-mt8188-vdo1.o clk-mt8188-venc.o
>  obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
>  obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
>  obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> diff --git a/drivers/clk/mediatek/clk-mt8188-venc.c b/drivers/clk/mediatek/clk-mt8188-venc.c
> new file mode 100644
> index 000000000000..375ef99e2349
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8188-venc.c
> @@ -0,0 +1,52 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +//
> +// Copyright (c) 2022 MediaTek Inc.
> +// Author: Garmin Chang <garmin.chang@mediatek.com>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> +
> +#include "clk-gate.h"
> +#include "clk-mtk.h"
> +
> +static const struct mtk_gate_regs ven1_cg_regs = {

Like the vdecsys patch, please change "ven" to "venc" to be consistent
with usages elsewhere.

> +       .set_ofs = 0x4,
> +       .clr_ofs = 0x8,
> +       .sta_ofs = 0x0,
> +};
> +
> +#define GATE_VEN1(_id, _name, _parent, _shift)                 \
> +       GATE_MTK(_id, _name, _parent, &ven1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
> +
> +static const struct mtk_gate ven1_clks[] = {
> +       GATE_VEN1(CLK_VEN1_CKE0_LARB, "ven1_cke0_larb", "top_venc", 0),
> +       GATE_VEN1(CLK_VEN1_CKE1_VENC, "ven1_cke1_venc", "top_venc", 4),
> +       GATE_VEN1(CLK_VEN1_CKE2_JPGENC, "ven1_cke2_jpgenc", "top_venc", 8),
> +       GATE_VEN1(CLK_VEN1_CKE3_JPGDEC, "ven1_cke3_jpgdec", "top_venc", 12),
> +       GATE_VEN1(CLK_VEN1_CKE4_JPGDEC_C1, "ven1_cke4_jpgdec_c1", "top_venc", 16),
> +       GATE_VEN1(CLK_VEN1_CKE5_GALS, "ven1_cke5_gals", "top_venc", 28),
> +       GATE_VEN1(CLK_VEN1_CKE6_GALS_SRAM, "ven1_cke6_gals_sram", "top_venc", 31),

Is ckeN in both the macro name and clock name necessary? We don't really
care about the index.

ChenYu

> +};
> +
> +static const struct mtk_clk_desc ven1_desc = {
> +       .clks = ven1_clks,
> +       .num_clks = ARRAY_SIZE(ven1_clks),
> +};
> +
> +static const struct of_device_id of_match_clk_mt8188_ven1[] = {
> +       { .compatible = "mediatek,mt8188-vencsys", .data = &ven1_desc },
> +       { /* sentinel */ }
> +};
> +
> +static struct platform_driver clk_mt8188_ven1_drv = {
> +       .probe = mtk_clk_simple_probe,
> +       .remove = mtk_clk_simple_remove,
> +       .driver = {
> +               .name = "clk-mt8188-ven1",
> +               .of_match_table = of_match_clk_mt8188_ven1,
> +       },
> +};
> +
> +builtin_platform_driver(clk_mt8188_ven1_drv);
> +MODULE_LICENSE("GPL");
> --
> 2.18.0
>
>

Re: [PATCH v5 17/19] clk: mediatek: Add MT8188 wpesys clock support

[Chen-Yu Tsai]

On Thu, Jan 19, 2023 at 8:54 PM Garmin.Chang <Garmin.Chang@mediatek.com> wrote:
>
> Add MT8188 wpesys clock controllers which provide clock gate
> control in Wrapping Engine.
>
> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>

Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>

Re: [PATCH v5 15/19] clk: mediatek: Add MT8188 vppsys0 clock support

[Chen-Yu Tsai]

On Thu, Jan 19, 2023 at 8:54 PM Garmin.Chang <Garmin.Chang@mediatek.com> wrote:
>
> Add MT8188 vppsys0 clock controller which provides clock gate
> controller for Video Processor Pipe.
>
> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
> ---
>  drivers/clk/mediatek/Makefile          |   3 +-
>  drivers/clk/mediatek/clk-mt8188-vpp0.c | 143 +++++++++++++++++++++++++
>  2 files changed, 145 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/clk/mediatek/clk-mt8188-vpp0.c
>
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index 22a3840160fc..48deecc6b520 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -87,7 +87,8 @@ obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o
>                                    clk-mt8188-peri_ao.o clk-mt8188-infra_ao.o \
>                                    clk-mt8188-cam.o clk-mt8188-ccu.o clk-mt8188-img.o \
>                                    clk-mt8188-ipe.o clk-mt8188-mfg.o clk-mt8188-vdec.o \
> -                                  clk-mt8188-vdo0.o clk-mt8188-vdo1.o clk-mt8188-venc.o
> +                                  clk-mt8188-vdo0.o clk-mt8188-vdo1.o clk-mt8188-venc.o \
> +                                  clk-mt8188-vpp0.o
>  obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
>  obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
>  obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> diff --git a/drivers/clk/mediatek/clk-mt8188-vpp0.c b/drivers/clk/mediatek/clk-mt8188-vpp0.c
> new file mode 100644
> index 000000000000..e7b46142d653
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8188-vpp0.c
> @@ -0,0 +1,143 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +//
> +// Copyright (c) 2022 MediaTek Inc.
> +// Author: Garmin Chang <garmin.chang@mediatek.com>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> +
> +#include "clk-gate.h"
> +#include "clk-mtk.h"
> +
> +static const struct mtk_gate_regs vpp0_0_cg_regs = {
> +       .set_ofs = 0x24,
> +       .clr_ofs = 0x28,
> +       .sta_ofs = 0x20,
> +};
> +
> +static const struct mtk_gate_regs vpp0_1_cg_regs = {
> +       .set_ofs = 0x30,
> +       .clr_ofs = 0x34,
> +       .sta_ofs = 0x2c,
> +};
> +
> +static const struct mtk_gate_regs vpp0_2_cg_regs = {
> +       .set_ofs = 0x3c,
> +       .clr_ofs = 0x40,
> +       .sta_ofs = 0x38,
> +};
> +
> +#define GATE_VPP0_0(_id, _name, _parent, _shift)                       \
> +       GATE_MTK(_id, _name, _parent, &vpp0_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +#define GATE_VPP0_1(_id, _name, _parent, _shift)                       \
> +       GATE_MTK(_id, _name, _parent, &vpp0_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +#define GATE_VPP0_2(_id, _name, _parent, _shift)                       \
> +       GATE_MTK(_id, _name, _parent, &vpp0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +static const struct mtk_gate vpp0_clks[] = {
> +       /* VPP0_0 */
> +       GATE_VPP0_0(CLK_VPP0_MDP_FG, "vpp0_mdp_fg", "top_vpp", 1),
> +       GATE_VPP0_0(CLK_VPP0_STITCH, "vpp0_stitch", "top_vpp", 2),
> +       GATE_VPP0_0(CLK_VPP0_PADDING, "vpp0_padding", "top_vpp", 7),
> +       GATE_VPP0_0(CLK_VPP0_MDP_TCC, "vpp0_mdp_tcc", "top_vpp", 8),
> +       GATE_VPP0_0(CLK_VPP0_WARP0_ASYNC_TX, "vpp0_warp0_async_tx", "top_vpp", 10),
> +       GATE_VPP0_0(CLK_VPP0_WARP1_ASYNC_TX, "vpp0_warp1_async_tx", "top_vpp", 11),
> +       GATE_VPP0_0(CLK_VPP0_MUTEX, "vpp0_mutex", "top_vpp", 13),
> +       GATE_VPP0_0(CLK_VPP02VPP1_RELAY, "vpp02vpp1_relay", "top_vpp", 14),
> +       GATE_VPP0_0(CLK_VPP0_VPP12VPP0_ASYNC, "vpp0_vpp12vpp0_async", "top_vpp", 15),
> +       GATE_VPP0_0(CLK_VPP0_MMSYSRAM_TOP, "vpp0_mmsysram_top", "top_vpp", 16),
> +       GATE_VPP0_0(CLK_VPP0_MDP_AAL, "vpp0_mdp_aal", "top_vpp", 17),
> +       GATE_VPP0_0(CLK_VPP0_MDP_RSZ, "vpp0_mdp_rsz", "top_vpp", 18),
> +       /* VPP0_1 */
> +       GATE_VPP0_1(CLK_VPP0_SMI_COMMON_MMSRAM, "vpp0_smi_common_mmsram", "top_vpp", 0),
> +       GATE_VPP0_1(CLK_VPP0_GALS_VDO0_LARB0_MMSRAM, "vpp0_gals_vdo0_larb0_mmsram", "top_vpp", 1),
> +       GATE_VPP0_1(CLK_VPP0_GALS_VDO0_LARB1_MMSRAM, "vpp0_gals_vdo0_larb1_mmsram", "top_vpp", 2),
> +       GATE_VPP0_1(CLK_VPP0_GALS_VENCSYS_MMSRAM, "vpp0_gals_vencsys_mmsram", "top_vpp", 3),
> +       GATE_VPP0_1(CLK_VPP0_GALS_VENCSYS_CORE1_MMSRAM,
> +                   "vpp0_gals_vencsys_core1_mmsram", "top_vpp", 4),
> +       GATE_VPP0_1(CLK_VPP0_GALS_INFRA_MMSRAM, "vpp0_gals_infra_mmsram", "top_vpp", 5),
> +       GATE_VPP0_1(CLK_VPP0_GALS_CAMSYS_MMSRAM, "vpp0_gals_camsys_mmsram", "top_vpp", 6),
> +       GATE_VPP0_1(CLK_VPP0_GALS_VPP1_LARB5_MMSRAM, "vpp0_gals_vpp1_larb5_mmsram", "top_vpp", 7),
> +       GATE_VPP0_1(CLK_VPP0_GALS_VPP1_LARB6_MMSRAM, "vpp0_gals_vpp1_larb6_mmsram", "top_vpp", 8),
> +       GATE_VPP0_1(CLK_VPP0_SMI_REORDER_MMSRAM, "vpp0_smi_reorder_mmsram", "top_vpp", 9),
> +       GATE_VPP0_1(CLK_VPP0_SMI_IOMMU, "vpp0_smi_iommu", "top_vpp", 10),
> +       GATE_VPP0_1(CLK_VPP0_GALS_IMGSYS_CAMSYS, "vpp0_gals_imgsys_camsys", "top_vpp", 11),
> +       GATE_VPP0_1(CLK_VPP0_MDP_RDMA, "vpp0_mdp_rdma", "top_vpp", 12),
> +       GATE_VPP0_1(CLK_VPP0_MDP_WROT, "vpp0_mdp_wrot", "top_vpp", 13),
> +       GATE_VPP0_1(CLK_VPP0_GALS_EMI0_EMI1, "vpp0_gals_emi0_emi1", "top_vpp", 16),
> +       GATE_VPP0_1(CLK_VPP0_SMI_SUB_COMMON_REORDER, "vpp0_smi_sub_common_reorder", "top_vpp", 17),
> +       GATE_VPP0_1(CLK_VPP0_SMI_RSI, "vpp0_smi_rsi", "top_vpp", 18),
> +       GATE_VPP0_1(CLK_VPP0_SMI_COMMON_LARB4, "vpp0_smi_common_larb4", "top_vpp", 19),
> +       GATE_VPP0_1(CLK_VPP0_GALS_VDEC_VDEC_CORE1, "vpp0_gals_vdec_vdec_core1", "top_vpp", 20),
> +       GATE_VPP0_1(CLK_VPP0_GALS_VPP1_WPESYS, "vpp0_gals_vpp1_wpesys", "top_vpp", 21),
> +       GATE_VPP0_1(CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1,
> +                   "vpp0_gals_vdo0_vdo1_vencsys_core1", "top_vpp", 22),
> +       GATE_VPP0_1(CLK_VPP0_FAKE_ENG, "vpp0_fake_eng", "top_vpp", 23),
> +       GATE_VPP0_1(CLK_VPP0_MDP_HDR, "vpp0_mdp_hdr", "top_vpp", 24),
> +       GATE_VPP0_1(CLK_VPP0_MDP_TDSHP, "vpp0_mdp_tdshp", "top_vpp", 25),
> +       GATE_VPP0_1(CLK_VPP0_MDP_COLOR, "vpp0_mdp_color", "top_vpp", 26),
> +       GATE_VPP0_1(CLK_VPP0_MDP_OVL, "vpp0_mdp_ovl", "top_vpp", 27),
> +       GATE_VPP0_1(CLK_VPP0_DSIP_RDMA, "vpp0_dsip_rdma", "top_vpp", 28),
> +       GATE_VPP0_1(CLK_VPP0_DISP_WDMA, "vpp0_disp_wdma", "top_vpp", 29),
> +       GATE_VPP0_1(CLK_VPP0_MDP_HMS, "vpp0_mdp_hms", "top_vpp", 30),
> +       /* VPP0_2 */
> +       GATE_VPP0_2(CLK_VPP0_WARP0_RELAY, "vpp0_warp0_relay", "top_wpe_vpp", 0),
> +       GATE_VPP0_2(CLK_VPP0_WARP0_ASYNC, "vpp0_warp0_async", "top_wpe_vpp", 1),
> +       GATE_VPP0_2(CLK_VPP0_WARP1_RELAY, "vpp0_warp1_relay", "top_wpe_vpp", 2),
> +       GATE_VPP0_2(CLK_VPP0_WARP1_ASYNC, "vpp0_warp1_async", "top_wpe_vpp", 3),
> +};
> +
> +static int clk_mt8188_vpp0_probe(struct platform_device *pdev)
> +{
> +       struct device *dev = &pdev->dev;
> +       struct device_node *node = dev->parent->of_node;
> +       struct clk_hw_onecell_data *clk_data;
> +       int r;
> +
> +       clk_data = mtk_alloc_clk_data(CLK_VPP0_NR_CLK);
> +       if (!clk_data)
> +               return -ENOMEM;
> +
> +       r = mtk_clk_register_gates(node, vpp0_clks, ARRAY_SIZE(vpp0_clks), clk_data);

This API has changed. Please rebase and update.

Otherwise,

Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>

Re: [PATCH v5 16/19] clk: mediatek: Add MT8188 vppsys1 clock support

[Chen-Yu Tsai]

On Thu, Jan 19, 2023 at 8:58 PM Garmin.Chang <Garmin.Chang@mediatek.com> wrote:
>
> Add MT8188 vppsys1 clock controller which provides clock gate
> controller for Video Processor Pipe.
>
> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
> ---
>  drivers/clk/mediatek/Makefile          |   2 +-
>  drivers/clk/mediatek/clk-mt8188-vpp1.c | 138 +++++++++++++++++++++++++
>  2 files changed, 139 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/clk/mediatek/clk-mt8188-vpp1.c
>
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index 48deecc6b520..37663de293bf 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -88,7 +88,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o
>                                    clk-mt8188-cam.o clk-mt8188-ccu.o clk-mt8188-img.o \
>                                    clk-mt8188-ipe.o clk-mt8188-mfg.o clk-mt8188-vdec.o \
>                                    clk-mt8188-vdo0.o clk-mt8188-vdo1.o clk-mt8188-venc.o \
> -                                  clk-mt8188-vpp0.o
> +                                  clk-mt8188-vpp0.o clk-mt8188-vpp1.o
>  obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
>  obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
>  obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> diff --git a/drivers/clk/mediatek/clk-mt8188-vpp1.c b/drivers/clk/mediatek/clk-mt8188-vpp1.c
> new file mode 100644
> index 000000000000..2bff3a52c93f
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8188-vpp1.c
> @@ -0,0 +1,138 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +//
> +// Copyright (c) 2022 MediaTek Inc.
> +// Author: Garmin Chang <garmin.chang@mediatek.com>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> +
> +#include "clk-gate.h"
> +#include "clk-mtk.h"
> +
> +static const struct mtk_gate_regs vpp1_0_cg_regs = {
> +       .set_ofs = 0x104,
> +       .clr_ofs = 0x108,
> +       .sta_ofs = 0x100,
> +};
> +
> +static const struct mtk_gate_regs vpp1_1_cg_regs = {
> +       .set_ofs = 0x114,
> +       .clr_ofs = 0x118,
> +       .sta_ofs = 0x110,
> +};
> +
> +#define GATE_VPP1_0(_id, _name, _parent, _shift)                       \
> +       GATE_MTK(_id, _name, _parent, &vpp1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +#define GATE_VPP1_1(_id, _name, _parent, _shift)                       \
> +       GATE_MTK(_id, _name, _parent, &vpp1_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +static const struct mtk_gate vpp1_clks[] = {
> +       /* VPP1_0 */
> +       GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_OVL, "vpp1_svpp1_mdp_ovl", "top_vpp", 0),
> +       GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_TCC, "vpp1_svpp1_mdp_tcc", "top_vpp", 1),
> +       GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_WROT, "vpp1_svpp1_mdp_wrot", "top_vpp", 2),
> +       GATE_VPP1_0(CLK_VPP1_SVPP1_VPP_PAD, "vpp1_svpp1_vpp_pad", "top_vpp", 3),
> +       GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_WROT, "vpp1_svpp2_mdp_wrot", "top_vpp", 4),
> +       GATE_VPP1_0(CLK_VPP1_SVPP2_VPP_PAD, "vpp1_svpp2_vpp_pad", "top_vpp", 5),
> +       GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_WROT, "vpp1_svpp3_mdp_wrot", "top_vpp", 6),
> +       GATE_VPP1_0(CLK_VPP1_SVPP3_VPP_PAD, "vpp1_svpp3_vpp_pad", "top_vpp", 7),
> +       GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_RDMA, "vpp1_svpp1_mdp_rdma", "top_vpp", 8),
> +       GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_FG, "vpp1_svpp1_mdp_fg", "top_vpp", 9),
> +       GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_RDMA, "vpp1_svpp2_mdp_rdma", "top_vpp", 10),
> +       GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_FG, "vpp1_svpp2_mdp_fg", "top_vpp", 11),
> +       GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_RDMA, "vpp1_svpp3_mdp_rdma", "top_vpp", 12),
> +       GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_FG, "vpp1_svpp3_mdp_fg", "top_vpp", 13),
> +       GATE_VPP1_0(CLK_VPP1_VPP_SPLIT, "vpp1_vpp_split", "top_vpp", 14),
> +       GATE_VPP1_0(CLK_VPP1_SVPP2_VDO0_DL_RELAY, "vpp1_svpp2_vdo0_dl_relay", "top_vpp", 15),
> +       GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_RSZ, "vpp1_svpp1_mdp_rsz", "top_vpp", 16),
> +       GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_TDSHP, "vpp1_svpp1_mdp_tdshp", "top_vpp", 17),
> +       GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_COLOR, "vpp1_svpp1_mdp_color", "top_vpp", 18),
> +       GATE_VPP1_0(CLK_VPP1_SVPP3_VDO1_DL_RELAY, "vpp1_svpp3_vdo1_dl_relay", "top_vpp", 19),
> +       GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_RSZ, "vpp1_svpp2_mdp_rsz", "top_vpp", 20),
> +       GATE_VPP1_0(CLK_VPP1_SVPP2_VPP_MERGE, "vpp1_svpp2_vpp_merge", "top_vpp", 21),
> +       GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_TDSHP, "vpp1_svpp2_mdp_tdshp", "top_vpp", 22),
> +       GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_COLOR, "vpp1_svpp2_mdp_color", "top_vpp", 23),
> +       GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_RSZ, "vpp1_svpp3_mdp_rsz", "top_vpp", 24),
> +       GATE_VPP1_0(CLK_VPP1_SVPP3_VPP_MERGE, "vpp1_svpp3_vpp_merge", "top_vpp", 25),
> +       GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_TDSHP, "vpp1_svpp3_mdp_tdshp", "top_vpp", 26),
> +       GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_COLOR, "vpp1_svpp3_mdp_color", "top_vpp", 27),
> +       GATE_VPP1_0(CLK_VPP1_GALS5, "vpp1_gals5", "top_vpp", 28),
> +       GATE_VPP1_0(CLK_VPP1_GALS6, "vpp1_gals6", "top_vpp", 29),
> +       GATE_VPP1_0(CLK_VPP1_LARB5, "vpp1_larb5", "top_vpp", 30),
> +       GATE_VPP1_0(CLK_VPP1_LARB6, "vpp1_larb6", "top_vpp", 31),
> +       /* VPP1_1 */
> +       GATE_VPP1_1(CLK_VPP1_SVPP1_MDP_HDR, "vpp1_svpp1_mdp_hdr", "top_vpp", 0),
> +       GATE_VPP1_1(CLK_VPP1_SVPP1_MDP_AAL, "vpp1_svpp1_mdp_aal", "top_vpp", 1),
> +       GATE_VPP1_1(CLK_VPP1_SVPP2_MDP_HDR, "vpp1_svpp2_mdp_hdr", "top_vpp", 2),
> +       GATE_VPP1_1(CLK_VPP1_SVPP2_MDP_AAL, "vpp1_svpp2_mdp_aal", "top_vpp", 3),
> +       GATE_VPP1_1(CLK_VPP1_SVPP3_MDP_HDR, "vpp1_svpp3_mdp_hdr", "top_vpp", 4),
> +       GATE_VPP1_1(CLK_VPP1_SVPP3_MDP_AAL, "vpp1_svpp3_mdp_aal", "top_vpp", 5),
> +       GATE_VPP1_1(CLK_VPP1_DISP_MUTEX, "vpp1_disp_mutex", "top_vpp", 7),
> +       GATE_VPP1_1(CLK_VPP1_SVPP2_VDO1_DL_RELAY, "vpp1_svpp2_vdo1_dl_relay", "top_vpp", 8),
> +       GATE_VPP1_1(CLK_VPP1_SVPP3_VDO0_DL_RELAY, "vpp1_svpp3_vdo0_dl_relay", "top_vpp", 9),
> +       GATE_VPP1_1(CLK_VPP1_VPP0_DL_ASYNC, "vpp1_vpp0_dl_async", "top_vpp", 10),
> +       GATE_VPP1_1(CLK_VPP1_VPP0_DL1_RELAY, "vpp1_vpp0_dl1_relay", "top_vpp", 11),
> +       GATE_VPP1_1(CLK_VPP1_LARB5_FAKE_ENG, "vpp1_larb5_fake_eng", "top_vpp", 12),
> +       GATE_VPP1_1(CLK_VPP1_LARB6_FAKE_ENG, "vpp1_larb6_fake_eng", "top_vpp", 13),
> +       GATE_VPP1_1(CLK_VPP1_HDMI_META, "vpp1_hdmi_meta", "top_vpp", 16),
> +       GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_HDMI, "vpp1_vpp_split_hdmi", "top_vpp", 17),
> +       GATE_VPP1_1(CLK_VPP1_DGI_IN, "vpp1_dgi_in", "top_vpp", 18),
> +       GATE_VPP1_1(CLK_VPP1_DGI_OUT, "vpp1_dgi_out", "top_vpp", 19),
> +       GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_DGI, "vpp1_vpp_split_dgi", "top_vpp", 20),
> +       GATE_VPP1_1(CLK_VPP1_DL_CON_OCC, "vpp1_dl_con_occ", "top_vpp", 21),
> +       GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_26M, "vpp1_vpp_split_26m", "top_vpp", 26),
> +};
> +
> +static int clk_mt8188_vpp1_probe(struct platform_device *pdev)
> +{
> +       struct device *dev = &pdev->dev;
> +       struct device_node *node = dev->parent->of_node;
> +       struct clk_hw_onecell_data *clk_data;
> +       int r;
> +
> +       clk_data = mtk_alloc_clk_data(CLK_VPP1_NR_CLK);
> +       if (!clk_data)
> +               return -ENOMEM;
> +
> +       r = mtk_clk_register_gates(node, vpp1_clks, ARRAY_SIZE(vpp1_clks), clk_data);

Same here. Please update.

Once fixed,

Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>

Re: [PATCH v5 18/19] clk: mediatek: Add MT8188 imp i2c wrapper clock support

[Chen-Yu Tsai]

On Thu, Jan 19, 2023 at 8:55 PM Garmin.Chang <Garmin.Chang@mediatek.com> wrote:
>
> Add MT8188 imp i2c wrapper clock controllers which provide clock gate
> control in I2C IP blocks.
>
> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>

Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>

Re: [PATCH v5 19/19] clk: mediatek: Add MT8188 adsp clock support

[Chen-Yu Tsai]

On Thu, Jan 19, 2023 at 9:02 PM Garmin.Chang <Garmin.Chang@mediatek.com> wrote:
>
> Add MT8188 adsp clock controller which provides clock gate
> control for Audio DSP.
>
> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
> ---
>  drivers/clk/mediatek/Makefile                 |  2 +-
>  .../clk/mediatek/clk-mt8188-adsp_audio26m.c   | 45 +++++++++++++++++++
>  2 files changed, 46 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/clk/mediatek/clk-mt8188-adsp_audio26m.c
>
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index 8befaedfdd3d..b56ae9bee1d8 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -89,7 +89,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o
>                                    clk-mt8188-ipe.o clk-mt8188-mfg.o clk-mt8188-vdec.o \
>                                    clk-mt8188-vdo0.o clk-mt8188-vdo1.o clk-mt8188-venc.o \
>                                    clk-mt8188-vpp0.o clk-mt8188-vpp1.o clk-mt8188-wpe.o \
> -                                  clk-mt8188-imp_iic_wrap.o
> +                                  clk-mt8188-imp_iic_wrap.o clk-mt8188-adsp_audio26m.o
>  obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
>  obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
>  obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> diff --git a/drivers/clk/mediatek/clk-mt8188-adsp_audio26m.c b/drivers/clk/mediatek/clk-mt8188-adsp_audio26m.c
> new file mode 100644
> index 000000000000..f91381a1316c
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8188-adsp_audio26m.c
> @@ -0,0 +1,45 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +//
> +// Copyright (c) 2022 MediaTek Inc.
> +// Author: Garmin Chang <garmin.chang@mediatek.com>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> +
> +#include "clk-gate.h"
> +#include "clk-mtk.h"
> +
> +static const struct mtk_gate_regs adsp_audio26m_cg_regs = {
> +       .set_ofs = 0x80,
> +       .clr_ofs = 0x80,
> +       .sta_ofs = 0x80,
> +};
> +
> +#define GATE_ADSP_FLAGS(_id, _name, _parent, _shift)           \
> +       GATE_MTK_FLAGS(_id, _name, _parent, &adsp_audio26m_cg_regs, _shift,             \
> +               &mtk_clk_gate_ops_no_setclr, CLK_IGNORE_UNUSED)

Why CLK_IGNORE_UNUSED?

Re: [PATCH v5 02/19] clk: mediatek: Add MT8188 apmixedsys clock support

[Chen-Yu Tsai]

On Thu, Jan 19, 2023 at 8:54 PM Garmin.Chang <Garmin.Chang@mediatek.com> wrote:
>
> Add MT8188 apmixedsys clock controller which provides Plls
> generated from SoC 26m and ssusb clock gate control.
>
> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
> ---
>  drivers/clk/mediatek/Kconfig                 |  11 ++
>  drivers/clk/mediatek/Makefile                |   1 +
>  drivers/clk/mediatek/clk-mt8188-apmixedsys.c | 154 +++++++++++++++++++
>  3 files changed, 166 insertions(+)
>  create mode 100644 drivers/clk/mediatek/clk-mt8188-apmixedsys.c
>
> diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
> index 22e8e79475ee..f02b679f71d0 100644
> --- a/drivers/clk/mediatek/Kconfig
> +++ b/drivers/clk/mediatek/Kconfig
> @@ -565,6 +565,17 @@ config COMMON_CLK_MT8186
>         help
>           This driver supports MediaTek MT8186 clocks.
>
> +config COMMON_CLK_MT8188
> +       bool "Clock driver for MediaTek MT8188"
> +       depends on ARM64 || COMPILE_TEST
> +       select COMMON_CLK_MEDIATEK
> +       default ARCH_MEDIATEK
> +       help
> +         This driver supports MediaTek MT8188 basic clocks and clocks
> +         required for various peripheral found on MediaTek. Choose
> +         M or Y here if you want to use clocks such as peri_ao,
> +         infra_ao, etc.
> +
>  config COMMON_CLK_MT8192
>         bool "Clock driver for MediaTek MT8192"
>         depends on ARM64 || COMPILE_TEST
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index e24080fd6e7f..13ab8deb362c 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -83,6 +83,7 @@ obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt
>                                    clk-mt8186-mfg.o clk-mt8186-mm.o clk-mt8186-wpe.o \
>                                    clk-mt8186-img.o clk-mt8186-vdec.o clk-mt8186-venc.o \
>                                    clk-mt8186-cam.o clk-mt8186-mdp.o clk-mt8186-ipe.o
> +obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o
>  obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
>  obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
>  obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> diff --git a/drivers/clk/mediatek/clk-mt8188-apmixedsys.c b/drivers/clk/mediatek/clk-mt8188-apmixedsys.c
> new file mode 100644
> index 000000000000..8d73ae3a0da8
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8188-apmixedsys.c
> @@ -0,0 +1,154 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +//
> +// Copyright (c) 2022 MediaTek Inc.
> +// Author: Garmin Chang <garmin.chang@mediatek.com>
> +
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> +
> +#include "clk-gate.h"
> +#include "clk-mtk.h"
> +#include "clk-pll.h"
> +
> +static const struct mtk_gate_regs apmixed_cg_regs = {
> +       .set_ofs = 0x8,
> +       .clr_ofs = 0x8,
> +       .sta_ofs = 0x8,
> +};
> +
> +#define GATE_APMIXED(_id, _name, _parent, _shift)                      \
> +       GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
> +
> +static const struct mtk_gate apmixed_clks[] = {
> +       GATE_APMIXED(CLK_APMIXED_PLL_SSUSB26M_EN, "pll_ssusb26m_en", "clk26m", 1),
> +};
> +
> +#define MT8188_PLL_FMAX                (3800UL * MHZ)
> +#define MT8188_PLL_FMIN                (1500UL * MHZ)
> +#define MT8188_INTEGER_BITS    8
> +
> +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags,              \
> +           _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift,                \
> +           _tuner_reg, _tuner_en_reg, _tuner_en_bit,                   \
> +           _pcw_reg, _pcw_shift, _pcw_chg_reg,                         \
> +           _en_reg, _pll_en_bit) {                                     \
> +               .id = _id,                                              \
> +               .name = _name,                                          \
> +               .reg = _reg,                                            \
> +               .pwr_reg = _pwr_reg,                                    \
> +               .en_mask = _en_mask,                                    \
> +               .flags = _flags,                                        \
> +               .rst_bar_mask = _rst_bar_mask,                          \
> +               .fmax = MT8188_PLL_FMAX,                                \
> +               .fmin = MT8188_PLL_FMIN,                                \
> +               .pcwbits = _pcwbits,                                    \
> +               .pcwibits = MT8188_INTEGER_BITS,                        \
> +               .pd_reg = _pd_reg,                                      \
> +               .pd_shift = _pd_shift,                                  \
> +               .tuner_reg = _tuner_reg,                                \
> +               .tuner_en_reg = _tuner_en_reg,                          \
> +               .tuner_en_bit = _tuner_en_bit,                          \
> +               .pcw_reg = _pcw_reg,                                    \
> +               .pcw_shift = _pcw_shift,                                \
> +               .pcw_chg_reg = _pcw_chg_reg,                            \
> +               .en_reg = _en_reg,                                      \
> +               .pll_en_bit = _pll_en_bit,                              \
> +       }
> +
> +static const struct mtk_pll_data plls[] = {
> +       PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x044C, 0x0458, 0,
> +           0, 0, 22, 0x0450, 24, 0, 0, 0, 0x0450, 0, 0, 0, 9),
> +       PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0514, 0x0520, 0,
> +           0, 0, 22, 0x0518, 24, 0, 0, 0, 0x0518, 0, 0, 0, 9),
> +       PLL(CLK_APMIXED_TVDPLL1, "tvdpll1", 0x0524, 0x0530, 0,
> +           0, 0, 22, 0x0528, 24, 0, 0, 0, 0x0528, 0, 0, 0, 9),
> +       PLL(CLK_APMIXED_TVDPLL2, "tvdpll2", 0x0534, 0x0540, 0,
> +           0, 0, 22, 0x0538, 24, 0, 0, 0, 0x0538, 0, 0, 0, 9),
> +       PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0544, 0x0550, 0xff000000,
> +           HAVE_RST_BAR, BIT(23), 22, 0x0548, 24, 0, 0, 0, 0x0548, 0, 0, 0, 9),
> +       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x045C, 0x0468, 0xff000000,
> +           HAVE_RST_BAR, BIT(23), 22, 0x0460, 24, 0, 0, 0, 0x0460, 0, 0, 0, 9),
> +       PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0554, 0x0560, 0,
> +           0, 0, 22, 0x0558, 24, 0, 0, 0, 0x0558, 0, 0, 0, 9),
> +       PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0504, 0x0510, 0xff000000,
> +           HAVE_RST_BAR, BIT(23), 22, 0x0508, 24, 0, 0, 0, 0x0508, 0, 0, 0, 9),
> +       PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x042C, 0x0438, 0,
> +           0, 0, 22, 0x0430, 24, 0, 0, 0, 0x0430, 0, 0, 0, 9),
> +       PLL(CLK_APMIXED_APLL1, "apll1", 0x0304, 0x0314, 0,
> +           0, 0, 32, 0x0308, 24, 0x0034, 0x0000, 12, 0x030C, 0, 0, 0, 9),
> +       PLL(CLK_APMIXED_APLL2, "apll2", 0x0318, 0x0328, 0,
> +           0, 0, 32, 0x031C, 24, 0x0038, 0x0000, 13, 0x0320, 0, 0, 0, 9),
> +       PLL(CLK_APMIXED_APLL3, "apll3", 0x032C, 0x033C, 0,
> +           0, 0, 32, 0x0330, 24, 0x003C, 0x0000, 14, 0x0334, 0, 0, 0, 9),
> +       PLL(CLK_APMIXED_APLL4, "apll4", 0x0404, 0x0414, 0,
> +           0, 0, 32, 0x0408, 24, 0x0040, 0x0000, 15, 0x040C, 0, 0, 0, 9),
> +       PLL(CLK_APMIXED_APLL5, "apll5", 0x0418, 0x0428, 0,
> +           0, 0, 32, 0x041C, 24, 0x0044, 0x0000, 16, 0x0420, 0, 0, 0, 9),
> +       PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0340, 0x034C, 0,
> +           0, 0, 22, 0x0344, 24, 0, 0, 0, 0x0344, 0, 0, 0, 9),
> +};
> +
> +static const struct of_device_id of_match_clk_mt8188_apmixed[] = {
> +       { .compatible = "mediatek,mt8188-apmixedsys", },
> +       {}
> +};
> +
> +static int clk_mt8188_apmixed_probe(struct platform_device *pdev)
> +{
> +       struct clk_hw_onecell_data *clk_data;
> +       struct device_node *node = pdev->dev.of_node;
> +       int r;
> +
> +       clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
> +       if (!clk_data)
> +               return -ENOMEM;
> +
> +       r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
> +       if (r)
> +               goto free_apmixed_data;
> +
> +       r = mtk_clk_register_gates_with_dev(node, apmixed_clks,
> +               ARRAY_SIZE(apmixed_clks), clk_data, NULL);

This API is gone. Please replace it with mtk_clk_register_clks. And please
pass in the |struct device| pointer.

ChenYu

Re: [PATCH v5 12/19] clk: mediatek: Add MT8188 vdosys0 clock support

[AngeloGioacchino Del Regno]

Il 03/02/23 08:19, Chen-Yu Tsai ha scritto:
> On Thu, Jan 19, 2023 at 8:54 PM Garmin.Chang <Garmin.Chang@mediatek.com> wrote:
>>
>> Add MT8188 vdosys0 clock controller which provides clock gate
>> control in video system. This is integrated with mtk-mmsys
>> driver which will populate device by platform_device_register_data
>> to start vdosys clock driver.
>>
>> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
>> ---
>>   drivers/clk/mediatek/Makefile          |   3 +-
>>   drivers/clk/mediatek/clk-mt8188-vdo0.c | 134 +++++++++++++++++++++++++
>>   2 files changed, 136 insertions(+), 1 deletion(-)
>>   create mode 100644 drivers/clk/mediatek/clk-mt8188-vdo0.c
>>
>> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
>> index 7d09e9fc6538..df78c0777fef 100644
>> --- a/drivers/clk/mediatek/Makefile
>> +++ b/drivers/clk/mediatek/Makefile
>> @@ -86,7 +86,8 @@ obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt
>>   obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o \
>>                                     clk-mt8188-peri_ao.o clk-mt8188-infra_ao.o \
>>                                     clk-mt8188-cam.o clk-mt8188-ccu.o clk-mt8188-img.o \
>> -                                  clk-mt8188-ipe.o clk-mt8188-mfg.o clk-mt8188-vdec.o
>> +                                  clk-mt8188-ipe.o clk-mt8188-mfg.o clk-mt8188-vdec.o \
>> +                                  clk-mt8188-vdo0.o
>>   obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
>>   obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
>>   obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
>> diff --git a/drivers/clk/mediatek/clk-mt8188-vdo0.c b/drivers/clk/mediatek/clk-mt8188-vdo0.c
>> new file mode 100644
>> index 000000000000..30dd64374ace
>> --- /dev/null
>> +++ b/drivers/clk/mediatek/clk-mt8188-vdo0.c
>> @@ -0,0 +1,134 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +//
>> +// Copyright (c) 2022 MediaTek Inc.
>> +// Author: Garmin Chang <garmin.chang@mediatek.com>
>> +
>> +#include <linux/clk-provider.h>
>> +#include <linux/platform_device.h>
>> +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
>> +
>> +#include "clk-gate.h"
>> +#include "clk-mtk.h"
>> +
>> +static const struct mtk_gate_regs vdo0_0_cg_regs = {
>> +       .set_ofs = 0x104,
>> +       .clr_ofs = 0x108,
>> +       .sta_ofs = 0x100,
>> +};
>> +
>> +static const struct mtk_gate_regs vdo0_1_cg_regs = {
>> +       .set_ofs = 0x114,
>> +       .clr_ofs = 0x118,
>> +       .sta_ofs = 0x110,
>> +};
>> +
>> +static const struct mtk_gate_regs vdo0_2_cg_regs = {
>> +       .set_ofs = 0x124,
>> +       .clr_ofs = 0x128,
>> +       .sta_ofs = 0x120,
>> +};
>> +
>> +#define GATE_VDO0_0(_id, _name, _parent, _shift)                       \
>> +       GATE_MTK(_id, _name, _parent, &vdo0_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
>> +
>> +#define GATE_VDO0_1(_id, _name, _parent, _shift)                       \
>> +       GATE_MTK(_id, _name, _parent, &vdo0_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
>> +
>> +#define GATE_VDO0_2(_id, _name, _parent, _shift)                       \
>> +       GATE_MTK(_id, _name, _parent, &vdo0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
>> +
>> +#define GATE_VDO0_2_FLAGS(_id, _name, _parent, _shift, _flags)         \
>> +       GATE_MTK_FLAGS(_id, _name, _parent, &vdo0_2_cg_regs, _shift,    \
>> +       &mtk_clk_gate_ops_setclr, _flags)
>> +
>> +static const struct mtk_gate vdo0_clks[] = {
>> +       /* VDO0_0 */
>> +       GATE_VDO0_0(CLK_VDO0_DISP_OVL0, "vdo0_disp_ovl0", "top_vpp", 0),
>> +       GATE_VDO0_0(CLK_VDO0_FAKE_ENG0, "vdo0_fake_eng0", "top_vpp", 2),
>> +       GATE_VDO0_0(CLK_VDO0_DISP_CCORR0, "vdo0_disp_ccorr0", "top_vpp", 4),
>> +       GATE_VDO0_0(CLK_VDO0_DISP_MUTEX0, "vdo0_disp_mutex0", "top_vpp", 6),
>> +       GATE_VDO0_0(CLK_VDO0_DISP_GAMMA0, "vdo0_disp_gamma0", "top_vpp", 8),
>> +       GATE_VDO0_0(CLK_VDO0_DISP_DITHER0, "vdo0_disp_dither0", "top_vpp", 10),
>> +       GATE_VDO0_0(CLK_VDO0_DISP_WDMA0, "vdo0_disp_wdma0", "top_vpp", 17),
>> +       GATE_VDO0_0(CLK_VDO0_DISP_RDMA0, "vdo0_disp_rdma0", "top_vpp", 19),
>> +       GATE_VDO0_0(CLK_VDO0_DSI0, "vdo0_dsi0", "top_vpp", 21),
>> +       GATE_VDO0_0(CLK_VDO0_DSI1, "vdo0_dsi1", "top_vpp", 22),
>> +       GATE_VDO0_0(CLK_VDO0_DSC_WRAP0, "vdo0_dsc_wrap0", "top_vpp", 23),
>> +       GATE_VDO0_0(CLK_VDO0_VPP_MERGE0, "vdo0_vpp_merge0", "top_vpp", 24),
>> +       GATE_VDO0_0(CLK_VDO0_DP_INTF0, "vdo0_dp_intf0", "top_vpp", 25),
>> +       GATE_VDO0_0(CLK_VDO0_DISP_AAL0, "vdo0_disp_aal0", "top_vpp", 26),
>> +       GATE_VDO0_0(CLK_VDO0_INLINEROT0, "vdo0_inlinerot0", "top_vpp", 27),
>> +       GATE_VDO0_0(CLK_VDO0_APB_BUS, "vdo0_apb_bus", "top_vpp", 28),
>> +       GATE_VDO0_0(CLK_VDO0_DISP_COLOR0, "vdo0_disp_color0", "top_vpp", 29),
>> +       GATE_VDO0_0(CLK_VDO0_MDP_WROT0, "vdo0_mdp_wrot0", "top_vpp", 30),
>> +       GATE_VDO0_0(CLK_VDO0_DISP_RSZ0, "vdo0_disp_rsz0", "top_vpp", 31),
>> +       /* VDO0_1 */
>> +       GATE_VDO0_1(CLK_VDO0_DISP_POSTMASK0, "vdo0_disp_postmask0", "top_vpp", 0),
>> +       GATE_VDO0_1(CLK_VDO0_FAKE_ENG1, "vdo0_fake_eng1", "top_vpp", 1),
>> +       GATE_VDO0_1(CLK_VDO0_DL_ASYNC2, "vdo0_dl_async2", "top_vpp", 5),
>> +       GATE_VDO0_1(CLK_VDO0_DL_RELAY3, "vdo0_dl_relay3", "top_vpp", 6),
>> +       GATE_VDO0_1(CLK_VDO0_DL_RELAY4, "vdo0_dl_relay4", "top_vpp", 7),
>> +       GATE_VDO0_1(CLK_VDO0_SMI_GALS, "vdo0_smi_gals", "top_vpp", 10),
>> +       GATE_VDO0_1(CLK_VDO0_SMI_COMMON, "vdo0_smi_common", "top_vpp", 11),
>> +       GATE_VDO0_1(CLK_VDO0_SMI_EMI, "vdo0_smi_emi", "top_vpp", 12),
>> +       GATE_VDO0_1(CLK_VDO0_SMI_IOMMU, "vdo0_smi_iommu", "top_vpp", 13),
>> +       GATE_VDO0_1(CLK_VDO0_SMI_LARB, "vdo0_smi_larb", "top_vpp", 14),
>> +       GATE_VDO0_1(CLK_VDO0_SMI_RSI, "vdo0_smi_rsi", "top_vpp", 15),
>> +       /* VDO0_2 */
>> +       GATE_VDO0_2(CLK_VDO0_DSI0_DSI, "vdo0_dsi0_dsi", "top_dsi_occ", 0),
>> +       GATE_VDO0_2(CLK_VDO0_DSI1_DSI, "vdo0_dsi1_dsi", "top_dsi_occ", 8),
>> +       GATE_VDO0_2_FLAGS(CLK_VDO0_DP_INTF0_DP_INTF, "vdo0_dp_intf0_dp_intf",
>> +               "top_edp", 16, CLK_SET_RATE_PARENT),
>> +};
>> +
>> +static int clk_mt8188_vdo0_probe(struct platform_device *pdev)
>> +{
>> +       struct device *dev = &pdev->dev;
>> +       struct device_node *node = dev->parent->of_node;
>> +       struct clk_hw_onecell_data *clk_data;
>> +       int r;
>> +
>> +       clk_data = mtk_alloc_clk_data(CLK_VDO0_NR_CLK);
>> +       if (!clk_data)
>> +               return -ENOMEM;
>> +
>> +       r = mtk_clk_register_gates(node, vdo0_clks, ARRAY_SIZE(vdo0_clks), clk_data);
> 
> This API was changed. Please rebase onto the latest -next and update.
> 
> Angelo (CC-ed) also mentioned a new simple probe variant for non-DT
> clock drivers is being developed. He didn't mention a timeline though.

I've already tested the new simple probe variant for non-DT clock drivers and
it works fine on MT8173, MT8192 and MT8195.

Timeline - I should be able to push the part 2 series next week, which will include
more conversion to simple probe and almost all clock drivers changed to allow
building as modules.

Cheers,
Angelo

Re: [PATCH v5 00/19] MediaTek MT8188 clock support

[Garmin Chang (張家銘)]

On Fri, 2023-02-03 at 14:23 +0800, Chen-Yu Tsai wrote:
> On Thu, Jan 19, 2023 at 8:49 PM Garmin.Chang <
> Garmin.Chang@mediatek.com> wrote:
> > 
> > Base on tag: next-20230119, linux-next/master
> 
> There are some recent changes to the MediaTek clk driver library
> that makes this series incompatible. Could you rebase onto next-
> 202302xx
> and send a new version?
> 
> Thanks

OK. I'll rebase onto next 202303xx, thanks.

Re: [PATCH v5 19/19] clk: mediatek: Add MT8188 adsp clock support

[Garmin Chang (張家銘)]

On Fri, 2023-02-03 at 15:39 +0800, Chen-Yu Tsai wrote:
> On Thu, Jan 19, 2023 at 9:02 PM Garmin.Chang <
> Garmin.Chang@mediatek.com> wrote:
> > 
> > Add MT8188 adsp clock controller which provides clock gate
> > control for Audio DSP.
> > 
> > Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
> > ---
> >  drivers/clk/mediatek/Makefile                 |  2 +-
> >  .../clk/mediatek/clk-mt8188-adsp_audio26m.c   | 45
> > +++++++++++++++++++
> >  2 files changed, 46 insertions(+), 1 deletion(-)
> >  create mode 100644 drivers/clk/mediatek/clk-mt8188-adsp_audio26m.c
> > 
> > diff --git a/drivers/clk/mediatek/Makefile
> > b/drivers/clk/mediatek/Makefile
> > index 8befaedfdd3d..b56ae9bee1d8 100644
> > --- a/drivers/clk/mediatek/Makefile
> > +++ b/drivers/clk/mediatek/Makefile
> > @@ -89,7 +89,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-
> > apmixedsys.o clk-mt8188-topckgen.o
> >                                    clk-mt8188-ipe.o clk-mt8188-
> > mfg.o clk-mt8188-vdec.o \
> >                                    clk-mt8188-vdo0.o clk-mt8188-
> > vdo1.o clk-mt8188-venc.o \
> >                                    clk-mt8188-vpp0.o clk-mt8188-
> > vpp1.o clk-mt8188-wpe.o \
> > -                                  clk-mt8188-imp_iic_wrap.o
> > +                                  clk-mt8188-imp_iic_wrap.o clk-
> > mt8188-adsp_audio26m.o
> >  obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
> >  obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
> >  obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> > diff --git a/drivers/clk/mediatek/clk-mt8188-adsp_audio26m.c
> > b/drivers/clk/mediatek/clk-mt8188-adsp_audio26m.c
> > new file mode 100644
> > index 000000000000..f91381a1316c
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt8188-adsp_audio26m.c
> > @@ -0,0 +1,45 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +//
> > +// Copyright (c) 2022 MediaTek Inc.
> > +// Author: Garmin Chang <garmin.chang@mediatek.com>
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/platform_device.h>
> > +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> > +
> > +#include "clk-gate.h"
> > +#include "clk-mtk.h"
> > +
> > +static const struct mtk_gate_regs adsp_audio26m_cg_regs = {
> > +       .set_ofs = 0x80,
> > +       .clr_ofs = 0x80,
> > +       .sta_ofs = 0x80,
> > +};
> > +
> > +#define GATE_ADSP_FLAGS(_id, _name, _parent, _shift)           \
> > +       GATE_MTK_FLAGS(_id, _name, _parent, &adsp_audio26m_cg_regs,
> > _shift,             \
> > +               &mtk_clk_gate_ops_no_setclr, CLK_IGNORE_UNUSED)
> 
> Why CLK_IGNORE_UNUSED?

Thank you for your review.

Because ADSP_INFRA is always on, it is unnecessary to add
CLK_IGNORE_UNUSED now.  I wiil remove it in v6. Please see commit

https://patchwork.kernel.org/project/linux-mediatek/patch/20221223080553.9397-3-Garmin.Chang@mediatek.com/

Add ignore_unused before to avoid "ADSP_INFRA is turned off". If
ADSP_INFRA is turned off, accessing registers will cause the system to
hang.

Re: [PATCH v5 16/19] clk: mediatek: Add MT8188 vppsys1 clock support

[Garmin Chang (張家銘)]

On Fri, 2023-02-03 at 15:35 +0800, Chen-Yu Tsai wrote:
> On Thu, Jan 19, 2023 at 8:58 PM Garmin.Chang <
> Garmin.Chang@mediatek.com> wrote:
> > 
> > Add MT8188 vppsys1 clock controller which provides clock gate
> > controller for Video Processor Pipe.
> > 
> > Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
> > ---
> >  drivers/clk/mediatek/Makefile          |   2 +-
> >  drivers/clk/mediatek/clk-mt8188-vpp1.c | 138
> > +++++++++++++++++++++++++
> >  2 files changed, 139 insertions(+), 1 deletion(-)
> >  create mode 100644 drivers/clk/mediatek/clk-mt8188-vpp1.c
> > 
> > diff --git a/drivers/clk/mediatek/Makefile
> > b/drivers/clk/mediatek/Makefile
> > index 48deecc6b520..37663de293bf 100644
> > --- a/drivers/clk/mediatek/Makefile
> > +++ b/drivers/clk/mediatek/Makefile
> > @@ -88,7 +88,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-
> > apmixedsys.o clk-mt8188-topckgen.o
> >                                    clk-mt8188-cam.o clk-mt8188-
> > ccu.o clk-mt8188-img.o \
> >                                    clk-mt8188-ipe.o clk-mt8188-
> > mfg.o clk-mt8188-vdec.o \
> >                                    clk-mt8188-vdo0.o clk-mt8188-
> > vdo1.o clk-mt8188-venc.o \
> > -                                  clk-mt8188-vpp0.o
> > +                                  clk-mt8188-vpp0.o clk-mt8188-
> > vpp1.o
> >  obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
> >  obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
> >  obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> > diff --git a/drivers/clk/mediatek/clk-mt8188-vpp1.c
> > b/drivers/clk/mediatek/clk-mt8188-vpp1.c
> > new file mode 100644
> > index 000000000000..2bff3a52c93f
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt8188-vpp1.c
> > @@ -0,0 +1,138 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +//
> > +// Copyright (c) 2022 MediaTek Inc.
> > +// Author: Garmin Chang <garmin.chang@mediatek.com>
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/platform_device.h>
> > +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> > +
> > +#include "clk-gate.h"
> > +#include "clk-mtk.h"
> > +
> > +static const struct mtk_gate_regs vpp1_0_cg_regs = {
> > +       .set_ofs = 0x104,
> > +       .clr_ofs = 0x108,
> > +       .sta_ofs = 0x100,
> > +};
> > +
> > +static const struct mtk_gate_regs vpp1_1_cg_regs = {
> > +       .set_ofs = 0x114,
> > +       .clr_ofs = 0x118,
> > +       .sta_ofs = 0x110,
> > +};
> > +
> > +#define GATE_VPP1_0(_id, _name, _parent,
> > _shift)                       \
> > +       GATE_MTK(_id, _name, _parent, &vpp1_0_cg_regs, _shift,
> > &mtk_clk_gate_ops_setclr)
> > +
> > +#define GATE_VPP1_1(_id, _name, _parent,
> > _shift)                       \
> > +       GATE_MTK(_id, _name, _parent, &vpp1_1_cg_regs, _shift,
> > &mtk_clk_gate_ops_setclr)
> > +
> > +static const struct mtk_gate vpp1_clks[] = {
> > +       /* VPP1_0 */
> > +       GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_OVL, "vpp1_svpp1_mdp_ovl",
> > "top_vpp", 0),
> > +       GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_TCC, "vpp1_svpp1_mdp_tcc",
> > "top_vpp", 1),
> > +       GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_WROT, "vpp1_svpp1_mdp_wrot",
> > "top_vpp", 2),
> > +       GATE_VPP1_0(CLK_VPP1_SVPP1_VPP_PAD, "vpp1_svpp1_vpp_pad",
> > "top_vpp", 3),
> > +       GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_WROT, "vpp1_svpp2_mdp_wrot",
> > "top_vpp", 4),
> > +       GATE_VPP1_0(CLK_VPP1_SVPP2_VPP_PAD, "vpp1_svpp2_vpp_pad",
> > "top_vpp", 5),
> > +       GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_WROT, "vpp1_svpp3_mdp_wrot",
> > "top_vpp", 6),
> > +       GATE_VPP1_0(CLK_VPP1_SVPP3_VPP_PAD, "vpp1_svpp3_vpp_pad",
> > "top_vpp", 7),
> > +       GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_RDMA, "vpp1_svpp1_mdp_rdma",
> > "top_vpp", 8),
> > +       GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_FG, "vpp1_svpp1_mdp_fg",
> > "top_vpp", 9),
> > +       GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_RDMA, "vpp1_svpp2_mdp_rdma",
> > "top_vpp", 10),
> > +       GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_FG, "vpp1_svpp2_mdp_fg",
> > "top_vpp", 11),
> > +       GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_RDMA, "vpp1_svpp3_mdp_rdma",
> > "top_vpp", 12),
> > +       GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_FG, "vpp1_svpp3_mdp_fg",
> > "top_vpp", 13),
> > +       GATE_VPP1_0(CLK_VPP1_VPP_SPLIT, "vpp1_vpp_split",
> > "top_vpp", 14),
> > +       GATE_VPP1_0(CLK_VPP1_SVPP2_VDO0_DL_RELAY,
> > "vpp1_svpp2_vdo0_dl_relay", "top_vpp", 15),
> > +       GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_RSZ, "vpp1_svpp1_mdp_rsz",
> > "top_vpp", 16),
> > +       GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_TDSHP,
> > "vpp1_svpp1_mdp_tdshp", "top_vpp", 17),
> > +       GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_COLOR,
> > "vpp1_svpp1_mdp_color", "top_vpp", 18),
> > +       GATE_VPP1_0(CLK_VPP1_SVPP3_VDO1_DL_RELAY,
> > "vpp1_svpp3_vdo1_dl_relay", "top_vpp", 19),
> > +       GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_RSZ, "vpp1_svpp2_mdp_rsz",
> > "top_vpp", 20),
> > +       GATE_VPP1_0(CLK_VPP1_SVPP2_VPP_MERGE,
> > "vpp1_svpp2_vpp_merge", "top_vpp", 21),
> > +       GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_TDSHP,
> > "vpp1_svpp2_mdp_tdshp", "top_vpp", 22),
> > +       GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_COLOR,
> > "vpp1_svpp2_mdp_color", "top_vpp", 23),
> > +       GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_RSZ, "vpp1_svpp3_mdp_rsz",
> > "top_vpp", 24),
> > +       GATE_VPP1_0(CLK_VPP1_SVPP3_VPP_MERGE,
> > "vpp1_svpp3_vpp_merge", "top_vpp", 25),
> > +       GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_TDSHP,
> > "vpp1_svpp3_mdp_tdshp", "top_vpp", 26),
> > +       GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_COLOR,
> > "vpp1_svpp3_mdp_color", "top_vpp", 27),
> > +       GATE_VPP1_0(CLK_VPP1_GALS5, "vpp1_gals5", "top_vpp", 28),
> > +       GATE_VPP1_0(CLK_VPP1_GALS6, "vpp1_gals6", "top_vpp", 29),
> > +       GATE_VPP1_0(CLK_VPP1_LARB5, "vpp1_larb5", "top_vpp", 30),
> > +       GATE_VPP1_0(CLK_VPP1_LARB6, "vpp1_larb6", "top_vpp", 31),
> > +       /* VPP1_1 */
> > +       GATE_VPP1_1(CLK_VPP1_SVPP1_MDP_HDR, "vpp1_svpp1_mdp_hdr",
> > "top_vpp", 0),
> > +       GATE_VPP1_1(CLK_VPP1_SVPP1_MDP_AAL, "vpp1_svpp1_mdp_aal",
> > "top_vpp", 1),
> > +       GATE_VPP1_1(CLK_VPP1_SVPP2_MDP_HDR, "vpp1_svpp2_mdp_hdr",
> > "top_vpp", 2),
> > +       GATE_VPP1_1(CLK_VPP1_SVPP2_MDP_AAL, "vpp1_svpp2_mdp_aal",
> > "top_vpp", 3),
> > +       GATE_VPP1_1(CLK_VPP1_SVPP3_MDP_HDR, "vpp1_svpp3_mdp_hdr",
> > "top_vpp", 4),
> > +       GATE_VPP1_1(CLK_VPP1_SVPP3_MDP_AAL, "vpp1_svpp3_mdp_aal",
> > "top_vpp", 5),
> > +       GATE_VPP1_1(CLK_VPP1_DISP_MUTEX, "vpp1_disp_mutex",
> > "top_vpp", 7),
> > +       GATE_VPP1_1(CLK_VPP1_SVPP2_VDO1_DL_RELAY,
> > "vpp1_svpp2_vdo1_dl_relay", "top_vpp", 8),
> > +       GATE_VPP1_1(CLK_VPP1_SVPP3_VDO0_DL_RELAY,
> > "vpp1_svpp3_vdo0_dl_relay", "top_vpp", 9),
> > +       GATE_VPP1_1(CLK_VPP1_VPP0_DL_ASYNC, "vpp1_vpp0_dl_async",
> > "top_vpp", 10),
> > +       GATE_VPP1_1(CLK_VPP1_VPP0_DL1_RELAY, "vpp1_vpp0_dl1_relay",
> > "top_vpp", 11),
> > +       GATE_VPP1_1(CLK_VPP1_LARB5_FAKE_ENG, "vpp1_larb5_fake_eng",
> > "top_vpp", 12),
> > +       GATE_VPP1_1(CLK_VPP1_LARB6_FAKE_ENG, "vpp1_larb6_fake_eng",
> > "top_vpp", 13),
> > +       GATE_VPP1_1(CLK_VPP1_HDMI_META, "vpp1_hdmi_meta",
> > "top_vpp", 16),
> > +       GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_HDMI, "vpp1_vpp_split_hdmi",
> > "top_vpp", 17),
> > +       GATE_VPP1_1(CLK_VPP1_DGI_IN, "vpp1_dgi_in", "top_vpp", 18),
> > +       GATE_VPP1_1(CLK_VPP1_DGI_OUT, "vpp1_dgi_out", "top_vpp",
> > 19),
> > +       GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_DGI, "vpp1_vpp_split_dgi",
> > "top_vpp", 20),
> > +       GATE_VPP1_1(CLK_VPP1_DL_CON_OCC, "vpp1_dl_con_occ",
> > "top_vpp", 21),
> > +       GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_26M, "vpp1_vpp_split_26m",
> > "top_vpp", 26),
> > +};
> > +
> > +static int clk_mt8188_vpp1_probe(struct platform_device *pdev)
> > +{
> > +       struct device *dev = &pdev->dev;
> > +       struct device_node *node = dev->parent->of_node;
> > +       struct clk_hw_onecell_data *clk_data;
> > +       int r;
> > +
> > +       clk_data = mtk_alloc_clk_data(CLK_VPP1_NR_CLK);
> > +       if (!clk_data)
> > +               return -ENOMEM;
> > +
> > +       r = mtk_clk_register_gates(node, vpp1_clks,
> > ARRAY_SIZE(vpp1_clks), clk_data);
> 
> Same here. Please update.

Thank you for your suggestions.
OK. I'll moidfy it in v6.

> 
> Once fixed,
> 
> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>

Re: [PATCH v5 15/19] clk: mediatek: Add MT8188 vppsys0 clock support

[Garmin Chang (張家銘)]

On Fri, 2023-02-03 at 15:33 +0800, Chen-Yu Tsai wrote:
> On Thu, Jan 19, 2023 at 8:54 PM Garmin.Chang <
> Garmin.Chang@mediatek.com> wrote:
> > 
> > Add MT8188 vppsys0 clock controller which provides clock gate
> > controller for Video Processor Pipe.
> > 
> > Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
> > ---
> >  drivers/clk/mediatek/Makefile          |   3 +-
> >  drivers/clk/mediatek/clk-mt8188-vpp0.c | 143
> > +++++++++++++++++++++++++
> >  2 files changed, 145 insertions(+), 1 deletion(-)
> >  create mode 100644 drivers/clk/mediatek/clk-mt8188-vpp0.c
> > 
> > diff --git a/drivers/clk/mediatek/Makefile
> > b/drivers/clk/mediatek/Makefile
> > index 22a3840160fc..48deecc6b520 100644
> > --- a/drivers/clk/mediatek/Makefile
> > +++ b/drivers/clk/mediatek/Makefile
> > @@ -87,7 +87,8 @@ obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-
> > apmixedsys.o clk-mt8188-topckgen.o
> >                                    clk-mt8188-peri_ao.o clk-mt8188-
> > infra_ao.o \
> >                                    clk-mt8188-cam.o clk-mt8188-
> > ccu.o clk-mt8188-img.o \
> >                                    clk-mt8188-ipe.o clk-mt8188-
> > mfg.o clk-mt8188-vdec.o \
> > -                                  clk-mt8188-vdo0.o clk-mt8188-
> > vdo1.o clk-mt8188-venc.o
> > +                                  clk-mt8188-vdo0.o clk-mt8188-
> > vdo1.o clk-mt8188-venc.o \
> > +                                  clk-mt8188-vpp0.o
> >  obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
> >  obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
> >  obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> > diff --git a/drivers/clk/mediatek/clk-mt8188-vpp0.c
> > b/drivers/clk/mediatek/clk-mt8188-vpp0.c
> > new file mode 100644
> > index 000000000000..e7b46142d653
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt8188-vpp0.c
> > @@ -0,0 +1,143 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +//
> > +// Copyright (c) 2022 MediaTek Inc.
> > +// Author: Garmin Chang <garmin.chang@mediatek.com>
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/platform_device.h>
> > +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> > +
> > +#include "clk-gate.h"
> > +#include "clk-mtk.h"
> > +
> > +static const struct mtk_gate_regs vpp0_0_cg_regs = {
> > +       .set_ofs = 0x24,
> > +       .clr_ofs = 0x28,
> > +       .sta_ofs = 0x20,
> > +};
> > +
> > +static const struct mtk_gate_regs vpp0_1_cg_regs = {
> > +       .set_ofs = 0x30,
> > +       .clr_ofs = 0x34,
> > +       .sta_ofs = 0x2c,
> > +};
> > +
> > +static const struct mtk_gate_regs vpp0_2_cg_regs = {
> > +       .set_ofs = 0x3c,
> > +       .clr_ofs = 0x40,
> > +       .sta_ofs = 0x38,
> > +};
> > +
> > +#define GATE_VPP0_0(_id, _name, _parent,
> > _shift)                       \
> > +       GATE_MTK(_id, _name, _parent, &vpp0_0_cg_regs, _shift,
> > &mtk_clk_gate_ops_setclr)
> > +
> > +#define GATE_VPP0_1(_id, _name, _parent,
> > _shift)                       \
> > +       GATE_MTK(_id, _name, _parent, &vpp0_1_cg_regs, _shift,
> > &mtk_clk_gate_ops_setclr)
> > +
> > +#define GATE_VPP0_2(_id, _name, _parent,
> > _shift)                       \
> > +       GATE_MTK(_id, _name, _parent, &vpp0_2_cg_regs, _shift,
> > &mtk_clk_gate_ops_setclr)
> > +
> > +static const struct mtk_gate vpp0_clks[] = {
> > +       /* VPP0_0 */
> > +       GATE_VPP0_0(CLK_VPP0_MDP_FG, "vpp0_mdp_fg", "top_vpp", 1),
> > +       GATE_VPP0_0(CLK_VPP0_STITCH, "vpp0_stitch", "top_vpp", 2),
> > +       GATE_VPP0_0(CLK_VPP0_PADDING, "vpp0_padding", "top_vpp",
> > 7),
> > +       GATE_VPP0_0(CLK_VPP0_MDP_TCC, "vpp0_mdp_tcc", "top_vpp",
> > 8),
> > +       GATE_VPP0_0(CLK_VPP0_WARP0_ASYNC_TX, "vpp0_warp0_async_tx",
> > "top_vpp", 10),
> > +       GATE_VPP0_0(CLK_VPP0_WARP1_ASYNC_TX, "vpp0_warp1_async_tx",
> > "top_vpp", 11),
> > +       GATE_VPP0_0(CLK_VPP0_MUTEX, "vpp0_mutex", "top_vpp", 13),
> > +       GATE_VPP0_0(CLK_VPP02VPP1_RELAY, "vpp02vpp1_relay",
> > "top_vpp", 14),
> > +       GATE_VPP0_0(CLK_VPP0_VPP12VPP0_ASYNC,
> > "vpp0_vpp12vpp0_async", "top_vpp", 15),
> > +       GATE_VPP0_0(CLK_VPP0_MMSYSRAM_TOP, "vpp0_mmsysram_top",
> > "top_vpp", 16),
> > +       GATE_VPP0_0(CLK_VPP0_MDP_AAL, "vpp0_mdp_aal", "top_vpp",
> > 17),
> > +       GATE_VPP0_0(CLK_VPP0_MDP_RSZ, "vpp0_mdp_rsz", "top_vpp",
> > 18),
> > +       /* VPP0_1 */
> > +       GATE_VPP0_1(CLK_VPP0_SMI_COMMON_MMSRAM,
> > "vpp0_smi_common_mmsram", "top_vpp", 0),
> > +       GATE_VPP0_1(CLK_VPP0_GALS_VDO0_LARB0_MMSRAM,
> > "vpp0_gals_vdo0_larb0_mmsram", "top_vpp", 1),
> > +       GATE_VPP0_1(CLK_VPP0_GALS_VDO0_LARB1_MMSRAM,
> > "vpp0_gals_vdo0_larb1_mmsram", "top_vpp", 2),
> > +       GATE_VPP0_1(CLK_VPP0_GALS_VENCSYS_MMSRAM,
> > "vpp0_gals_vencsys_mmsram", "top_vpp", 3),
> > +       GATE_VPP0_1(CLK_VPP0_GALS_VENCSYS_CORE1_MMSRAM,
> > +                   "vpp0_gals_vencsys_core1_mmsram", "top_vpp",
> > 4),
> > +       GATE_VPP0_1(CLK_VPP0_GALS_INFRA_MMSRAM,
> > "vpp0_gals_infra_mmsram", "top_vpp", 5),
> > +       GATE_VPP0_1(CLK_VPP0_GALS_CAMSYS_MMSRAM,
> > "vpp0_gals_camsys_mmsram", "top_vpp", 6),
> > +       GATE_VPP0_1(CLK_VPP0_GALS_VPP1_LARB5_MMSRAM,
> > "vpp0_gals_vpp1_larb5_mmsram", "top_vpp", 7),
> > +       GATE_VPP0_1(CLK_VPP0_GALS_VPP1_LARB6_MMSRAM,
> > "vpp0_gals_vpp1_larb6_mmsram", "top_vpp", 8),
> > +       GATE_VPP0_1(CLK_VPP0_SMI_REORDER_MMSRAM,
> > "vpp0_smi_reorder_mmsram", "top_vpp", 9),
> > +       GATE_VPP0_1(CLK_VPP0_SMI_IOMMU, "vpp0_smi_iommu",
> > "top_vpp", 10),
> > +       GATE_VPP0_1(CLK_VPP0_GALS_IMGSYS_CAMSYS,
> > "vpp0_gals_imgsys_camsys", "top_vpp", 11),
> > +       GATE_VPP0_1(CLK_VPP0_MDP_RDMA, "vpp0_mdp_rdma", "top_vpp",
> > 12),
> > +       GATE_VPP0_1(CLK_VPP0_MDP_WROT, "vpp0_mdp_wrot", "top_vpp",
> > 13),
> > +       GATE_VPP0_1(CLK_VPP0_GALS_EMI0_EMI1, "vpp0_gals_emi0_emi1",
> > "top_vpp", 16),
> > +       GATE_VPP0_1(CLK_VPP0_SMI_SUB_COMMON_REORDER,
> > "vpp0_smi_sub_common_reorder", "top_vpp", 17),
> > +       GATE_VPP0_1(CLK_VPP0_SMI_RSI, "vpp0_smi_rsi", "top_vpp",
> > 18),
> > +       GATE_VPP0_1(CLK_VPP0_SMI_COMMON_LARB4,
> > "vpp0_smi_common_larb4", "top_vpp", 19),
> > +       GATE_VPP0_1(CLK_VPP0_GALS_VDEC_VDEC_CORE1,
> > "vpp0_gals_vdec_vdec_core1", "top_vpp", 20),
> > +       GATE_VPP0_1(CLK_VPP0_GALS_VPP1_WPESYS,
> > "vpp0_gals_vpp1_wpesys", "top_vpp", 21),
> > +       GATE_VPP0_1(CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1,
> > +                   "vpp0_gals_vdo0_vdo1_vencsys_core1", "top_vpp",
> > 22),
> > +       GATE_VPP0_1(CLK_VPP0_FAKE_ENG, "vpp0_fake_eng", "top_vpp",
> > 23),
> > +       GATE_VPP0_1(CLK_VPP0_MDP_HDR, "vpp0_mdp_hdr", "top_vpp",
> > 24),
> > +       GATE_VPP0_1(CLK_VPP0_MDP_TDSHP, "vpp0_mdp_tdshp",
> > "top_vpp", 25),
> > +       GATE_VPP0_1(CLK_VPP0_MDP_COLOR, "vpp0_mdp_color",
> > "top_vpp", 26),
> > +       GATE_VPP0_1(CLK_VPP0_MDP_OVL, "vpp0_mdp_ovl", "top_vpp",
> > 27),
> > +       GATE_VPP0_1(CLK_VPP0_DSIP_RDMA, "vpp0_dsip_rdma",
> > "top_vpp", 28),
> > +       GATE_VPP0_1(CLK_VPP0_DISP_WDMA, "vpp0_disp_wdma",
> > "top_vpp", 29),
> > +       GATE_VPP0_1(CLK_VPP0_MDP_HMS, "vpp0_mdp_hms", "top_vpp",
> > 30),
> > +       /* VPP0_2 */
> > +       GATE_VPP0_2(CLK_VPP0_WARP0_RELAY, "vpp0_warp0_relay",
> > "top_wpe_vpp", 0),
> > +       GATE_VPP0_2(CLK_VPP0_WARP0_ASYNC, "vpp0_warp0_async",
> > "top_wpe_vpp", 1),
> > +       GATE_VPP0_2(CLK_VPP0_WARP1_RELAY, "vpp0_warp1_relay",
> > "top_wpe_vpp", 2),
> > +       GATE_VPP0_2(CLK_VPP0_WARP1_ASYNC, "vpp0_warp1_async",
> > "top_wpe_vpp", 3),
> > +};
> > +
> > +static int clk_mt8188_vpp0_probe(struct platform_device *pdev)
> > +{
> > +       struct device *dev = &pdev->dev;
> > +       struct device_node *node = dev->parent->of_node;
> > +       struct clk_hw_onecell_data *clk_data;
> > +       int r;
> > +
> > +       clk_data = mtk_alloc_clk_data(CLK_VPP0_NR_CLK);
> > +       if (!clk_data)
> > +               return -ENOMEM;
> > +
> > +       r = mtk_clk_register_gates(node, vpp0_clks,
> > ARRAY_SIZE(vpp0_clks), clk_data);
> 
> This API has changed. Please rebase and update.

Thank you for your suggestions.
OK I will modify it in v6.
> 
> Otherwise,
> 
> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>

Re: [PATCH v5 12/19] clk: mediatek: Add MT8188 vdosys0 clock support

[Garmin Chang (張家銘)]

On Fri, 2023-02-03 at 15:19 +0800, Chen-Yu Tsai wrote:
> On Thu, Jan 19, 2023 at 8:54 PM Garmin.Chang <
> Garmin.Chang@mediatek.com> wrote:
> > 
> > Add MT8188 vdosys0 clock controller which provides clock gate
> > control in video system. This is integrated with mtk-mmsys
> > driver which will populate device by platform_device_register_data
> > to start vdosys clock driver.
> > 
> > Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
> > ---
> >  drivers/clk/mediatek/Makefile          |   3 +-
> >  drivers/clk/mediatek/clk-mt8188-vdo0.c | 134
> > +++++++++++++++++++++++++
> >  2 files changed, 136 insertions(+), 1 deletion(-)
> >  create mode 100644 drivers/clk/mediatek/clk-mt8188-vdo0.c
> > 
> > diff --git a/drivers/clk/mediatek/Makefile
> > b/drivers/clk/mediatek/Makefile
> > index 7d09e9fc6538..df78c0777fef 100644
> > --- a/drivers/clk/mediatek/Makefile
> > +++ b/drivers/clk/mediatek/Makefile
> > @@ -86,7 +86,8 @@ obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-
> > mcu.o clk-mt8186-topckgen.o clk-mt
> >  obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-
> > mt8188-topckgen.o \
> >                                    clk-mt8188-peri_ao.o clk-mt8188-
> > infra_ao.o \
> >                                    clk-mt8188-cam.o clk-mt8188-
> > ccu.o clk-mt8188-img.o \
> > -                                  clk-mt8188-ipe.o clk-mt8188-
> > mfg.o clk-mt8188-vdec.o
> > +                                  clk-mt8188-ipe.o clk-mt8188-
> > mfg.o clk-mt8188-vdec.o \
> > +                                  clk-mt8188-vdo0.o
> >  obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
> >  obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
> >  obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> > diff --git a/drivers/clk/mediatek/clk-mt8188-vdo0.c
> > b/drivers/clk/mediatek/clk-mt8188-vdo0.c
> > new file mode 100644
> > index 000000000000..30dd64374ace
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt8188-vdo0.c
> > @@ -0,0 +1,134 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +//
> > +// Copyright (c) 2022 MediaTek Inc.
> > +// Author: Garmin Chang <garmin.chang@mediatek.com>
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/platform_device.h>
> > +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> > +
> > +#include "clk-gate.h"
> > +#include "clk-mtk.h"
> > +
> > +static const struct mtk_gate_regs vdo0_0_cg_regs = {
> > +       .set_ofs = 0x104,
> > +       .clr_ofs = 0x108,
> > +       .sta_ofs = 0x100,
> > +};
> > +
> > +static const struct mtk_gate_regs vdo0_1_cg_regs = {
> > +       .set_ofs = 0x114,
> > +       .clr_ofs = 0x118,
> > +       .sta_ofs = 0x110,
> > +};
> > +
> > +static const struct mtk_gate_regs vdo0_2_cg_regs = {
> > +       .set_ofs = 0x124,
> > +       .clr_ofs = 0x128,
> > +       .sta_ofs = 0x120,
> > +};
> > +
> > +#define GATE_VDO0_0(_id, _name, _parent,
> > _shift)                       \
> > +       GATE_MTK(_id, _name, _parent, &vdo0_0_cg_regs, _shift,
> > &mtk_clk_gate_ops_setclr)
> > +
> > +#define GATE_VDO0_1(_id, _name, _parent,
> > _shift)                       \
> > +       GATE_MTK(_id, _name, _parent, &vdo0_1_cg_regs, _shift,
> > &mtk_clk_gate_ops_setclr)
> > +
> > +#define GATE_VDO0_2(_id, _name, _parent,
> > _shift)                       \
> > +       GATE_MTK(_id, _name, _parent, &vdo0_2_cg_regs, _shift,
> > &mtk_clk_gate_ops_setclr)
> > +
> > +#define GATE_VDO0_2_FLAGS(_id, _name, _parent, _shift,
> > _flags)         \
> > +       GATE_MTK_FLAGS(_id, _name, _parent, &vdo0_2_cg_regs,
> > _shift,    \
> > +       &mtk_clk_gate_ops_setclr, _flags)
> > +
> > +static const struct mtk_gate vdo0_clks[] = {
> > +       /* VDO0_0 */
> > +       GATE_VDO0_0(CLK_VDO0_DISP_OVL0, "vdo0_disp_ovl0",
> > "top_vpp", 0),
> > +       GATE_VDO0_0(CLK_VDO0_FAKE_ENG0, "vdo0_fake_eng0",
> > "top_vpp", 2),
> > +       GATE_VDO0_0(CLK_VDO0_DISP_CCORR0, "vdo0_disp_ccorr0",
> > "top_vpp", 4),
> > +       GATE_VDO0_0(CLK_VDO0_DISP_MUTEX0, "vdo0_disp_mutex0",
> > "top_vpp", 6),
> > +       GATE_VDO0_0(CLK_VDO0_DISP_GAMMA0, "vdo0_disp_gamma0",
> > "top_vpp", 8),
> > +       GATE_VDO0_0(CLK_VDO0_DISP_DITHER0, "vdo0_disp_dither0",
> > "top_vpp", 10),
> > +       GATE_VDO0_0(CLK_VDO0_DISP_WDMA0, "vdo0_disp_wdma0",
> > "top_vpp", 17),
> > +       GATE_VDO0_0(CLK_VDO0_DISP_RDMA0, "vdo0_disp_rdma0",
> > "top_vpp", 19),
> > +       GATE_VDO0_0(CLK_VDO0_DSI0, "vdo0_dsi0", "top_vpp", 21),
> > +       GATE_VDO0_0(CLK_VDO0_DSI1, "vdo0_dsi1", "top_vpp", 22),
> > +       GATE_VDO0_0(CLK_VDO0_DSC_WRAP0, "vdo0_dsc_wrap0",
> > "top_vpp", 23),
> > +       GATE_VDO0_0(CLK_VDO0_VPP_MERGE0, "vdo0_vpp_merge0",
> > "top_vpp", 24),
> > +       GATE_VDO0_0(CLK_VDO0_DP_INTF0, "vdo0_dp_intf0", "top_vpp",
> > 25),
> > +       GATE_VDO0_0(CLK_VDO0_DISP_AAL0, "vdo0_disp_aal0",
> > "top_vpp", 26),
> > +       GATE_VDO0_0(CLK_VDO0_INLINEROT0, "vdo0_inlinerot0",
> > "top_vpp", 27),
> > +       GATE_VDO0_0(CLK_VDO0_APB_BUS, "vdo0_apb_bus", "top_vpp",
> > 28),
> > +       GATE_VDO0_0(CLK_VDO0_DISP_COLOR0, "vdo0_disp_color0",
> > "top_vpp", 29),
> > +       GATE_VDO0_0(CLK_VDO0_MDP_WROT0, "vdo0_mdp_wrot0",
> > "top_vpp", 30),
> > +       GATE_VDO0_0(CLK_VDO0_DISP_RSZ0, "vdo0_disp_rsz0",
> > "top_vpp", 31),
> > +       /* VDO0_1 */
> > +       GATE_VDO0_1(CLK_VDO0_DISP_POSTMASK0, "vdo0_disp_postmask0",
> > "top_vpp", 0),
> > +       GATE_VDO0_1(CLK_VDO0_FAKE_ENG1, "vdo0_fake_eng1",
> > "top_vpp", 1),
> > +       GATE_VDO0_1(CLK_VDO0_DL_ASYNC2, "vdo0_dl_async2",
> > "top_vpp", 5),
> > +       GATE_VDO0_1(CLK_VDO0_DL_RELAY3, "vdo0_dl_relay3",
> > "top_vpp", 6),
> > +       GATE_VDO0_1(CLK_VDO0_DL_RELAY4, "vdo0_dl_relay4",
> > "top_vpp", 7),
> > +       GATE_VDO0_1(CLK_VDO0_SMI_GALS, "vdo0_smi_gals", "top_vpp",
> > 10),
> > +       GATE_VDO0_1(CLK_VDO0_SMI_COMMON, "vdo0_smi_common",
> > "top_vpp", 11),
> > +       GATE_VDO0_1(CLK_VDO0_SMI_EMI, "vdo0_smi_emi", "top_vpp",
> > 12),
> > +       GATE_VDO0_1(CLK_VDO0_SMI_IOMMU, "vdo0_smi_iommu",
> > "top_vpp", 13),
> > +       GATE_VDO0_1(CLK_VDO0_SMI_LARB, "vdo0_smi_larb", "top_vpp",
> > 14),
> > +       GATE_VDO0_1(CLK_VDO0_SMI_RSI, "vdo0_smi_rsi", "top_vpp",
> > 15),
> > +       /* VDO0_2 */
> > +       GATE_VDO0_2(CLK_VDO0_DSI0_DSI, "vdo0_dsi0_dsi",
> > "top_dsi_occ", 0),
> > +       GATE_VDO0_2(CLK_VDO0_DSI1_DSI, "vdo0_dsi1_dsi",
> > "top_dsi_occ", 8),
> > +       GATE_VDO0_2_FLAGS(CLK_VDO0_DP_INTF0_DP_INTF,
> > "vdo0_dp_intf0_dp_intf",
> > +               "top_edp", 16, CLK_SET_RATE_PARENT),
> > +};
> > +
> > +static int clk_mt8188_vdo0_probe(struct platform_device *pdev)
> > +{
> > +       struct device *dev = &pdev->dev;
> > +       struct device_node *node = dev->parent->of_node;
> > +       struct clk_hw_onecell_data *clk_data;
> > +       int r;
> > +
> > +       clk_data = mtk_alloc_clk_data(CLK_VDO0_NR_CLK);
> > +       if (!clk_data)
> > +               return -ENOMEM;
> > +
> > +       r = mtk_clk_register_gates(node, vdo0_clks,
> > ARRAY_SIZE(vdo0_clks), clk_data);
> 
> This API was changed. Please rebase onto the latest -next and update.

Thank you for your suggestions.
OK I will modify it in v6.
> 
> Angelo (CC-ed) also mentioned a new simple probe variant for non-DT
> clock drivers is being developed. He didn't mention a timeline
> though.


When the new simple probe variant is ready, I will rebase latest-next
and update it.

Re: [PATCH v5 11/19] clk: mediatek: Add MT8188 vdecsys clock support

[Garmin Chang (張家銘)]

On Fri, 2023-02-03 at 15:17 +0800, Chen-Yu Tsai wrote:
> On Thu, Jan 19, 2023 at 8:49 PM Garmin.Chang <
> Garmin.Chang@mediatek.com> wrote:
> > 
> > Add MT8188 vdec clock controllers which provide clock gate
> > control for video decoder.
> > 
> > Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
> > ---
> >  drivers/clk/mediatek/Makefile          |  2 +-
> >  drivers/clk/mediatek/clk-mt8188-vdec.c | 90
> > ++++++++++++++++++++++++++
> >  2 files changed, 91 insertions(+), 1 deletion(-)
> >  create mode 100644 drivers/clk/mediatek/clk-mt8188-vdec.c
> > 
> > diff --git a/drivers/clk/mediatek/Makefile
> > b/drivers/clk/mediatek/Makefile
> > index a0fd87a882b5..7d09e9fc6538 100644
> > --- a/drivers/clk/mediatek/Makefile
> > +++ b/drivers/clk/mediatek/Makefile
> > @@ -86,7 +86,7 @@ obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-
> > mcu.o clk-mt8186-topckgen.o clk-mt
> >  obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-
> > mt8188-topckgen.o \
> >                                    clk-mt8188-peri_ao.o clk-mt8188-
> > infra_ao.o \
> >                                    clk-mt8188-cam.o clk-mt8188-
> > ccu.o clk-mt8188-img.o \
> > -                                  clk-mt8188-ipe.o clk-mt8188-
> > mfg.o
> > +                                  clk-mt8188-ipe.o clk-mt8188-
> > mfg.o clk-mt8188-vdec.o
> >  obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
> >  obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
> >  obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> > diff --git a/drivers/clk/mediatek/clk-mt8188-vdec.c
> > b/drivers/clk/mediatek/clk-mt8188-vdec.c
> > new file mode 100644
> > index 000000000000..e05a27957136
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt8188-vdec.c
> > @@ -0,0 +1,90 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +//
> > +// Copyright (c) 2022 MediaTek Inc.
> > +// Author: Garmin Chang <garmin.chang@mediatek.com>
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/platform_device.h>
> > +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> > +
> > +#include "clk-gate.h"
> > +#include "clk-mtk.h"
> > +
> > +static const struct mtk_gate_regs vde0_cg_regs = {
> 
> Could you replace all instances of "vde" (both upper and lower case)
> with "vdec" to be consistent with usages elsewhere?

Thank you for your suggestions.
OK, I will modify this series in v6.
> 
> > +       .set_ofs = 0x0,
> > +       .clr_ofs = 0x4,
> > +       .sta_ofs = 0x0,
> > +};
> > +
> > +static const struct mtk_gate_regs vde1_cg_regs = {
> > +       .set_ofs = 0x200,
> > +       .clr_ofs = 0x204,
> > +       .sta_ofs = 0x200,
> > +};
> > +
> > +static const struct mtk_gate_regs vde2_cg_regs = {
> > +       .set_ofs = 0x8,
> > +       .clr_ofs = 0xc,
> > +       .sta_ofs = 0x8,
> > +};
> > +
> > +#define GATE_VDE0(_id, _name, _parent, _shift)                 \
> > +       GATE_MTK(_id, _name, _parent, &vde0_cg_regs, _shift,
> > &mtk_clk_gate_ops_setclr_inv)
> > +
> > +#define GATE_VDE1(_id, _name, _parent, _shift)                 \
> > +       GATE_MTK(_id, _name, _parent, &vde1_cg_regs, _shift,
> > &mtk_clk_gate_ops_setclr_inv)
> > +
> > +#define GATE_VDE2(_id, _name, _parent, _shift)                 \
> > +       GATE_MTK(_id, _name, _parent, &vde2_cg_regs, _shift,
> > &mtk_clk_gate_ops_setclr_inv)
> > +
> > +static const struct mtk_gate vde1_clks[] = {
> > +       /* VDE1_0 */
> > +       GATE_VDE0(CLK_VDE1_SOC_VDEC, "vde1_soc_vdec", "top_vdec",
> > 0),
> > +       GATE_VDE0(CLK_VDE1_SOC_VDEC_ACTIVE, "vde1_soc_vdec_active",
> > "top_vdec", 4),
> > +       GATE_VDE0(CLK_VDE1_SOC_VDEC_ENG, "vde1_soc_vdec_eng",
> > "top_vdec", 8),
> > +       /* VDE1_1 */
> > +       GATE_VDE1(CLK_VDE1_SOC_LAT, "vde1_soc_lat", "top_vdec", 0),
> > +       GATE_VDE1(CLK_VDE1_SOC_LAT_ACTIVE, "vde1_soc_lat_active",
> > "top_vdec", 4),
> > +       GATE_VDE1(CLK_VDE1_SOC_LAT_ENG, "vde1_soc_lat_eng",
> > "top_vdec", 8),
> > +       /* VDE12 */
> 
> Add an underscore like the above?
> 
> ChenYu
OK, I will add underscore in v6.
> 
> > +       GATE_VDE2(CLK_VDE1_SOC_LARB1, "vde1_soc_larb1", "top_vdec",
> > 0),
> > +};
> > +
> > +static const struct mtk_gate vde2_clks[] = {
> > +       /* VDE2_0 */
> > +       GATE_VDE0(CLK_VDE2_VDEC, "vde2_vdec", "top_vdec", 0),
> > +       GATE_VDE0(CLK_VDE2_VDEC_ACTIVE, "vde2_vdec_active",
> > "top_vdec", 4),
> > +       GATE_VDE0(CLK_VDE2_VDEC_ENG, "vde2_vdec_eng", "top_vdec",
> > 8),
> > +       /* VDE2_1 */
> > +       GATE_VDE1(CLK_VDE2_LAT, "vde2_lat", "top_vdec", 0),
> > +       /* VDE2_2 */
> > +       GATE_VDE2(CLK_VDE2_LARB1, "vde2_larb1", "top_vdec", 0),
> > +};
> > +
> > +static const struct mtk_clk_desc vde1_desc = {
> > +       .clks = vde1_clks,
> > +       .num_clks = ARRAY_SIZE(vde1_clks),
> > +};
> > +
> > +static const struct mtk_clk_desc vde2_desc = {
> > +       .clks = vde2_clks,
> > +       .num_clks = ARRAY_SIZE(vde2_clks),
> > +};
> > +
> > +static const struct of_device_id of_match_clk_mt8188_vde[] = {
> > +       { .compatible = "mediatek,mt8188-vdecsys-soc", .data =
> > &vde1_desc },
> > +       { .compatible = "mediatek,mt8188-vdecsys", .data =
> > &vde2_desc },
> > +       { /* sentinel */ }
> > +};
> > +
> > +static struct platform_driver clk_mt8188_vde_drv = {
> > +       .probe = mtk_clk_simple_probe,
> > +       .remove = mtk_clk_simple_remove,
> > +       .driver = {
> > +               .name = "clk-mt8188-vde",
> > +               .of_match_table = of_match_clk_mt8188_vde,
> > +       },
> > +};
> > +
> > +builtin_platform_driver(clk_mt8188_vde_drv);
> > +MODULE_LICENSE("GPL");
> > --
> > 2.18.0
> > 
> > 

Re: [PATCH v5 14/19] clk: mediatek: Add MT8188 vencsys clock support

[Garmin Chang (張家銘)]

On Fri, 2023-02-03 at 15:25 +0800, Chen-Yu Tsai wrote:
> On Thu, Jan 19, 2023 at 8:55 PM Garmin.Chang <
> Garmin.Chang@mediatek.com> wrote:
> > 
> > Add MT8188 vencsys clock controllers which provide clock gate
> > control for video encoder.
> > 
> > Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
> > ---
> >  drivers/clk/mediatek/Makefile          |  2 +-
> >  drivers/clk/mediatek/clk-mt8188-venc.c | 52
> > ++++++++++++++++++++++++++
> >  2 files changed, 53 insertions(+), 1 deletion(-)
> >  create mode 100644 drivers/clk/mediatek/clk-mt8188-venc.c
> > 
> > diff --git a/drivers/clk/mediatek/Makefile
> > b/drivers/clk/mediatek/Makefile
> > index c654f4288e09..22a3840160fc 100644
> > --- a/drivers/clk/mediatek/Makefile
> > +++ b/drivers/clk/mediatek/Makefile
> > @@ -87,7 +87,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-
> > apmixedsys.o clk-mt8188-topckgen.o
> >                                    clk-mt8188-peri_ao.o clk-mt8188-
> > infra_ao.o \
> >                                    clk-mt8188-cam.o clk-mt8188-
> > ccu.o clk-mt8188-img.o \
> >                                    clk-mt8188-ipe.o clk-mt8188-
> > mfg.o clk-mt8188-vdec.o \
> > -                                  clk-mt8188-vdo0.o clk-mt8188-
> > vdo1.o
> > +                                  clk-mt8188-vdo0.o clk-mt8188-
> > vdo1.o clk-mt8188-venc.o
> >  obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
> >  obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
> >  obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> > diff --git a/drivers/clk/mediatek/clk-mt8188-venc.c
> > b/drivers/clk/mediatek/clk-mt8188-venc.c
> > new file mode 100644
> > index 000000000000..375ef99e2349
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt8188-venc.c
> > @@ -0,0 +1,52 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +//
> > +// Copyright (c) 2022 MediaTek Inc.
> > +// Author: Garmin Chang <garmin.chang@mediatek.com>
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/platform_device.h>
> > +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> > +
> > +#include "clk-gate.h"
> > +#include "clk-mtk.h"
> > +
> > +static const struct mtk_gate_regs ven1_cg_regs = {
> 
> Like the vdecsys patch, please change "ven" to "venc" to be
> consistent
> with usages elsewhere.


Thank you for your suggestions.
OK, I will modify this series in v6.
> 
> > +       .set_ofs = 0x4,
> > +       .clr_ofs = 0x8,
> > +       .sta_ofs = 0x0,
> > +};
> > +
> > +#define GATE_VEN1(_id, _name, _parent, _shift)                 \
> > +       GATE_MTK(_id, _name, _parent, &ven1_cg_regs, _shift,
> > &mtk_clk_gate_ops_setclr_inv)
> > +
> > +static const struct mtk_gate ven1_clks[] = {
> > +       GATE_VEN1(CLK_VEN1_CKE0_LARB, "ven1_cke0_larb", "top_venc",
> > 0),
> > +       GATE_VEN1(CLK_VEN1_CKE1_VENC, "ven1_cke1_venc", "top_venc",
> > 4),
> > +       GATE_VEN1(CLK_VEN1_CKE2_JPGENC, "ven1_cke2_jpgenc",
> > "top_venc", 8),
> > +       GATE_VEN1(CLK_VEN1_CKE3_JPGDEC, "ven1_cke3_jpgdec",
> > "top_venc", 12),
> > +       GATE_VEN1(CLK_VEN1_CKE4_JPGDEC_C1, "ven1_cke4_jpgdec_c1",
> > "top_venc", 16),
> > +       GATE_VEN1(CLK_VEN1_CKE5_GALS, "ven1_cke5_gals", "top_venc",
> > 28),
> > +       GATE_VEN1(CLK_VEN1_CKE6_GALS_SRAM, "ven1_cke6_gals_sram",
> > "top_venc", 31),
> 
> Is ckeN in both the macro name and clock name necessary? We don't
> really
> care about the index.
> 
> ChenYu

OK, I will modify it in v6.
> 
> > +};
> > +
> > +static const struct mtk_clk_desc ven1_desc = {
> > +       .clks = ven1_clks,
> > +       .num_clks = ARRAY_SIZE(ven1_clks),
> > +};
> > +
> > +static const struct of_device_id of_match_clk_mt8188_ven1[] = {
> > +       { .compatible = "mediatek,mt8188-vencsys", .data =
> > &ven1_desc },
> > +       { /* sentinel */ }
> > +};
> > +
> > +static struct platform_driver clk_mt8188_ven1_drv = {
> > +       .probe = mtk_clk_simple_probe,
> > +       .remove = mtk_clk_simple_remove,
> > +       .driver = {
> > +               .name = "clk-mt8188-ven1",
> > +               .of_match_table = of_match_clk_mt8188_ven1,
> > +       },
> > +};
> > +
> > +builtin_platform_driver(clk_mt8188_ven1_drv);
> > +MODULE_LICENSE("GPL");
> > --
> > 2.18.0
> > 
> > 

Re: [PATCH v5 10/19] clk: mediatek: Add MT8188 mfgcfg clock support

[Garmin Chang (張家銘)]

On Fri, 2023-02-03 at 15:02 +0800, Chen-Yu Tsai wrote:
> On Thu, Jan 19, 2023 at 8:50 PM Garmin.Chang <
> Garmin.Chang@mediatek.com> wrote:
> > 
> > Add MT8188 mfg clock controller which provides clock gate
> > control for GPU.
> > 
> > Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
> > ---
> >  drivers/clk/mediatek/Makefile         |  2 +-
> >  drivers/clk/mediatek/clk-mt8188-mfg.c | 47
> > +++++++++++++++++++++++++++
> >  2 files changed, 48 insertions(+), 1 deletion(-)
> >  create mode 100644 drivers/clk/mediatek/clk-mt8188-mfg.c
> > 
> > diff --git a/drivers/clk/mediatek/Makefile
> > b/drivers/clk/mediatek/Makefile
> > index 4a599122f761..a0fd87a882b5 100644
> > --- a/drivers/clk/mediatek/Makefile
> > +++ b/drivers/clk/mediatek/Makefile
> > @@ -86,7 +86,7 @@ obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-
> > mcu.o clk-mt8186-topckgen.o clk-mt
> >  obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-
> > mt8188-topckgen.o \
> >                                    clk-mt8188-peri_ao.o clk-mt8188-
> > infra_ao.o \
> >                                    clk-mt8188-cam.o clk-mt8188-
> > ccu.o clk-mt8188-img.o \
> > -                                  clk-mt8188-ipe.o
> > +                                  clk-mt8188-ipe.o clk-mt8188-
> > mfg.o
> >  obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
> >  obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
> >  obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> > diff --git a/drivers/clk/mediatek/clk-mt8188-mfg.c
> > b/drivers/clk/mediatek/clk-mt8188-mfg.c
> > new file mode 100644
> > index 000000000000..57b0afb5f4df
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt8188-mfg.c
> > @@ -0,0 +1,47 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +//
> > +// Copyright (c) 2022 MediaTek Inc.
> > +// Author: Garmin Chang <garmin.chang@mediatek.com>
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/platform_device.h>
> > +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> > +
> > +#include "clk-gate.h"
> > +#include "clk-mtk.h"
> > +
> > +static const struct mtk_gate_regs mfgcfg_cg_regs = {
> > +       .set_ofs = 0x4,
> > +       .clr_ofs = 0x8,
> > +       .sta_ofs = 0x0,
> > +};
> > +
> > +#define GATE_MFG(_id, _name, _parent,
> > _shift)                          \
> > +       GATE_MTK_FLAGS(_id, _name, _parent, &mfgcfg_cg_regs,
> > _shift,    \
> > +                      &mtk_clk_gate_ops_setclr,
> > CLK_SET_RATE_PARENT)
> > +
> > +static const struct mtk_gate mfgcfg_clks[] = {
> > +       GATE_MFG(CLK_MFGCFG_BG3D, "mfgcfg_bg3d",
> > "top_mfg_core_tmp", 0),
> 
> Are you sure the parent isn't "mfg_ck_fast_ref"?

Thank you for your suggestions. 
OK, I will chnage to mfg_ck_fast_ref in v6.

> 
> ChenYu

Re: [PATCH v5 02/19] clk: mediatek: Add MT8188 apmixedsys clock support

[Garmin Chang (張家銘)]

On Fri, 2023-02-03 at 15:44 +0800, Chen-Yu Tsai wrote:
> On Thu, Jan 19, 2023 at 8:54 PM Garmin.Chang <
> Garmin.Chang@mediatek.com> wrote:
> > 
> > Add MT8188 apmixedsys clock controller which provides Plls
> > generated from SoC 26m and ssusb clock gate control.
> > 
> > Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
> > ---
> >  drivers/clk/mediatek/Kconfig                 |  11 ++
> >  drivers/clk/mediatek/Makefile                |   1 +
> >  drivers/clk/mediatek/clk-mt8188-apmixedsys.c | 154
> > +++++++++++++++++++
> >  3 files changed, 166 insertions(+)
> >  create mode 100644 drivers/clk/mediatek/clk-mt8188-apmixedsys.c
> > 
> > diff --git a/drivers/clk/mediatek/Kconfig
> > b/drivers/clk/mediatek/Kconfig
> > index 22e8e79475ee..f02b679f71d0 100644
> > --- a/drivers/clk/mediatek/Kconfig
> > +++ b/drivers/clk/mediatek/Kconfig
> > @@ -565,6 +565,17 @@ config COMMON_CLK_MT8186
> >         help
> >           This driver supports MediaTek MT8186 clocks.
> > 
> > +config COMMON_CLK_MT8188
> > +       bool "Clock driver for MediaTek MT8188"
> > +       depends on ARM64 || COMPILE_TEST
> > +       select COMMON_CLK_MEDIATEK
> > +       default ARCH_MEDIATEK
> > +       help
> > +         This driver supports MediaTek MT8188 basic clocks and
> > clocks
> > +         required for various peripheral found on MediaTek. Choose
> > +         M or Y here if you want to use clocks such as peri_ao,
> > +         infra_ao, etc.
> > +
> >  config COMMON_CLK_MT8192
> >         bool "Clock driver for MediaTek MT8192"
> >         depends on ARM64 || COMPILE_TEST
> > diff --git a/drivers/clk/mediatek/Makefile
> > b/drivers/clk/mediatek/Makefile
> > index e24080fd6e7f..13ab8deb362c 100644
> > --- a/drivers/clk/mediatek/Makefile
> > +++ b/drivers/clk/mediatek/Makefile
> > @@ -83,6 +83,7 @@ obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-
> > mcu.o clk-mt8186-topckgen.o clk-mt
> >                                    clk-mt8186-mfg.o clk-mt8186-mm.o 
> > clk-mt8186-wpe.o \
> >                                    clk-mt8186-img.o clk-mt8186-
> > vdec.o clk-mt8186-venc.o \
> >                                    clk-mt8186-cam.o clk-mt8186-
> > mdp.o clk-mt8186-ipe.o
> > +obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o
> >  obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
> >  obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
> >  obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> > diff --git a/drivers/clk/mediatek/clk-mt8188-apmixedsys.c
> > b/drivers/clk/mediatek/clk-mt8188-apmixedsys.c
> > new file mode 100644
> > index 000000000000..8d73ae3a0da8
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt8188-apmixedsys.c
> > @@ -0,0 +1,154 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +//
> > +// Copyright (c) 2022 MediaTek Inc.
> > +// Author: Garmin Chang <garmin.chang@mediatek.com>
> > +
> > +#include <linux/of_device.h>
> > +#include <linux/platform_device.h>
> > +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> > +
> > +#include "clk-gate.h"
> > +#include "clk-mtk.h"
> > +#include "clk-pll.h"
> > +
> > +static const struct mtk_gate_regs apmixed_cg_regs = {
> > +       .set_ofs = 0x8,
> > +       .clr_ofs = 0x8,
> > +       .sta_ofs = 0x8,
> > +};
> > +
> > +#define GATE_APMIXED(_id, _name, _parent,
> > _shift)                      \
> > +       GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift,
> > &mtk_clk_gate_ops_no_setclr_inv)
> > +
> > +static const struct mtk_gate apmixed_clks[] = {
> > +       GATE_APMIXED(CLK_APMIXED_PLL_SSUSB26M_EN,
> > "pll_ssusb26m_en", "clk26m", 1),
> > +};
> > +
> > +#define MT8188_PLL_FMAX                (3800UL * MHZ)
> > +#define MT8188_PLL_FMIN                (1500UL * MHZ)
> > +#define MT8188_INTEGER_BITS    8
> > +
> > +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask,
> > _flags,              \
> > +           _rst_bar_mask, _pcwbits, _pd_reg,
> > _pd_shift,                \
> > +           _tuner_reg, _tuner_en_reg,
> > _tuner_en_bit,                   \
> > +           _pcw_reg, _pcw_shift,
> > _pcw_chg_reg,                         \
> > +           _en_reg, _pll_en_bit)
> > {                                     \
> > +               .id =
> > _id,                                              \
> > +               .name =
> > _name,                                          \
> > +               .reg =
> > _reg,                                            \
> > +               .pwr_reg =
> > _pwr_reg,                                    \
> > +               .en_mask =
> > _en_mask,                                    \
> > +               .flags =
> > _flags,                                        \
> > +               .rst_bar_mask =
> > _rst_bar_mask,                          \
> > +               .fmax =
> > MT8188_PLL_FMAX,                                \
> > +               .fmin =
> > MT8188_PLL_FMIN,                                \
> > +               .pcwbits =
> > _pcwbits,                                    \
> > +               .pcwibits =
> > MT8188_INTEGER_BITS,                        \
> > +               .pd_reg =
> > _pd_reg,                                      \
> > +               .pd_shift =
> > _pd_shift,                                  \
> > +               .tuner_reg =
> > _tuner_reg,                                \
> > +               .tuner_en_reg =
> > _tuner_en_reg,                          \
> > +               .tuner_en_bit =
> > _tuner_en_bit,                          \
> > +               .pcw_reg =
> > _pcw_reg,                                    \
> > +               .pcw_shift =
> > _pcw_shift,                                \
> > +               .pcw_chg_reg =
> > _pcw_chg_reg,                            \
> > +               .en_reg =
> > _en_reg,                                      \
> > +               .pll_en_bit =
> > _pll_en_bit,                              \
> > +       }
> > +
> > +static const struct mtk_pll_data plls[] = {
> > +       PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x044C, 0x0458, 0,
> > +           0, 0, 22, 0x0450, 24, 0, 0, 0, 0x0450, 0, 0, 0, 9),
> > +       PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0514, 0x0520, 0,
> > +           0, 0, 22, 0x0518, 24, 0, 0, 0, 0x0518, 0, 0, 0, 9),
> > +       PLL(CLK_APMIXED_TVDPLL1, "tvdpll1", 0x0524, 0x0530, 0,
> > +           0, 0, 22, 0x0528, 24, 0, 0, 0, 0x0528, 0, 0, 0, 9),
> > +       PLL(CLK_APMIXED_TVDPLL2, "tvdpll2", 0x0534, 0x0540, 0,
> > +           0, 0, 22, 0x0538, 24, 0, 0, 0, 0x0538, 0, 0, 0, 9),
> > +       PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0544, 0x0550, 0xff000000,
> > +           HAVE_RST_BAR, BIT(23), 22, 0x0548, 24, 0, 0, 0, 0x0548,
> > 0, 0, 0, 9),
> > +       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x045C, 0x0468,
> > 0xff000000,
> > +           HAVE_RST_BAR, BIT(23), 22, 0x0460, 24, 0, 0, 0, 0x0460,
> > 0, 0, 0, 9),
> > +       PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0554, 0x0560, 0,
> > +           0, 0, 22, 0x0558, 24, 0, 0, 0, 0x0558, 0, 0, 0, 9),
> > +       PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0504, 0x0510,
> > 0xff000000,
> > +           HAVE_RST_BAR, BIT(23), 22, 0x0508, 24, 0, 0, 0, 0x0508,
> > 0, 0, 0, 9),
> > +       PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x042C, 0x0438, 0,
> > +           0, 0, 22, 0x0430, 24, 0, 0, 0, 0x0430, 0, 0, 0, 9),
> > +       PLL(CLK_APMIXED_APLL1, "apll1", 0x0304, 0x0314, 0,
> > +           0, 0, 32, 0x0308, 24, 0x0034, 0x0000, 12, 0x030C, 0, 0,
> > 0, 9),
> > +       PLL(CLK_APMIXED_APLL2, "apll2", 0x0318, 0x0328, 0,
> > +           0, 0, 32, 0x031C, 24, 0x0038, 0x0000, 13, 0x0320, 0, 0,
> > 0, 9),
> > +       PLL(CLK_APMIXED_APLL3, "apll3", 0x032C, 0x033C, 0,
> > +           0, 0, 32, 0x0330, 24, 0x003C, 0x0000, 14, 0x0334, 0, 0,
> > 0, 9),
> > +       PLL(CLK_APMIXED_APLL4, "apll4", 0x0404, 0x0414, 0,
> > +           0, 0, 32, 0x0408, 24, 0x0040, 0x0000, 15, 0x040C, 0, 0,
> > 0, 9),
> > +       PLL(CLK_APMIXED_APLL5, "apll5", 0x0418, 0x0428, 0,
> > +           0, 0, 32, 0x041C, 24, 0x0044, 0x0000, 16, 0x0420, 0, 0,
> > 0, 9),
> > +       PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0340, 0x034C, 0,
> > +           0, 0, 22, 0x0344, 24, 0, 0, 0, 0x0344, 0, 0, 0, 9),
> > +};
> > +
> > +static const struct of_device_id of_match_clk_mt8188_apmixed[] = {
> > +       { .compatible = "mediatek,mt8188-apmixedsys", },
> > +       {}
> > +};
> > +
> > +static int clk_mt8188_apmixed_probe(struct platform_device *pdev)
> > +{
> > +       struct clk_hw_onecell_data *clk_data;
> > +       struct device_node *node = pdev->dev.of_node;
> > +       int r;
> > +
> > +       clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
> > +       if (!clk_data)
> > +               return -ENOMEM;
> > +
> > +       r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
> > clk_data);
> > +       if (r)
> > +               goto free_apmixed_data;
> > +
> > +       r = mtk_clk_register_gates_with_dev(node, apmixed_clks,
> > +               ARRAY_SIZE(apmixed_clks), clk_data, NULL);
> 
> This API is gone. Please replace it with mtk_clk_register_clks. And
> please
> pass in the |struct device| pointer.
> 
> ChenYu

Thank you for your suggestions.
OK, I will use mtk_clk_register_gates in v6.

Re: [PATCH v5 12/19] clk: mediatek: Add MT8188 vdosys0 clock support

[Garmin Chang (張家銘)]

On Fri, 2023-02-03 at 11:49 +0100, AngeloGioacchino Del Regno wrote:
> Il 03/02/23 08:19, Chen-Yu Tsai ha scritto:
> > On Thu, Jan 19, 2023 at 8:54 PM Garmin.Chang <
> > Garmin.Chang@mediatek.com> wrote:
> > > 
> > > Add MT8188 vdosys0 clock controller which provides clock gate
> > > control in video system. This is integrated with mtk-mmsys
> > > driver which will populate device by
> > > platform_device_register_data
> > > to start vdosys clock driver.
> > > 
> > > Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
> > > ---
> > >   drivers/clk/mediatek/Makefile          |   3 +-
> > >   drivers/clk/mediatek/clk-mt8188-vdo0.c | 134
> > > +++++++++++++++++++++++++
> > >   2 files changed, 136 insertions(+), 1 deletion(-)
> > >   create mode 100644 drivers/clk/mediatek/clk-mt8188-vdo0.c
> > > 
> > > diff --git a/drivers/clk/mediatek/Makefile
> > > b/drivers/clk/mediatek/Makefile
> > > index 7d09e9fc6538..df78c0777fef 100644
> > > --- a/drivers/clk/mediatek/Makefile
> > > +++ b/drivers/clk/mediatek/Makefile
> > > @@ -86,7 +86,8 @@ obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-
> > > mcu.o clk-mt8186-topckgen.o clk-mt
> > >   obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-
> > > mt8188-topckgen.o \
> > >                                     clk-mt8188-peri_ao.o clk-
> > > mt8188-infra_ao.o \
> > >                                     clk-mt8188-cam.o clk-mt8188-
> > > ccu.o clk-mt8188-img.o \
> > > -                                  clk-mt8188-ipe.o clk-mt8188-
> > > mfg.o clk-mt8188-vdec.o
> > > +                                  clk-mt8188-ipe.o clk-mt8188-
> > > mfg.o clk-mt8188-vdec.o \
> > > +                                  clk-mt8188-vdo0.o
> > >   obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
> > >   obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
> > >   obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> > > diff --git a/drivers/clk/mediatek/clk-mt8188-vdo0.c
> > > b/drivers/clk/mediatek/clk-mt8188-vdo0.c
> > > new file mode 100644
> > > index 000000000000..30dd64374ace
> > > --- /dev/null
> > > +++ b/drivers/clk/mediatek/clk-mt8188-vdo0.c
> > > @@ -0,0 +1,134 @@
> > > +// SPDX-License-Identifier: GPL-2.0-only
> > > +//
> > > +// Copyright (c) 2022 MediaTek Inc.
> > > +// Author: Garmin Chang <garmin.chang@mediatek.com>
> > > +
> > > +#include <linux/clk-provider.h>
> > > +#include <linux/platform_device.h>
> > > +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> > > +
> > > +#include "clk-gate.h"
> > > +#include "clk-mtk.h"
> > > +
> > > +static const struct mtk_gate_regs vdo0_0_cg_regs = {
> > > +       .set_ofs = 0x104,
> > > +       .clr_ofs = 0x108,
> > > +       .sta_ofs = 0x100,
> > > +};
> > > +
> > > +static const struct mtk_gate_regs vdo0_1_cg_regs = {
> > > +       .set_ofs = 0x114,
> > > +       .clr_ofs = 0x118,
> > > +       .sta_ofs = 0x110,
> > > +};
> > > +
> > > +static const struct mtk_gate_regs vdo0_2_cg_regs = {
> > > +       .set_ofs = 0x124,
> > > +       .clr_ofs = 0x128,
> > > +       .sta_ofs = 0x120,
> > > +};
> > > +
> > > +#define GATE_VDO0_0(_id, _name, _parent,
> > > _shift)                       \
> > > +       GATE_MTK(_id, _name, _parent, &vdo0_0_cg_regs, _shift,
> > > &mtk_clk_gate_ops_setclr)
> > > +
> > > +#define GATE_VDO0_1(_id, _name, _parent,
> > > _shift)                       \
> > > +       GATE_MTK(_id, _name, _parent, &vdo0_1_cg_regs, _shift,
> > > &mtk_clk_gate_ops_setclr)
> > > +
> > > +#define GATE_VDO0_2(_id, _name, _parent,
> > > _shift)                       \
> > > +       GATE_MTK(_id, _name, _parent, &vdo0_2_cg_regs, _shift,
> > > &mtk_clk_gate_ops_setclr)
> > > +
> > > +#define GATE_VDO0_2_FLAGS(_id, _name, _parent, _shift,
> > > _flags)         \
> > > +       GATE_MTK_FLAGS(_id, _name, _parent, &vdo0_2_cg_regs,
> > > _shift,    \
> > > +       &mtk_clk_gate_ops_setclr, _flags)
> > > +
> > > +static const struct mtk_gate vdo0_clks[] = {
> > > +       /* VDO0_0 */
> > > +       GATE_VDO0_0(CLK_VDO0_DISP_OVL0, "vdo0_disp_ovl0",
> > > "top_vpp", 0),
> > > +       GATE_VDO0_0(CLK_VDO0_FAKE_ENG0, "vdo0_fake_eng0",
> > > "top_vpp", 2),
> > > +       GATE_VDO0_0(CLK_VDO0_DISP_CCORR0, "vdo0_disp_ccorr0",
> > > "top_vpp", 4),
> > > +       GATE_VDO0_0(CLK_VDO0_DISP_MUTEX0, "vdo0_disp_mutex0",
> > > "top_vpp", 6),
> > > +       GATE_VDO0_0(CLK_VDO0_DISP_GAMMA0, "vdo0_disp_gamma0",
> > > "top_vpp", 8),
> > > +       GATE_VDO0_0(CLK_VDO0_DISP_DITHER0, "vdo0_disp_dither0",
> > > "top_vpp", 10),
> > > +       GATE_VDO0_0(CLK_VDO0_DISP_WDMA0, "vdo0_disp_wdma0",
> > > "top_vpp", 17),
> > > +       GATE_VDO0_0(CLK_VDO0_DISP_RDMA0, "vdo0_disp_rdma0",
> > > "top_vpp", 19),
> > > +       GATE_VDO0_0(CLK_VDO0_DSI0, "vdo0_dsi0", "top_vpp", 21),
> > > +       GATE_VDO0_0(CLK_VDO0_DSI1, "vdo0_dsi1", "top_vpp", 22),
> > > +       GATE_VDO0_0(CLK_VDO0_DSC_WRAP0, "vdo0_dsc_wrap0",
> > > "top_vpp", 23),
> > > +       GATE_VDO0_0(CLK_VDO0_VPP_MERGE0, "vdo0_vpp_merge0",
> > > "top_vpp", 24),
> > > +       GATE_VDO0_0(CLK_VDO0_DP_INTF0, "vdo0_dp_intf0",
> > > "top_vpp", 25),
> > > +       GATE_VDO0_0(CLK_VDO0_DISP_AAL0, "vdo0_disp_aal0",
> > > "top_vpp", 26),
> > > +       GATE_VDO0_0(CLK_VDO0_INLINEROT0, "vdo0_inlinerot0",
> > > "top_vpp", 27),
> > > +       GATE_VDO0_0(CLK_VDO0_APB_BUS, "vdo0_apb_bus", "top_vpp",
> > > 28),
> > > +       GATE_VDO0_0(CLK_VDO0_DISP_COLOR0, "vdo0_disp_color0",
> > > "top_vpp", 29),
> > > +       GATE_VDO0_0(CLK_VDO0_MDP_WROT0, "vdo0_mdp_wrot0",
> > > "top_vpp", 30),
> > > +       GATE_VDO0_0(CLK_VDO0_DISP_RSZ0, "vdo0_disp_rsz0",
> > > "top_vpp", 31),
> > > +       /* VDO0_1 */
> > > +       GATE_VDO0_1(CLK_VDO0_DISP_POSTMASK0,
> > > "vdo0_disp_postmask0", "top_vpp", 0),
> > > +       GATE_VDO0_1(CLK_VDO0_FAKE_ENG1, "vdo0_fake_eng1",
> > > "top_vpp", 1),
> > > +       GATE_VDO0_1(CLK_VDO0_DL_ASYNC2, "vdo0_dl_async2",
> > > "top_vpp", 5),
> > > +       GATE_VDO0_1(CLK_VDO0_DL_RELAY3, "vdo0_dl_relay3",
> > > "top_vpp", 6),
> > > +       GATE_VDO0_1(CLK_VDO0_DL_RELAY4, "vdo0_dl_relay4",
> > > "top_vpp", 7),
> > > +       GATE_VDO0_1(CLK_VDO0_SMI_GALS, "vdo0_smi_gals",
> > > "top_vpp", 10),
> > > +       GATE_VDO0_1(CLK_VDO0_SMI_COMMON, "vdo0_smi_common",
> > > "top_vpp", 11),
> > > +       GATE_VDO0_1(CLK_VDO0_SMI_EMI, "vdo0_smi_emi", "top_vpp",
> > > 12),
> > > +       GATE_VDO0_1(CLK_VDO0_SMI_IOMMU, "vdo0_smi_iommu",
> > > "top_vpp", 13),
> > > +       GATE_VDO0_1(CLK_VDO0_SMI_LARB, "vdo0_smi_larb",
> > > "top_vpp", 14),
> > > +       GATE_VDO0_1(CLK_VDO0_SMI_RSI, "vdo0_smi_rsi", "top_vpp",
> > > 15),
> > > +       /* VDO0_2 */
> > > +       GATE_VDO0_2(CLK_VDO0_DSI0_DSI, "vdo0_dsi0_dsi",
> > > "top_dsi_occ", 0),
> > > +       GATE_VDO0_2(CLK_VDO0_DSI1_DSI, "vdo0_dsi1_dsi",
> > > "top_dsi_occ", 8),
> > > +       GATE_VDO0_2_FLAGS(CLK_VDO0_DP_INTF0_DP_INTF,
> > > "vdo0_dp_intf0_dp_intf",
> > > +               "top_edp", 16, CLK_SET_RATE_PARENT),
> > > +};
> > > +
> > > +static int clk_mt8188_vdo0_probe(struct platform_device *pdev)
> > > +{
> > > +       struct device *dev = &pdev->dev;
> > > +       struct device_node *node = dev->parent->of_node;
> > > +       struct clk_hw_onecell_data *clk_data;
> > > +       int r;
> > > +
> > > +       clk_data = mtk_alloc_clk_data(CLK_VDO0_NR_CLK);
> > > +       if (!clk_data)
> > > +               return -ENOMEM;
> > > +
> > > +       r = mtk_clk_register_gates(node, vdo0_clks,
> > > ARRAY_SIZE(vdo0_clks), clk_data);
> > 
> > This API was changed. Please rebase onto the latest -next and
> > update.
> > 
> > Angelo (CC-ed) also mentioned a new simple probe variant for non-DT
> > clock drivers is being developed. He didn't mention a timeline
> > though.
> 
> I've already tested the new simple probe variant for non-DT clock
> drivers and
> it works fine on MT8173, MT8192 and MT8195.
> 
> Timeline - I should be able to push the part 2 series next week,
> which will include
> more conversion to simple probe and almost all clock drivers changed
> to allow
> building as modules.
> 
> Cheers,
> Angelo
> 
Thank you for your suggestions.
When the new simple probe variant and building as modules are ready, I
will rebase latest-next and update it.

Re: [PATCH v5 12/19] clk: mediatek: Add MT8188 vdosys0 clock support

[AngeloGioacchino Del Regno]

Il 09/03/23 06:49, Garmin Chang (張家銘) ha scritto:
> On Fri, 2023-02-03 at 11:49 +0100, AngeloGioacchino Del Regno wrote:
>> Il 03/02/23 08:19, Chen-Yu Tsai ha scritto:
>>> On Thu, Jan 19, 2023 at 8:54 PM Garmin.Chang <
>>> Garmin.Chang@mediatek.com> wrote:
>>>>
>>>> Add MT8188 vdosys0 clock controller which provides clock gate
>>>> control in video system. This is integrated with mtk-mmsys
>>>> driver which will populate device by
>>>> platform_device_register_data
>>>> to start vdosys clock driver.
>>>>
>>>> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
>>>> ---
>>>>    drivers/clk/mediatek/Makefile          |   3 +-
>>>>    drivers/clk/mediatek/clk-mt8188-vdo0.c | 134
>>>> +++++++++++++++++++++++++
>>>>    2 files changed, 136 insertions(+), 1 deletion(-)
>>>>    create mode 100644 drivers/clk/mediatek/clk-mt8188-vdo0.c
>>>>
>>>> diff --git a/drivers/clk/mediatek/Makefile
>>>> b/drivers/clk/mediatek/Makefile
>>>> index 7d09e9fc6538..df78c0777fef 100644
>>>> --- a/drivers/clk/mediatek/Makefile
>>>> +++ b/drivers/clk/mediatek/Makefile
>>>> @@ -86,7 +86,8 @@ obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-
>>>> mcu.o clk-mt8186-topckgen.o clk-mt
>>>>    obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-
>>>> mt8188-topckgen.o \
>>>>                                      clk-mt8188-peri_ao.o clk-
>>>> mt8188-infra_ao.o \
>>>>                                      clk-mt8188-cam.o clk-mt8188-
>>>> ccu.o clk-mt8188-img.o \
>>>> -                                  clk-mt8188-ipe.o clk-mt8188-
>>>> mfg.o clk-mt8188-vdec.o
>>>> +                                  clk-mt8188-ipe.o clk-mt8188-
>>>> mfg.o clk-mt8188-vdec.o \
>>>> +                                  clk-mt8188-vdo0.o
>>>>    obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
>>>>    obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
>>>>    obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
>>>> diff --git a/drivers/clk/mediatek/clk-mt8188-vdo0.c
>>>> b/drivers/clk/mediatek/clk-mt8188-vdo0.c
>>>> new file mode 100644
>>>> index 000000000000..30dd64374ace
>>>> --- /dev/null
>>>> +++ b/drivers/clk/mediatek/clk-mt8188-vdo0.c
>>>> @@ -0,0 +1,134 @@
>>>> +// SPDX-License-Identifier: GPL-2.0-only
>>>> +//
>>>> +// Copyright (c) 2022 MediaTek Inc.
>>>> +// Author: Garmin Chang <garmin.chang@mediatek.com>
>>>> +
>>>> +#include <linux/clk-provider.h>
>>>> +#include <linux/platform_device.h>
>>>> +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
>>>> +
>>>> +#include "clk-gate.h"
>>>> +#include "clk-mtk.h"
>>>> +
>>>> +static const struct mtk_gate_regs vdo0_0_cg_regs = {
>>>> +       .set_ofs = 0x104,
>>>> +       .clr_ofs = 0x108,
>>>> +       .sta_ofs = 0x100,
>>>> +};
>>>> +
>>>> +static const struct mtk_gate_regs vdo0_1_cg_regs = {
>>>> +       .set_ofs = 0x114,
>>>> +       .clr_ofs = 0x118,
>>>> +       .sta_ofs = 0x110,
>>>> +};
>>>> +
>>>> +static const struct mtk_gate_regs vdo0_2_cg_regs = {
>>>> +       .set_ofs = 0x124,
>>>> +       .clr_ofs = 0x128,
>>>> +       .sta_ofs = 0x120,
>>>> +};
>>>> +
>>>> +#define GATE_VDO0_0(_id, _name, _parent,
>>>> _shift)                       \
>>>> +       GATE_MTK(_id, _name, _parent, &vdo0_0_cg_regs, _shift,
>>>> &mtk_clk_gate_ops_setclr)
>>>> +
>>>> +#define GATE_VDO0_1(_id, _name, _parent,
>>>> _shift)                       \
>>>> +       GATE_MTK(_id, _name, _parent, &vdo0_1_cg_regs, _shift,
>>>> &mtk_clk_gate_ops_setclr)
>>>> +
>>>> +#define GATE_VDO0_2(_id, _name, _parent,
>>>> _shift)                       \
>>>> +       GATE_MTK(_id, _name, _parent, &vdo0_2_cg_regs, _shift,
>>>> &mtk_clk_gate_ops_setclr)
>>>> +
>>>> +#define GATE_VDO0_2_FLAGS(_id, _name, _parent, _shift,
>>>> _flags)         \
>>>> +       GATE_MTK_FLAGS(_id, _name, _parent, &vdo0_2_cg_regs,
>>>> _shift,    \
>>>> +       &mtk_clk_gate_ops_setclr, _flags)
>>>> +
>>>> +static const struct mtk_gate vdo0_clks[] = {
>>>> +       /* VDO0_0 */
>>>> +       GATE_VDO0_0(CLK_VDO0_DISP_OVL0, "vdo0_disp_ovl0",
>>>> "top_vpp", 0),
>>>> +       GATE_VDO0_0(CLK_VDO0_FAKE_ENG0, "vdo0_fake_eng0",
>>>> "top_vpp", 2),
>>>> +       GATE_VDO0_0(CLK_VDO0_DISP_CCORR0, "vdo0_disp_ccorr0",
>>>> "top_vpp", 4),
>>>> +       GATE_VDO0_0(CLK_VDO0_DISP_MUTEX0, "vdo0_disp_mutex0",
>>>> "top_vpp", 6),
>>>> +       GATE_VDO0_0(CLK_VDO0_DISP_GAMMA0, "vdo0_disp_gamma0",
>>>> "top_vpp", 8),
>>>> +       GATE_VDO0_0(CLK_VDO0_DISP_DITHER0, "vdo0_disp_dither0",
>>>> "top_vpp", 10),
>>>> +       GATE_VDO0_0(CLK_VDO0_DISP_WDMA0, "vdo0_disp_wdma0",
>>>> "top_vpp", 17),
>>>> +       GATE_VDO0_0(CLK_VDO0_DISP_RDMA0, "vdo0_disp_rdma0",
>>>> "top_vpp", 19),
>>>> +       GATE_VDO0_0(CLK_VDO0_DSI0, "vdo0_dsi0", "top_vpp", 21),
>>>> +       GATE_VDO0_0(CLK_VDO0_DSI1, "vdo0_dsi1", "top_vpp", 22),
>>>> +       GATE_VDO0_0(CLK_VDO0_DSC_WRAP0, "vdo0_dsc_wrap0",
>>>> "top_vpp", 23),
>>>> +       GATE_VDO0_0(CLK_VDO0_VPP_MERGE0, "vdo0_vpp_merge0",
>>>> "top_vpp", 24),
>>>> +       GATE_VDO0_0(CLK_VDO0_DP_INTF0, "vdo0_dp_intf0",
>>>> "top_vpp", 25),
>>>> +       GATE_VDO0_0(CLK_VDO0_DISP_AAL0, "vdo0_disp_aal0",
>>>> "top_vpp", 26),
>>>> +       GATE_VDO0_0(CLK_VDO0_INLINEROT0, "vdo0_inlinerot0",
>>>> "top_vpp", 27),
>>>> +       GATE_VDO0_0(CLK_VDO0_APB_BUS, "vdo0_apb_bus", "top_vpp",
>>>> 28),
>>>> +       GATE_VDO0_0(CLK_VDO0_DISP_COLOR0, "vdo0_disp_color0",
>>>> "top_vpp", 29),
>>>> +       GATE_VDO0_0(CLK_VDO0_MDP_WROT0, "vdo0_mdp_wrot0",
>>>> "top_vpp", 30),
>>>> +       GATE_VDO0_0(CLK_VDO0_DISP_RSZ0, "vdo0_disp_rsz0",
>>>> "top_vpp", 31),
>>>> +       /* VDO0_1 */
>>>> +       GATE_VDO0_1(CLK_VDO0_DISP_POSTMASK0,
>>>> "vdo0_disp_postmask0", "top_vpp", 0),
>>>> +       GATE_VDO0_1(CLK_VDO0_FAKE_ENG1, "vdo0_fake_eng1",
>>>> "top_vpp", 1),
>>>> +       GATE_VDO0_1(CLK_VDO0_DL_ASYNC2, "vdo0_dl_async2",
>>>> "top_vpp", 5),
>>>> +       GATE_VDO0_1(CLK_VDO0_DL_RELAY3, "vdo0_dl_relay3",
>>>> "top_vpp", 6),
>>>> +       GATE_VDO0_1(CLK_VDO0_DL_RELAY4, "vdo0_dl_relay4",
>>>> "top_vpp", 7),
>>>> +       GATE_VDO0_1(CLK_VDO0_SMI_GALS, "vdo0_smi_gals",
>>>> "top_vpp", 10),
>>>> +       GATE_VDO0_1(CLK_VDO0_SMI_COMMON, "vdo0_smi_common",
>>>> "top_vpp", 11),
>>>> +       GATE_VDO0_1(CLK_VDO0_SMI_EMI, "vdo0_smi_emi", "top_vpp",
>>>> 12),
>>>> +       GATE_VDO0_1(CLK_VDO0_SMI_IOMMU, "vdo0_smi_iommu",
>>>> "top_vpp", 13),
>>>> +       GATE_VDO0_1(CLK_VDO0_SMI_LARB, "vdo0_smi_larb",
>>>> "top_vpp", 14),
>>>> +       GATE_VDO0_1(CLK_VDO0_SMI_RSI, "vdo0_smi_rsi", "top_vpp",
>>>> 15),
>>>> +       /* VDO0_2 */
>>>> +       GATE_VDO0_2(CLK_VDO0_DSI0_DSI, "vdo0_dsi0_dsi",
>>>> "top_dsi_occ", 0),
>>>> +       GATE_VDO0_2(CLK_VDO0_DSI1_DSI, "vdo0_dsi1_dsi",
>>>> "top_dsi_occ", 8),
>>>> +       GATE_VDO0_2_FLAGS(CLK_VDO0_DP_INTF0_DP_INTF,
>>>> "vdo0_dp_intf0_dp_intf",
>>>> +               "top_edp", 16, CLK_SET_RATE_PARENT),
>>>> +};
>>>> +
>>>> +static int clk_mt8188_vdo0_probe(struct platform_device *pdev)
>>>> +{
>>>> +       struct device *dev = &pdev->dev;
>>>> +       struct device_node *node = dev->parent->of_node;
>>>> +       struct clk_hw_onecell_data *clk_data;
>>>> +       int r;
>>>> +
>>>> +       clk_data = mtk_alloc_clk_data(CLK_VDO0_NR_CLK);
>>>> +       if (!clk_data)
>>>> +               return -ENOMEM;
>>>> +
>>>> +       r = mtk_clk_register_gates(node, vdo0_clks,
>>>> ARRAY_SIZE(vdo0_clks), clk_data);
>>>
>>> This API was changed. Please rebase onto the latest -next and
>>> update.
>>>
>>> Angelo (CC-ed) also mentioned a new simple probe variant for non-DT
>>> clock drivers is being developed. He didn't mention a timeline
>>> though.
>>
>> I've already tested the new simple probe variant for non-DT clock
>> drivers and
>> it works fine on MT8173, MT8192 and MT8195.
>>
>> Timeline - I should be able to push the part 2 series next week,
>> which will include
>> more conversion to simple probe and almost all clock drivers changed
>> to allow
>> building as modules.
>>
>> Cheers,
>> Angelo
>>
> Thank you for your suggestions.
> When the new simple probe variant and building as modules are ready, I
> will rebase latest-next and update it.

It's *finally* ready as it's fully tested and reviewed.

You can go on with a rebase on top of it:

https://patchwork.kernel.org/project/linux-mediatek/list/?series=726914

Regards,
Angelo