From: Anshuman Khandual <anshuman.khandual@arm.com>
To: Rob Herring <robh@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org,
linux-kernel@vger.kernel.org,
Mathieu Poirier <mathieu.poirier@linaro.org>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Mike Leach <mike.leach@linaro.org>,
Linu Cherian <lcherian@marvell.com>,
devicetree@vger.kernel.org
Subject: Re: [PATCH 11/11] dts: bindings: Document device tree binding for Arm TRBE
Date: Mon, 4 Jan 2021 09:14:24 +0530 [thread overview]
Message-ID: <21536a1c-0878-a390-aff3-fc2300be6941@arm.com> (raw)
In-Reply-To: <20210103170540.GA4055084@robh.at.kernel.org>
On 1/3/21 10:35 PM, Rob Herring wrote:
> On Wed, Dec 23, 2020 at 03:33:43PM +0530, Anshuman Khandual wrote:
>> This patch documents the device tree binding in use for Arm TRBE.
>>
>> Cc: devicetree@vger.kernel.org
>> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
>> Cc: Mike Leach <mike.leach@linaro.org>
>> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>> ---
>> Changes in V1:
>>
>> - TRBE DT entry has been renamed as 'arm, trace-buffer-extension'
>>
>> Documentation/devicetree/bindings/arm/trbe.txt | 20 ++++++++++++++++++++
>> 1 file changed, 20 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/arm/trbe.txt
>>
>> diff --git a/Documentation/devicetree/bindings/arm/trbe.txt b/Documentation/devicetree/bindings/arm/trbe.txt
>> new file mode 100644
>> index 0000000..001945d
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/trbe.txt
>> @@ -0,0 +1,20 @@
>> +* Trace Buffer Extension (TRBE)
>> +
>> +Trace Buffer Extension (TRBE) is used for collecting trace data generated
>> +from a corresponding trace unit (ETE) using an in memory trace buffer.
>> +
>> +** TRBE Required properties:
>> +
>> +- compatible : should be one of:
>> + "arm,trace-buffer-extension"
>> +
>> +- interrupts : Exactly 1 PPI must be listed. For heterogeneous systems where
>> + TRBE is only supported on a subset of the CPUs, please consult
>> + the arm,gic-v3 binding for details on describing a PPI partition.
>> +
>> +** Example:
>> +
>> +trbe {
>> + compatible = "arm,trace-buffer-extension";
>> + interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
>
> If only an interrupt, then could just be part of ETE? If not, how is
> this hardware block accessed? An interrupt alone is not enough unless
> there's some architected way to access.
TRBE hardware block is accessed via respective new system registers but the
PPI number where the IRQ will be triggered for various buffer events, would
depend on the platform as defined in the SBSA.
TRBE would need a ETE to work but the reverse is not true. ETE might just
be present without a corresponding TRBE and can work with traditional sinks.
Hence just wondering whether it would be prudent to add the TRBE interrupt
number as part of the ETE DT specification.
next prev parent reply other threads:[~2021-01-04 3:45 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-23 10:03 [PATCH 00/11] arm64: coresight: Enable ETE and TRBE Anshuman Khandual
2020-12-23 10:03 ` [PATCH 01/11] coresight: etm-perf: Allow an event to use different sinks Anshuman Khandual
2020-12-23 10:03 ` [PATCH 02/11] coresight: Do not scan for graph if none is present Anshuman Khandual
2020-12-23 10:03 ` [PATCH 03/11] coresight: etm4x: Add support for PE OS lock Anshuman Khandual
2020-12-23 10:03 ` [PATCH 04/11] coresight: ete: Add support for ETE sysreg access Anshuman Khandual
2020-12-23 10:03 ` [PATCH 05/11] coresight: ete: Add support for ETE tracing Anshuman Khandual
2020-12-23 10:03 ` [PATCH 06/11] dts: bindings: Document device tree bindings for ETE Anshuman Khandual
2021-01-03 17:02 ` Rob Herring
2021-01-04 14:42 ` Suzuki K Poulose
2021-01-04 18:15 ` Mathieu Poirier
2021-01-04 20:31 ` Rob Herring
2020-12-23 10:03 ` [PATCH 07/11] arm64: Add TRBE definitions Anshuman Khandual
2020-12-23 10:03 ` [PATCH 08/11] coresight: core: Add support for dedicated percpu sinks Anshuman Khandual
2020-12-23 10:03 ` [PATCH 09/11] coresight: etm-perf: Truncate the perf record if handle has no space Anshuman Khandual
2020-12-23 10:03 ` [PATCH 10/11] coresight: sink: Add TRBE driver Anshuman Khandual
2021-01-04 16:28 ` Suzuki K Poulose
2021-01-05 9:29 ` Anshuman Khandual
2021-01-05 11:37 ` Suzuki K Poulose
2021-01-06 11:50 ` Anshuman Khandual
2021-01-07 14:01 ` Suzuki K Poulose
2020-12-23 10:03 ` [PATCH 11/11] dts: bindings: Document device tree binding for Arm TRBE Anshuman Khandual
2021-01-03 17:05 ` Rob Herring
2021-01-04 3:44 ` Anshuman Khandual [this message]
2021-01-07 14:05 ` Suzuki K Poulose
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