Re: [PATCH v2] x86: Skip WBINVD instruction for VM guest

From: Dave Hansen <dave.hansen@intel.com>
To: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>,
	Thomas Gleixner <tglx@linutronix.de>
Cc: Kuppuswamy Sathyanarayanan 
	<sathyanarayanan.kuppuswamy@linux.intel.com>,
	Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
	Dave Hansen <dave.hansen@linux.intel.com>,
	x86@kernel.org, "Rafael J . Wysocki" <rjw@rjwysocki.net>,
	"H . Peter Anvin" <hpa@zytor.com>,
	Tony Luck <tony.luck@intel.com>,
	Dan Williams <dan.j.williams@intel.com>,
	Andi Kleen <ak@linux.intel.com>,
	Kuppuswamy Sathyanarayanan <knsathya@kernel.org>,
	linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org
Subject: Re: [PATCH v2] x86: Skip WBINVD instruction for VM guest
Date: Fri, 3 Dec 2021 16:20:34 -0800	[thread overview]
Message-ID: <2519e6b6-4f74-e2f8-c428-0fceb0e16472@intel.com> (raw)
In-Reply-To: <20211203234915.jw6kdd2qnfrionch@black.fi.intel.com>

On 12/3/21 3:49 PM, Kirill A. Shutemov wrote:
> -	ACPI_FLUSH_CPU_CACHE();
> +	if (acpi_state >= ACPI_STATE_S1 && acpi_state <= ACPI_STATE_S3)
> +		ACPI_FLUSH_CPU_CACHE();

It's a bit of a bummer that this per-sleep-state logic has to be
repeated so many time.

If you pass acpi_state into ACPI_FLUSH_CPU_CACHE() can you centralize
the set of places where that knowledge about which sleep states require
flushing?

> TDX doesn't support these S- and C-states. TDX is only supports S0 and S5.

This makes me a bit nervous.  Is this "the first TDX implementation
supports..." or "the TDX architecture *prohibits* supporting S1 (or
whatever"?

I really think we need some kind of architecture guarantee.  Without
that, we risk breaking things if someone at our employer simply changes
their mind.

The:

> #define ACPI_FLUSH_CPU_CACHE_PHYS()     \
>         if (!cpu_feature_enabled(XXX))	\
>         	wbinvd();               \  

does seem simpler and less error-prone than this, though.