linux-kernel.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Dave Hansen <dave.hansen@intel.com>
To: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>,
	Thomas Gleixner <tglx@linutronix.de>
Cc: Kuppuswamy Sathyanarayanan 
	<sathyanarayanan.kuppuswamy@linux.intel.com>,
	Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
	Dave Hansen <dave.hansen@linux.intel.com>,
	x86@kernel.org, "Rafael J . Wysocki" <rjw@rjwysocki.net>,
	"H . Peter Anvin" <hpa@zytor.com>,
	Tony Luck <tony.luck@intel.com>,
	Dan Williams <dan.j.williams@intel.com>,
	Andi Kleen <ak@linux.intel.com>,
	Kuppuswamy Sathyanarayanan <knsathya@kernel.org>,
	linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org
Subject: Re: [PATCH v2] x86: Skip WBINVD instruction for VM guest
Date: Thu, 2 Dec 2021 14:38:05 -0800	[thread overview]
Message-ID: <e2cccb22-1e83-55c6-bb12-906335320b0d@intel.com> (raw)
In-Reply-To: <20211202222109.pcsgm2jska3obvmx@black.fi.intel.com>

On 12/2/21 2:21 PM, Kirill A. Shutemov wrote:
>   - NVDIMMs are not supported inside TDX. If it will change we would need
>     to deal with cache flushing for this case. Hopefully, we would be able
>     to avoid WBINVD.

Maybe we can use this as an example since we have our friendly NVDIMM
developers on cc already.

Let's say that tomorrow Intel decides that NVDIMMs are OK to use in TDX.
 It might not be a good idea, but Intel could arbitrarily start
supporting them immediately.  Further, someone could take today's kernel
and stick it on some future, fancy platform which does support TDX and
NVDIMMs.  In other words, there are multiple reasons we can't just say
"TDX doesn't support NVDIMMs" and forget about it.

If either of those happened, we'd have a NVDIMM driver which uses
WBINVD, expects cache flushing and subsequently loses data.  I think we
can all agree that's a bad idea.

So, we've got two different cases that land in the #VE handler:

	1. Silly ACPI code that doesn't need WBINVD behavior

	2. Less silly NVDIMM code that badly needs WBINVD behavior

... but we have a #VE handler that can't tell the difference.

To me, that says we need to do _something_ different than just papering
over the WBINVD in the #VE handler.

Does anyone have a different take on it?

  reply	other threads:[~2021-12-02 22:39 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-16  0:50 [PATCH v1 1/1] x86: Skip WBINVD instruction for VM guest Kuppuswamy Sathyanarayanan
2021-11-16 16:24 ` Borislav Petkov
2021-11-16 16:36   ` Sathyanarayanan Kuppuswamy
2021-11-19  4:03   ` [PATCH v2] " Kuppuswamy Sathyanarayanan
2021-11-25  0:40     ` Thomas Gleixner
2021-12-02 22:21       ` Kirill A. Shutemov
2021-12-02 22:38         ` Dave Hansen [this message]
2021-12-02 23:48         ` Thomas Gleixner
2021-12-03 23:49           ` Kirill A. Shutemov
2021-12-04  0:20             ` Dave Hansen
2021-12-04  0:54               ` Kirill A. Shutemov
2021-12-06 15:35                 ` Dave Hansen
2021-12-06 16:39                   ` Dan Williams
2021-12-06 16:53                     ` Dave Hansen
2021-12-06 17:51                       ` Dan Williams
2021-12-04 20:27             ` Rafael J. Wysocki
2021-12-06 12:29               ` [PATCH 0/4] ACPI/ACPICA: Only flush caches on S1/S2/S3 and C3 Kirill A. Shutemov
2021-12-06 12:29                 ` [PATCH 1/4] ACPICA: Do not flush cache for on entering S4 and S5 Kirill A. Shutemov
2021-12-08 14:58                   ` Rafael J. Wysocki
2021-12-06 12:29                 ` [PATCH 2/4] ACPI: PM: Remove redundant cache flushing Kirill A. Shutemov
2021-12-07 16:35                   ` Rafael J. Wysocki
2021-12-09 13:32                     ` Kirill A. Shutemov
2021-12-17 18:04                       ` Rafael J. Wysocki
2021-12-06 12:29                 ` [PATCH 3/4] ACPI: processor idle: Only flush cache on entering C3 Kirill A. Shutemov
2021-12-06 15:03                   ` Peter Zijlstra
2021-12-08 16:26                     ` Rafael J. Wysocki
2021-12-09 13:33                       ` Kirill A. Shutemov
2021-12-17 17:58                         ` Rafael J. Wysocki
2021-12-06 12:29                 ` [PATCH 4/4] ACPI: PM: Avoid cache flush on entering S4 Kirill A. Shutemov
2021-12-08 15:10                   ` Rafael J. Wysocki
2021-12-08 16:04                     ` Kirill A. Shutemov
2021-12-08 16:16                       ` Rafael J. Wysocki

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=e2cccb22-1e83-55c6-bb12-906335320b0d@intel.com \
    --to=dave.hansen@intel.com \
    --cc=ak@linux.intel.com \
    --cc=bp@alien8.de \
    --cc=dan.j.williams@intel.com \
    --cc=dave.hansen@linux.intel.com \
    --cc=hpa@zytor.com \
    --cc=kirill.shutemov@linux.intel.com \
    --cc=knsathya@kernel.org \
    --cc=linux-acpi@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=mingo@redhat.com \
    --cc=rjw@rjwysocki.net \
    --cc=sathyanarayanan.kuppuswamy@linux.intel.com \
    --cc=tglx@linutronix.de \
    --cc=tony.luck@intel.com \
    --cc=x86@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).