* [v1 01/16] dt-bindings: ARM: Mediatek: Add new document bindings of MT8186 clock
[not found] <20220110134416.5191-1-chun-jie.chen@mediatek.com>
@ 2022-01-10 13:44 ` Chun-Jie Chen
2022-01-22 0:25 ` Rob Herring
2022-01-10 13:44 ` [v1 02/16] clk: mediatek: Add dt-bindings of MT8186 clocks Chun-Jie Chen
` (14 subsequent siblings)
15 siblings, 1 reply; 39+ messages in thread
From: Chun-Jie Chen @ 2022-01-10 13:44 UTC (permalink / raw)
To: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring
Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group,
Chun-Jie Chen
This patch adds the new binding documentation for system clock
and functional clock on Mediatek MT8186.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
.../arm/mediatek/mediatek,mt8186-clock.yaml | 133 ++++++++++++++++++
.../mediatek/mediatek,mt8186-sys-clock.yaml | 74 ++++++++++
2 files changed, 207 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-clock.yaml
create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-clock.yaml
new file mode 100644
index 000000000000..fc39101bc9b0
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-clock.yaml
@@ -0,0 +1,133 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-clock.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Mediatek Functional Clock Controller for MT8186
+
+maintainers:
+ - Chun-Jie Chen <chun-jie.chen@mediatek.com>
+
+description:
+ The clock architecture in Mediatek like below
+ PLLs -->
+ dividers -->
+ muxes
+ -->
+ clock gate
+
+ The devices provide clock gate control in different IP blocks.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8186-imp_iic_wrap
+ - mediatek,mt8186-mfgsys
+ - mediatek,mt8186-wpesys
+ - mediatek,mt8186-imgsys1
+ - mediatek,mt8186-imgsys2
+ - mediatek,mt8186-vdecsys
+ - mediatek,mt8186-vencsys
+ - mediatek,mt8186-camsys
+ - mediatek,mt8186-camsys_rawa
+ - mediatek,mt8186-camsys_rawb
+ - mediatek,mt8186-mdpsys
+ - mediatek,mt8186-ipesys
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ imp_iic_wrap: clock-controller@11017000 {
+ compatible = "mediatek,mt8186-imp_iic_wrap";
+ reg = <0x11017000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ - |
+ mfgsys: clock-controller@13000000 {
+ compatible = "mediatek,mt8186-mfgsys";
+ reg = <0x13000000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ - |
+ wpesys: clock-controller@14020000 {
+ compatible = "mediatek,mt8186-wpesys";
+ reg = <0x14020000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ - |
+ imgsys1: clock-controller@15020000 {
+ compatible = "mediatek,mt8186-imgsys1";
+ reg = <0x15020000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ - |
+ imgsys2: clock-controller@15820000 {
+ compatible = "mediatek,mt8186-imgsys2";
+ reg = <0x15820000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ - |
+ vdecsys: clock-controller@1602f000 {
+ compatible = "mediatek,mt8186-vdecsys";
+ reg = <0x1602f000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ - |
+ vencsys: clock-controller@17000000 {
+ compatible = "mediatek,mt8186-vencsys";
+ reg = <0x17000000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ - |
+ camsys: clock-controller@1a000000 {
+ compatible = "mediatek,mt8186-camsys";
+ reg = <0x1a000000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ - |
+ camsys_rawa: clock-controller@1a04f000 {
+ compatible = "mediatek,mt8186-camsys_rawa";
+ reg = <0x1a04f000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ - |
+ camsys_rawb: clock-controller@1a06f000 {
+ compatible = "mediatek,mt8186-camsys_rawb";
+ reg = <0x1a06f000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ - |
+ mdpsys: clock-controller@1b000000 {
+ compatible = "mediatek,mt8186-mdpsys";
+ reg = <0x1b000000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ - |
+ ipesys: clock-controller@1c000000 {
+ compatible = "mediatek,mt8186-ipesys";
+ reg = <0x1c000000 0x1000>;
+ #clock-cells = <1>;
+ };
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml
new file mode 100644
index 000000000000..11473971a165
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-sys-clock.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Mediatek System Clock Controller for MT8186
+
+maintainers:
+ - Chun-Jie Chen <chun-jie.chen@mediatek.com>
+
+description:
+ The clock architecture in Mediatek like below
+ PLLs -->
+ dividers -->
+ muxes
+ -->
+ clock gate
+
+ The apmixedsys provides most of PLLs which generated from SoC 26m.
+ The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
+ The infracfg_ao provides clock gate in peripheral and infrastructure IP blocks.
+ The mcusys provides mux control to select the clock source in AP MCU.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8186-mcusys
+ - mediatek,mt8186-topckgen
+ - mediatek,mt8186-infracfg_ao
+ - mediatek,mt8186-apmixedsys
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ mcusys: syscon@c53a000 {
+ compatible = "mediatek,mt8186-mcusys", "syscon";
+ reg = <0xc53a000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ - |
+ topckgen: syscon@10000000 {
+ compatible = "mediatek,mt8186-topckgen", "syscon";
+ reg = <0x10000000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ - |
+ infracfg_ao: syscon@10001000 {
+ compatible = "mediatek,mt8186-infracfg_ao", "syscon";
+ reg = <0x10001000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ - |
+ apmixedsys: syscon@1000c000 {
+ compatible = "mediatek,mt8186-apmixedsys", "syscon";
+ reg = <0x1000c000 0x1000>;
+ #clock-cells = <1>;
+ };
--
2.18.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [v1 01/16] dt-bindings: ARM: Mediatek: Add new document bindings of MT8186 clock
2022-01-10 13:44 ` [v1 01/16] dt-bindings: ARM: Mediatek: Add new document bindings of MT8186 clock Chun-Jie Chen
@ 2022-01-22 0:25 ` Rob Herring
2022-02-09 1:40 ` Chun-Jie Chen
0 siblings, 1 reply; 39+ messages in thread
From: Rob Herring @ 2022-01-22 0:25 UTC (permalink / raw)
To: Chun-Jie Chen
Cc: Matthias Brugger, Stephen Boyd, Nicolas Boichat,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group
On Mon, Jan 10, 2022 at 09:44:01PM +0800, Chun-Jie Chen wrote:
> This patch adds the new binding documentation for system clock
> and functional clock on Mediatek MT8186.
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> ---
> .../arm/mediatek/mediatek,mt8186-clock.yaml | 133 ++++++++++++++++++
> .../mediatek/mediatek,mt8186-sys-clock.yaml | 74 ++++++++++
> 2 files changed, 207 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-clock.yaml
> create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-clock.yaml
> new file mode 100644
> index 000000000000..fc39101bc9b0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-clock.yaml
> @@ -0,0 +1,133 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-clock.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Mediatek Functional Clock Controller for MT8186
> +
> +maintainers:
> + - Chun-Jie Chen <chun-jie.chen@mediatek.com>
> +
> +description:
> + The clock architecture in Mediatek like below
> + PLLs -->
> + dividers -->
> + muxes
> + -->
> + clock gate
> +
> + The devices provide clock gate control in different IP blocks.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - mediatek,mt8186-imp_iic_wrap
> + - mediatek,mt8186-mfgsys
> + - mediatek,mt8186-wpesys
> + - mediatek,mt8186-imgsys1
> + - mediatek,mt8186-imgsys2
> + - mediatek,mt8186-vdecsys
> + - mediatek,mt8186-vencsys
> + - mediatek,mt8186-camsys
> + - mediatek,mt8186-camsys_rawa
> + - mediatek,mt8186-camsys_rawb
> + - mediatek,mt8186-mdpsys
> + - mediatek,mt8186-ipesys
> + reg:
> + maxItems: 1
> +
> + '#clock-cells':
> + const: 1
> +
> +required:
> + - compatible
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + imp_iic_wrap: clock-controller@11017000 {
> + compatible = "mediatek,mt8186-imp_iic_wrap";
> + reg = <0x11017000 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + - |
> + mfgsys: clock-controller@13000000 {
> + compatible = "mediatek,mt8186-mfgsys";
> + reg = <0x13000000 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + - |
> + wpesys: clock-controller@14020000 {
> + compatible = "mediatek,mt8186-wpesys";
> + reg = <0x14020000 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + - |
> + imgsys1: clock-controller@15020000 {
> + compatible = "mediatek,mt8186-imgsys1";
> + reg = <0x15020000 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + - |
> + imgsys2: clock-controller@15820000 {
> + compatible = "mediatek,mt8186-imgsys2";
> + reg = <0x15820000 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + - |
> + vdecsys: clock-controller@1602f000 {
> + compatible = "mediatek,mt8186-vdecsys";
> + reg = <0x1602f000 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + - |
> + vencsys: clock-controller@17000000 {
> + compatible = "mediatek,mt8186-vencsys";
> + reg = <0x17000000 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + - |
> + camsys: clock-controller@1a000000 {
> + compatible = "mediatek,mt8186-camsys";
> + reg = <0x1a000000 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + - |
> + camsys_rawa: clock-controller@1a04f000 {
> + compatible = "mediatek,mt8186-camsys_rawa";
> + reg = <0x1a04f000 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + - |
> + camsys_rawb: clock-controller@1a06f000 {
> + compatible = "mediatek,mt8186-camsys_rawb";
> + reg = <0x1a06f000 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + - |
> + mdpsys: clock-controller@1b000000 {
> + compatible = "mediatek,mt8186-mdpsys";
> + reg = <0x1b000000 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + - |
> + ipesys: clock-controller@1c000000 {
> + compatible = "mediatek,mt8186-ipesys";
> + reg = <0x1c000000 0x1000>;
> + #clock-cells = <1>;
> + };
There's little point in enumerating every possible compatible. 1 example
is more than enough.
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml
> new file mode 100644
> index 000000000000..11473971a165
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml
> @@ -0,0 +1,74 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-sys-clock.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Mediatek System Clock Controller for MT8186
> +
> +maintainers:
> + - Chun-Jie Chen <chun-jie.chen@mediatek.com>
> +
> +description:
> + The clock architecture in Mediatek like below
> + PLLs -->
> + dividers -->
> + muxes
> + -->
> + clock gate
> +
> + The apmixedsys provides most of PLLs which generated from SoC 26m.
> + The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
> + The infracfg_ao provides clock gate in peripheral and infrastructure IP blocks.
> + The mcusys provides mux control to select the clock source in AP MCU.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - mediatek,mt8186-mcusys
> + - mediatek,mt8186-topckgen
> + - mediatek,mt8186-infracfg_ao
> + - mediatek,mt8186-apmixedsys
> + - const: syscon
> +
> + reg:
> + maxItems: 1
> +
> + '#clock-cells':
> + const: 1
> +
> +required:
> + - compatible
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + mcusys: syscon@c53a000 {
clock-controller@...
Drop unused labels.
> + compatible = "mediatek,mt8186-mcusys", "syscon";
> + reg = <0xc53a000 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + - |
> + topckgen: syscon@10000000 {
> + compatible = "mediatek,mt8186-topckgen", "syscon";
> + reg = <0x10000000 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + - |
> + infracfg_ao: syscon@10001000 {
> + compatible = "mediatek,mt8186-infracfg_ao", "syscon";
> + reg = <0x10001000 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + - |
> + apmixedsys: syscon@1000c000 {
> + compatible = "mediatek,mt8186-apmixedsys", "syscon";
> + reg = <0x1000c000 0x1000>;
> + #clock-cells = <1>;
> + };
Again, 1 example is enough.
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [v1 01/16] dt-bindings: ARM: Mediatek: Add new document bindings of MT8186 clock
2022-01-22 0:25 ` Rob Herring
@ 2022-02-09 1:40 ` Chun-Jie Chen
2022-02-15 10:23 ` Chun-Jie Chen
0 siblings, 1 reply; 39+ messages in thread
From: Chun-Jie Chen @ 2022-02-09 1:40 UTC (permalink / raw)
To: Rob Herring
Cc: Matthias Brugger, Stephen Boyd, Nicolas Boichat,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group
On Fri, 2022-01-21 at 18:25 -0600, Rob Herring wrote:
> On Mon, Jan 10, 2022 at 09:44:01PM +0800, Chun-Jie Chen wrote:
> > This patch adds the new binding documentation for system clock
> > and functional clock on Mediatek MT8186.
> >
> > Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> > ---
> > .../arm/mediatek/mediatek,mt8186-clock.yaml | 133
> > ++++++++++++++++++
> > .../mediatek/mediatek,mt8186-sys-clock.yaml | 74 ++++++++++
> > 2 files changed, 207 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-
> > clock.yaml
> > create mode 100644
> > Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-
> > clock.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-
> > clock.yaml
> > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-
> > clock.yaml
> > new file mode 100644
> > index 000000000000..fc39101bc9b0
> > --- /dev/null
> > +++
> > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-
> > clock.yaml
> > @@ -0,0 +1,133 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: "
> > https://urldefense.com/v3/__http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-clock.yaml*__;Iw!!CTRNKA9wMg0ARbw!3pIyNVU0grMb7zKVQZoRO2z-eKrg6FnGcieEON8cCw84G6_W7Tt4GEFwytcYEXyrcj6e$
> > "
> > +$schema: "
> > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!3pIyNVU0grMb7zKVQZoRO2z-eKrg6FnGcieEON8cCw84G6_W7Tt4GEFwytcYEUOCCW1i$
> > "
> > +
> > +title: Mediatek Functional Clock Controller for MT8186
> > +
> > +maintainers:
> > + - Chun-Jie Chen <chun-jie.chen@mediatek.com>
> > +
> > +description:
> > + The clock architecture in Mediatek like below
> > + PLLs -->
> > + dividers -->
> > + muxes
> > + -->
> > + clock gate
> > +
> > + The devices provide clock gate control in different IP blocks.
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - mediatek,mt8186-imp_iic_wrap
> > + - mediatek,mt8186-mfgsys
> > + - mediatek,mt8186-wpesys
> > + - mediatek,mt8186-imgsys1
> > + - mediatek,mt8186-imgsys2
> > + - mediatek,mt8186-vdecsys
> > + - mediatek,mt8186-vencsys
> > + - mediatek,mt8186-camsys
> > + - mediatek,mt8186-camsys_rawa
> > + - mediatek,mt8186-camsys_rawb
> > + - mediatek,mt8186-mdpsys
> > + - mediatek,mt8186-ipesys
> > + reg:
> > + maxItems: 1
> > +
> > + '#clock-cells':
> > + const: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + imp_iic_wrap: clock-controller@11017000 {
> > + compatible = "mediatek,mt8186-imp_iic_wrap";
> > + reg = <0x11017000 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + - |
> > + mfgsys: clock-controller@13000000 {
> > + compatible = "mediatek,mt8186-mfgsys";
> > + reg = <0x13000000 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + - |
> > + wpesys: clock-controller@14020000 {
> > + compatible = "mediatek,mt8186-wpesys";
> > + reg = <0x14020000 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + - |
> > + imgsys1: clock-controller@15020000 {
> > + compatible = "mediatek,mt8186-imgsys1";
> > + reg = <0x15020000 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + - |
> > + imgsys2: clock-controller@15820000 {
> > + compatible = "mediatek,mt8186-imgsys2";
> > + reg = <0x15820000 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + - |
> > + vdecsys: clock-controller@1602f000 {
> > + compatible = "mediatek,mt8186-vdecsys";
> > + reg = <0x1602f000 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + - |
> > + vencsys: clock-controller@17000000 {
> > + compatible = "mediatek,mt8186-vencsys";
> > + reg = <0x17000000 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + - |
> > + camsys: clock-controller@1a000000 {
> > + compatible = "mediatek,mt8186-camsys";
> > + reg = <0x1a000000 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + - |
> > + camsys_rawa: clock-controller@1a04f000 {
> > + compatible = "mediatek,mt8186-camsys_rawa";
> > + reg = <0x1a04f000 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + - |
> > + camsys_rawb: clock-controller@1a06f000 {
> > + compatible = "mediatek,mt8186-camsys_rawb";
> > + reg = <0x1a06f000 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + - |
> > + mdpsys: clock-controller@1b000000 {
> > + compatible = "mediatek,mt8186-mdpsys";
> > + reg = <0x1b000000 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + - |
> > + ipesys: clock-controller@1c000000 {
> > + compatible = "mediatek,mt8186-ipesys";
> > + reg = <0x1c000000 0x1000>;
> > + #clock-cells = <1>;
> > + };
>
> There's little point in enumerating every possible compatible. 1
> example
> is more than enough.
>
>
Ok, I will fix it in next patch.
> > diff --git
> > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-
> > sys-clock.yaml
> > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-
> > sys-clock.yaml
> > new file mode 100644
> > index 000000000000..11473971a165
> > --- /dev/null
> > +++
> > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-
> > sys-clock.yaml
> > @@ -0,0 +1,74 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: "
> > https://urldefense.com/v3/__http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-sys-clock.yaml*__;Iw!!CTRNKA9wMg0ARbw!3pIyNVU0grMb7zKVQZoRO2z-eKrg6FnGcieEON8cCw84G6_W7Tt4GEFwytcYERailYtq$
> > "
> > +$schema: "
> > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!3pIyNVU0grMb7zKVQZoRO2z-eKrg6FnGcieEON8cCw84G6_W7Tt4GEFwytcYEUOCCW1i$
> > "
> > +
> > +title: Mediatek System Clock Controller for MT8186
> > +
> > +maintainers:
> > + - Chun-Jie Chen <chun-jie.chen@mediatek.com>
> > +
> > +description:
> > + The clock architecture in Mediatek like below
> > + PLLs -->
> > + dividers -->
> > + muxes
> > + -->
> > + clock gate
> > +
> > + The apmixedsys provides most of PLLs which generated from SoC
> > 26m.
> > + The topckgen provides dividers and muxes which provide the clock
> > source to other IP blocks.
> > + The infracfg_ao provides clock gate in peripheral and
> > infrastructure IP blocks.
> > + The mcusys provides mux control to select the clock source in AP
> > MCU.
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - mediatek,mt8186-mcusys
> > + - mediatek,mt8186-topckgen
> > + - mediatek,mt8186-infracfg_ao
> > + - mediatek,mt8186-apmixedsys
> > + - const: syscon
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + '#clock-cells':
> > + const: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + mcusys: syscon@c53a000 {
>
> clock-controller@...
>
> Drop unused labels.
>
Ok, I will change to pure clock-controller
Thanks!
Best Regards,
Chun-Jie
> > + compatible = "mediatek,mt8186-mcusys", "syscon";
> > + reg = <0xc53a000 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + - |
> > + topckgen: syscon@10000000 {
> > + compatible = "mediatek,mt8186-topckgen", "syscon";
> > + reg = <0x10000000 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + - |
> > + infracfg_ao: syscon@10001000 {
> > + compatible = "mediatek,mt8186-infracfg_ao", "syscon";
> > + reg = <0x10001000 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + - |
> > + apmixedsys: syscon@1000c000 {
> > + compatible = "mediatek,mt8186-apmixedsys", "syscon";
> > + reg = <0x1000c000 0x1000>;
> > + #clock-cells = <1>;
> > + };
>
> Again, 1 example is enough.
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [v1 01/16] dt-bindings: ARM: Mediatek: Add new document bindings of MT8186 clock
2022-02-09 1:40 ` Chun-Jie Chen
@ 2022-02-15 10:23 ` Chun-Jie Chen
0 siblings, 0 replies; 39+ messages in thread
From: Chun-Jie Chen @ 2022-02-15 10:23 UTC (permalink / raw)
To: Rob Herring
Cc: Matthias Brugger, Stephen Boyd, Nicolas Boichat,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group
On Wed, 2022-02-09 at 09:40 +0800, Chun-Jie Chen wrote:
> On Fri, 2022-01-21 at 18:25 -0600, Rob Herring wrote:
> > On Mon, Jan 10, 2022 at 09:44:01PM +0800, Chun-Jie Chen wrote:
> > > This patch adds the new binding documentation for system clock
> > > and functional clock on Mediatek MT8186.
> > >
> > > Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> > > ---
> > > .../arm/mediatek/mediatek,mt8186-clock.yaml | 133
> > > ++++++++++++++++++
> > > .../mediatek/mediatek,mt8186-sys-clock.yaml | 74 ++++++++++
> > > 2 files changed, 207 insertions(+)
> > > create mode 100644
> > > Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-
> > > clock.yaml
> > > create mode 100644
> > > Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-
> > > sys-
> > > clock.yaml
> > >
> > > diff --git
> > > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-
> > > clock.yaml
> > > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-
> > > clock.yaml
> > > new file mode 100644
> > > index 000000000000..fc39101bc9b0
> > > --- /dev/null
> > > +++
> > > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-
> > > clock.yaml
> > > @@ -0,0 +1,133 @@
> > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id: "
> > >
https://urldefense.com/v3/__http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-clock.yaml*__;Iw!!CTRNKA9wMg0ARbw!3pIyNVU0grMb7zKVQZoRO2z-eKrg6FnGcieEON8cCw84G6_W7Tt4GEFwytcYEXyrcj6e$
> > > "
> > > +$schema: "
> > >
https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!3pIyNVU0grMb7zKVQZoRO2z-eKrg6FnGcieEON8cCw84G6_W7Tt4GEFwytcYEUOCCW1i$
> > > "
> > > +
> > > +title: Mediatek Functional Clock Controller for MT8186
> > > +
> > > +maintainers:
> > > + - Chun-Jie Chen <chun-jie.chen@mediatek.com>
> > > +
> > > +description:
> > > + The clock architecture in Mediatek like below
> > > + PLLs -->
> > > + dividers -->
> > > + muxes
> > > + -->
> > > + clock gate
> > > +
> > > + The devices provide clock gate control in different IP blocks.
> > > +
> > > +properties:
> > > + compatible:
> > > + items:
> > > + - enum:
> > > + - mediatek,mt8186-imp_iic_wrap
> > > + - mediatek,mt8186-mfgsys
> > > + - mediatek,mt8186-wpesys
> > > + - mediatek,mt8186-imgsys1
> > > + - mediatek,mt8186-imgsys2
> > > + - mediatek,mt8186-vdecsys
> > > + - mediatek,mt8186-vencsys
> > > + - mediatek,mt8186-camsys
> > > + - mediatek,mt8186-camsys_rawa
> > > + - mediatek,mt8186-camsys_rawb
> > > + - mediatek,mt8186-mdpsys
> > > + - mediatek,mt8186-ipesys
> > > + reg:
> > > + maxItems: 1
> > > +
> > > + '#clock-cells':
> > > + const: 1
> > > +
> > > +required:
> > > + - compatible
> > > + - reg
> > > +
> > > +additionalProperties: false
> > > +
> > > +examples:
> > > + - |
> > > + imp_iic_wrap: clock-controller@11017000 {
> > > + compatible = "mediatek,mt8186-imp_iic_wrap";
> > > + reg = <0x11017000 0x1000>;
> > > + #clock-cells = <1>;
> > > + };
> > > +
> > > + - |
> > > + mfgsys: clock-controller@13000000 {
> > > + compatible = "mediatek,mt8186-mfgsys";
> > > + reg = <0x13000000 0x1000>;
> > > + #clock-cells = <1>;
> > > + };
> > > +
> > > + - |
> > > + wpesys: clock-controller@14020000 {
> > > + compatible = "mediatek,mt8186-wpesys";
> > > + reg = <0x14020000 0x1000>;
> > > + #clock-cells = <1>;
> > > + };
> > > +
> > > + - |
> > > + imgsys1: clock-controller@15020000 {
> > > + compatible = "mediatek,mt8186-imgsys1";
> > > + reg = <0x15020000 0x1000>;
> > > + #clock-cells = <1>;
> > > + };
> > > +
> > > + - |
> > > + imgsys2: clock-controller@15820000 {
> > > + compatible = "mediatek,mt8186-imgsys2";
> > > + reg = <0x15820000 0x1000>;
> > > + #clock-cells = <1>;
> > > + };
> > > +
> > > + - |
> > > + vdecsys: clock-controller@1602f000 {
> > > + compatible = "mediatek,mt8186-vdecsys";
> > > + reg = <0x1602f000 0x1000>;
> > > + #clock-cells = <1>;
> > > + };
> > > +
> > > + - |
> > > + vencsys: clock-controller@17000000 {
> > > + compatible = "mediatek,mt8186-vencsys";
> > > + reg = <0x17000000 0x1000>;
> > > + #clock-cells = <1>;
> > > + };
> > > +
> > > + - |
> > > + camsys: clock-controller@1a000000 {
> > > + compatible = "mediatek,mt8186-camsys";
> > > + reg = <0x1a000000 0x1000>;
> > > + #clock-cells = <1>;
> > > + };
> > > +
> > > + - |
> > > + camsys_rawa: clock-controller@1a04f000 {
> > > + compatible = "mediatek,mt8186-camsys_rawa";
> > > + reg = <0x1a04f000 0x1000>;
> > > + #clock-cells = <1>;
> > > + };
> > > +
> > > + - |
> > > + camsys_rawb: clock-controller@1a06f000 {
> > > + compatible = "mediatek,mt8186-camsys_rawb";
> > > + reg = <0x1a06f000 0x1000>;
> > > + #clock-cells = <1>;
> > > + };
> > > +
> > > + - |
> > > + mdpsys: clock-controller@1b000000 {
> > > + compatible = "mediatek,mt8186-mdpsys";
> > > + reg = <0x1b000000 0x1000>;
> > > + #clock-cells = <1>;
> > > + };
> > > +
> > > + - |
> > > + ipesys: clock-controller@1c000000 {
> > > + compatible = "mediatek,mt8186-ipesys";
> > > + reg = <0x1c000000 0x1000>;
> > > + #clock-cells = <1>;
> > > + };
> >
> > There's little point in enumerating every possible compatible. 1
> > example
> > is more than enough.
> >
> >
>
> Ok, I will fix it in next patch.
>
> > > diff --git
> > > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-
> > > sys-clock.yaml
> > > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-
> > > sys-clock.yaml
> > > new file mode 100644
> > > index 000000000000..11473971a165
> > > --- /dev/null
> > > +++
> > > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-
> > > sys-clock.yaml
> > > @@ -0,0 +1,74 @@
> > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id: "
> > >
https://urldefense.com/v3/__http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-sys-clock.yaml*__;Iw!!CTRNKA9wMg0ARbw!3pIyNVU0grMb7zKVQZoRO2z-eKrg6FnGcieEON8cCw84G6_W7Tt4GEFwytcYERailYtq$
> > > "
> > > +$schema: "
> > >
https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!3pIyNVU0grMb7zKVQZoRO2z-eKrg6FnGcieEON8cCw84G6_W7Tt4GEFwytcYEUOCCW1i$
> > > "
> > > +
> > > +title: Mediatek System Clock Controller for MT8186
> > > +
> > > +maintainers:
> > > + - Chun-Jie Chen <chun-jie.chen@mediatek.com>
> > > +
> > > +description:
> > > + The clock architecture in Mediatek like below
> > > + PLLs -->
> > > + dividers -->
> > > + muxes
> > > + -->
> > > + clock gate
> > > +
> > > + The apmixedsys provides most of PLLs which generated from SoC
> > > 26m.
> > > + The topckgen provides dividers and muxes which provide the
> > > clock
> > > source to other IP blocks.
> > > + The infracfg_ao provides clock gate in peripheral and
> > > infrastructure IP blocks.
> > > + The mcusys provides mux control to select the clock source in
> > > AP
> > > MCU.
> > > +
> > > +properties:
> > > + compatible:
> > > + items:
> > > + - enum:
> > > + - mediatek,mt8186-mcusys
> > > + - mediatek,mt8186-topckgen
> > > + - mediatek,mt8186-infracfg_ao
> > > + - mediatek,mt8186-apmixedsys
> > > + - const: syscon
> > > +
> > > + reg:
> > > + maxItems: 1
> > > +
> > > + '#clock-cells':
> > > + const: 1
> > > +
> > > +required:
> > > + - compatible
> > > + - reg
> > > +
> > > +additionalProperties: false
> > > +
> > > +examples:
> > > + - |
> > > + mcusys: syscon@c53a000 {
> >
> > clock-controller@...
> >
> > Drop unused labels.
> >
>
> Ok, I will change to pure clock-controller
>
> Thanks!
> Best Regards,
> Chun-Jie
>
Please skip the reply above.
The devices in this binding document also support system configuration
not only pure clock provider, so make them as "syscon".
Thanks!
Best Regards,
Chun-Jie
> > > + compatible = "mediatek,mt8186-mcusys", "syscon";
> > > + reg = <0xc53a000 0x1000>;
> > > + #clock-cells = <1>;
> > > + };
> > > +
> > > + - |
> > > + topckgen: syscon@10000000 {
> > > + compatible = "mediatek,mt8186-topckgen", "syscon";
> > > + reg = <0x10000000 0x1000>;
> > > + #clock-cells = <1>;
> > > + };
> > > +
> > > + - |
> > > + infracfg_ao: syscon@10001000 {
> > > + compatible = "mediatek,mt8186-infracfg_ao", "syscon";
> > > + reg = <0x10001000 0x1000>;
> > > + #clock-cells = <1>;
> > > + };
> > > +
> > > + - |
> > > + apmixedsys: syscon@1000c000 {
> > > + compatible = "mediatek,mt8186-apmixedsys", "syscon";
> > > + reg = <0x1000c000 0x1000>;
> > > + #clock-cells = <1>;
> > > + };
> >
> > Again, 1 example is enough.
^ permalink raw reply [flat|nested] 39+ messages in thread
* [v1 02/16] clk: mediatek: Add dt-bindings of MT8186 clocks
[not found] <20220110134416.5191-1-chun-jie.chen@mediatek.com>
2022-01-10 13:44 ` [v1 01/16] dt-bindings: ARM: Mediatek: Add new document bindings of MT8186 clock Chun-Jie Chen
@ 2022-01-10 13:44 ` Chun-Jie Chen
2022-01-10 15:52 ` AngeloGioacchino Del Regno
2022-01-22 0:27 ` Rob Herring
2022-01-10 13:44 ` [v1 03/16] clk: mediatek: Add MT8186 mcusys clock support Chun-Jie Chen
` (13 subsequent siblings)
15 siblings, 2 replies; 39+ messages in thread
From: Chun-Jie Chen @ 2022-01-10 13:44 UTC (permalink / raw)
To: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring
Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group,
Chun-Jie Chen
Add MT8186 clock dt-bindings, includes topckgen, apmixedsys,
infracfg_ao, mcusys and subsystem clocks.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
include/dt-bindings/clock/mt8186-clk.h | 445 +++++++++++++++++++++++++
1 file changed, 445 insertions(+)
create mode 100644 include/dt-bindings/clock/mt8186-clk.h
diff --git a/include/dt-bindings/clock/mt8186-clk.h b/include/dt-bindings/clock/mt8186-clk.h
new file mode 100644
index 000000000000..6a291750cea4
--- /dev/null
+++ b/include/dt-bindings/clock/mt8186-clk.h
@@ -0,0 +1,445 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT8186_H
+#define _DT_BINDINGS_CLK_MT8186_H
+
+/* MCUSYS */
+
+#define CLK_MCU_ARMPLL_LL_SEL 0
+#define CLK_MCU_ARMPLL_BL_SEL 1
+#define CLK_MCU_ARMPLL_BUS_SEL 2
+#define CLK_MCU_NR_CLK 3
+
+/* TOPCKGEN */
+
+#define CLK_TOP_AXI 0
+#define CLK_TOP_SCP 1
+#define CLK_TOP_MFG 2
+#define CLK_TOP_CAMTG 3
+#define CLK_TOP_CAMTG1 4
+#define CLK_TOP_CAMTG2 5
+#define CLK_TOP_CAMTG3 6
+#define CLK_TOP_CAMTG4 7
+#define CLK_TOP_CAMTG5 8
+#define CLK_TOP_CAMTG6 9
+#define CLK_TOP_UART 10
+#define CLK_TOP_SPI 11
+#define CLK_TOP_MSDC50_0_HCLK 12
+#define CLK_TOP_MSDC50_0 13
+#define CLK_TOP_MSDC30_1 14
+#define CLK_TOP_AUDIO 15
+#define CLK_TOP_AUD_INTBUS 16
+#define CLK_TOP_AUD_1 17
+#define CLK_TOP_AUD_2 18
+#define CLK_TOP_AUD_ENGEN1 19
+#define CLK_TOP_AUD_ENGEN2 20
+#define CLK_TOP_DISP_PWM 21
+#define CLK_TOP_SSPM 22
+#define CLK_TOP_DXCC 23
+#define CLK_TOP_USB_TOP 24
+#define CLK_TOP_SRCK 25
+#define CLK_TOP_SPM 26
+#define CLK_TOP_I2C 27
+#define CLK_TOP_PWM 28
+#define CLK_TOP_SENINF 29
+#define CLK_TOP_SENINF1 30
+#define CLK_TOP_SENINF2 31
+#define CLK_TOP_SENINF3 32
+#define CLK_TOP_AES_MSDCFDE 33
+#define CLK_TOP_PWRAP_ULPOSC 34
+#define CLK_TOP_CAMTM 35
+#define CLK_TOP_VENC 36
+#define CLK_TOP_CAM 37
+#define CLK_TOP_IMG1 38
+#define CLK_TOP_IPE 39
+#define CLK_TOP_DPMAIF 40
+#define CLK_TOP_VDEC 41
+#define CLK_TOP_DISP 42
+#define CLK_TOP_MDP 43
+#define CLK_TOP_AUDIO_H 44
+#define CLK_TOP_UFS 45
+#define CLK_TOP_AES_FDE 46
+#define CLK_TOP_AUDIODSP 47
+#define CLK_TOP_DVFSRC 48
+#define CLK_TOP_DSI_OCC 49
+#define CLK_TOP_SPMI_MST 50
+#define CLK_TOP_SPINOR 51
+#define CLK_TOP_NNA 52
+#define CLK_TOP_NNA1 53
+#define CLK_TOP_NNA2 54
+#define CLK_TOP_SSUSB_XHCI 55
+#define CLK_TOP_SSUSB_TOP_1P 56
+#define CLK_TOP_SSUSB_XHCI_1P 57
+#define CLK_TOP_WPE 58
+#define CLK_TOP_DPI 59
+#define CLK_TOP_U3_OCC_250M 60
+#define CLK_TOP_U3_OCC_500M 61
+#define CLK_TOP_ADSP_BUS 62
+#define CLK_TOP_APLL_I2S0_MCK_SEL 63
+#define CLK_TOP_APLL_I2S1_MCK_SEL 64
+#define CLK_TOP_APLL_I2S2_MCK_SEL 65
+#define CLK_TOP_APLL_I2S4_MCK_SEL 66
+#define CLK_TOP_APLL_TDMOUT_MCK_SEL 67
+#define CLK_TOP_MAINPLL_D2 68
+#define CLK_TOP_MAINPLL_D2_D2 69
+#define CLK_TOP_MAINPLL_D2_D4 70
+#define CLK_TOP_MAINPLL_D2_D16 71
+#define CLK_TOP_MAINPLL_D3 72
+#define CLK_TOP_MAINPLL_D3_D2 73
+#define CLK_TOP_MAINPLL_D3_D4 74
+#define CLK_TOP_MAINPLL_D5 75
+#define CLK_TOP_MAINPLL_D5_D2 76
+#define CLK_TOP_MAINPLL_D5_D4 77
+#define CLK_TOP_MAINPLL_D7 78
+#define CLK_TOP_MAINPLL_D7_D2 79
+#define CLK_TOP_MAINPLL_D7_D4 80
+#define CLK_TOP_UNIVPLL 81
+#define CLK_TOP_UNIVPLL_D2 82
+#define CLK_TOP_UNIVPLL_D2_D2 83
+#define CLK_TOP_UNIVPLL_D2_D4 84
+#define CLK_TOP_UNIVPLL_D3 85
+#define CLK_TOP_UNIVPLL_D3_D2 86
+#define CLK_TOP_UNIVPLL_D3_D4 87
+#define CLK_TOP_UNIVPLL_D3_D8 88
+#define CLK_TOP_UNIVPLL_D3_D32 89
+#define CLK_TOP_UNIVPLL_D5 90
+#define CLK_TOP_UNIVPLL_D5_D2 91
+#define CLK_TOP_UNIVPLL_D5_D4 92
+#define CLK_TOP_UNIVPLL_D7 93
+#define CLK_TOP_UNIVPLL_192M 94
+#define CLK_TOP_UNIVPLL_192M_D4 95
+#define CLK_TOP_UNIVPLL_192M_D8 96
+#define CLK_TOP_UNIVPLL_192M_D16 97
+#define CLK_TOP_UNIVPLL_192M_D32 98
+#define CLK_TOP_APLL1_D2 99
+#define CLK_TOP_APLL1_D4 100
+#define CLK_TOP_APLL1_D8 101
+#define CLK_TOP_APLL2_D2 102
+#define CLK_TOP_APLL2_D4 103
+#define CLK_TOP_APLL2_D8 104
+#define CLK_TOP_MMPLL_D2 105
+#define CLK_TOP_TVDPLL_D2 106
+#define CLK_TOP_TVDPLL_D4 107
+#define CLK_TOP_TVDPLL_D8 108
+#define CLK_TOP_TVDPLL_D16 109
+#define CLK_TOP_TVDPLL_D32 110
+#define CLK_TOP_MSDCPLL_D2 111
+#define CLK_TOP_ULPOSC1 112
+#define CLK_TOP_ULPOSC1_D2 113
+#define CLK_TOP_ULPOSC1_D4 114
+#define CLK_TOP_ULPOSC1_D8 115
+#define CLK_TOP_ULPOSC1_D10 116
+#define CLK_TOP_ULPOSC1_D16 117
+#define CLK_TOP_ULPOSC1_D32 118
+#define CLK_TOP_ADSPPLL_D2 119
+#define CLK_TOP_ADSPPLL_D4 120
+#define CLK_TOP_ADSPPLL_D8 121
+#define CLK_TOP_NNAPLL_D2 122
+#define CLK_TOP_NNAPLL_D4 123
+#define CLK_TOP_NNAPLL_D8 124
+#define CLK_TOP_NNA2PLL_D2 125
+#define CLK_TOP_NNA2PLL_D4 126
+#define CLK_TOP_NNA2PLL_D8 127
+#define CLK_TOP_F_BIST2FPC 128
+#define CLK_TOP_466M_FMEM 129
+#define CLK_TOP_MPLL 130
+#define CLK_TOP_APLL12_CK_DIV0 131
+#define CLK_TOP_APLL12_CK_DIV1 132
+#define CLK_TOP_APLL12_CK_DIV2 133
+#define CLK_TOP_APLL12_CK_DIV4 134
+#define CLK_TOP_APLL12_CK_DIV_TDMOUT_M 135
+#define CLK_TOP_NR_CLK 136
+
+/* INFRACFG_AO */
+
+#define CLK_INFRA_AO_PMIC_TMR 0
+#define CLK_INFRA_AO_PMIC_AP 1
+#define CLK_INFRA_AO_PMIC_MD 2
+#define CLK_INFRA_AO_PMIC_CONN 3
+#define CLK_INFRA_AO_SCP_CORE 4
+#define CLK_INFRA_AO_SEJ 5
+#define CLK_INFRA_AO_APXGPT 6
+#define CLK_INFRA_AO_ICUSB 7
+#define CLK_INFRA_AO_GCE 8
+#define CLK_INFRA_AO_THERM 9
+#define CLK_INFRA_AO_I2C_AP 10
+#define CLK_INFRA_AO_I2C_CCU 11
+#define CLK_INFRA_AO_I2C_SSPM 12
+#define CLK_INFRA_AO_I2C_RSV 13
+#define CLK_INFRA_AO_PWM_HCLK 14
+#define CLK_INFRA_AO_PWM1 15
+#define CLK_INFRA_AO_PWM2 16
+#define CLK_INFRA_AO_PWM3 17
+#define CLK_INFRA_AO_PWM4 18
+#define CLK_INFRA_AO_PWM5 19
+#define CLK_INFRA_AO_PWM 20
+#define CLK_INFRA_AO_UART0 21
+#define CLK_INFRA_AO_UART1 22
+#define CLK_INFRA_AO_UART2 23
+#define CLK_INFRA_AO_GCE_26M 24
+#define CLK_INFRA_AO_CQ_DMA_FPC 25
+#define CLK_INFRA_AO_BTIF 26
+#define CLK_INFRA_AO_SPI0 27
+#define CLK_INFRA_AO_MSDC0 28
+#define CLK_INFRA_AO_MSDCFDE 29
+#define CLK_INFRA_AO_MSDC1 30
+#define CLK_INFRA_AO_DVFSRC 31
+#define CLK_INFRA_AO_GCPU 32
+#define CLK_INFRA_AO_TRNG 33
+#define CLK_INFRA_AO_AUXADC 34
+#define CLK_INFRA_AO_CPUM 35
+#define CLK_INFRA_AO_CCIF1_AP 36
+#define CLK_INFRA_AO_CCIF1_MD 37
+#define CLK_INFRA_AO_AUXADC_MD 38
+#define CLK_INFRA_AO_AP_DMA 39
+#define CLK_INFRA_AO_XIU 40
+#define CLK_INFRA_AO_DEVICE_APC 41
+#define CLK_INFRA_AO_CCIF_AP 42
+#define CLK_INFRA_AO_DEBUGTOP 43
+#define CLK_INFRA_AO_AUDIO 44
+#define CLK_INFRA_AO_CCIF_MD 45
+#define CLK_INFRA_AO_DXCC_SEC_CORE 46
+#define CLK_INFRA_AO_DXCC_AO 47
+#define CLK_INFRA_AO_IMP_IIC 48
+#define CLK_INFRA_AO_DRAMC_F26M 49
+#define CLK_INFRA_AO_RG_PWM_FBCLK6 50
+#define CLK_INFRA_AO_SSUSB_TOP_HCLK 51
+#define CLK_INFRA_AO_DISP_PWM 52
+#define CLK_INFRA_AO_CLDMA_BCLK 53
+#define CLK_INFRA_AO_AUDIO_26M_BCLK 54
+#define CLK_INFRA_AO_SSUSB_TOP_P1_HCLK 55
+#define CLK_INFRA_AO_SPI1 56
+#define CLK_INFRA_AO_I2C4 57
+#define CLK_INFRA_AO_MODEM_TEMP_SHARE 58
+#define CLK_INFRA_AO_SPI2 59
+#define CLK_INFRA_AO_SPI3 60
+#define CLK_INFRA_AO_SSUSB_TOP_REF 61
+#define CLK_INFRA_AO_SSUSB_TOP_XHCI 62
+#define CLK_INFRA_AO_SSUSB_TOP_P1_REF 63
+#define CLK_INFRA_AO_SSUSB_TOP_P1_XHCI 64
+#define CLK_INFRA_AO_SSPM 65
+#define CLK_INFRA_AO_SSUSB_TOP_P1_SYS 66
+#define CLK_INFRA_AO_I2C5 67
+#define CLK_INFRA_AO_I2C5_ARBITER 68
+#define CLK_INFRA_AO_I2C5_IMM 69
+#define CLK_INFRA_AO_I2C1_ARBITER 70
+#define CLK_INFRA_AO_I2C1_IMM 71
+#define CLK_INFRA_AO_I2C2_ARBITER 72
+#define CLK_INFRA_AO_I2C2_IMM 73
+#define CLK_INFRA_AO_SPI4 74
+#define CLK_INFRA_AO_SPI5 75
+#define CLK_INFRA_AO_CQ_DMA 76
+#define CLK_INFRA_AO_BIST2FPC 77
+#define CLK_INFRA_AO_MSDC0_SELF 78
+#define CLK_INFRA_AO_SPINOR 79
+#define CLK_INFRA_AO_SSPM_26M_SELF 80
+#define CLK_INFRA_AO_SSPM_32K_SELF 81
+#define CLK_INFRA_AO_I2C6 82
+#define CLK_INFRA_AO_AP_MSDC0 83
+#define CLK_INFRA_AO_MD_MSDC0 84
+#define CLK_INFRA_AO_MSDC0_SRC 85
+#define CLK_INFRA_AO_MSDC1_SRC 86
+#define CLK_INFRA_AO_SEJ_F13M 87
+#define CLK_INFRA_AO_AES_TOP0_BCLK 88
+#define CLK_INFRA_AO_MCU_PM_BCLK 89
+#define CLK_INFRA_AO_CCIF2_AP 90
+#define CLK_INFRA_AO_CCIF2_MD 91
+#define CLK_INFRA_AO_CCIF3_AP 92
+#define CLK_INFRA_AO_CCIF3_MD 93
+#define CLK_INFRA_AO_FADSP_26M 94
+#define CLK_INFRA_AO_FADSP_32K 95
+#define CLK_INFRA_AO_CCIF4_AP 96
+#define CLK_INFRA_AO_CCIF4_MD 97
+#define CLK_INFRA_AO_FADSP 98
+#define CLK_INFRA_AO_FLASHIF_133M 99
+#define CLK_INFRA_AO_FLASHIF_66M 100
+#define CLK_INFRA_AO_NR_CLK 101
+
+/* APMIXEDSYS */
+
+#define CLK_APMIXED_ARMPLL_LL 0
+#define CLK_APMIXED_ARMPLL_BL 1
+#define CLK_APMIXED_CCIPLL 2
+#define CLK_APMIXED_MAINPLL 3
+#define CLK_APMIXED_UNIV2PLL 4
+#define CLK_APMIXED_MSDCPLL 5
+#define CLK_APMIXED_MMPLL 6
+#define CLK_APMIXED_NNAPLL 7
+#define CLK_APMIXED_NNA2PLL 8
+#define CLK_APMIXED_ADSPPLL 9
+#define CLK_APMIXED_MFGPLL 10
+#define CLK_APMIXED_TVDPLL 11
+#define CLK_APMIXED_APLL1 12
+#define CLK_APMIXED_APLL2 13
+#define CLK_APMIXED_NR_CLK 14
+
+/* IMP_IIC_WRAP */
+
+#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0 0
+#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1 1
+#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2 2
+#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3 3
+#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4 4
+#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5 5
+#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6 6
+#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7 7
+#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8 8
+#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9 9
+#define CLK_IMP_IIC_WRAP_NR_CLK 10
+
+/* MFGCFG */
+
+#define CLK_MFG_BG3D 0
+#define CLK_MFG_NR_CLK 1
+
+/* MMSYS */
+
+#define CLK_MM_DISP_MUTEX0 0
+#define CLK_MM_APB_MM_BUS 1
+#define CLK_MM_DISP_OVL0 2
+#define CLK_MM_DISP_RDMA0 3
+#define CLK_MM_DISP_OVL0_2L 4
+#define CLK_MM_DISP_WDMA0 5
+#define CLK_MM_DISP_RSZ0 6
+#define CLK_MM_DISP_AAL0 7
+#define CLK_MM_DISP_CCORR0 8
+#define CLK_MM_DISP_COLOR0 9
+#define CLK_MM_SMI_INFRA 10
+#define CLK_MM_DISP_DSC_WRAP0 11
+#define CLK_MM_DISP_GAMMA0 12
+#define CLK_MM_DISP_POSTMASK0 13
+#define CLK_MM_DISP_DITHER0 14
+#define CLK_MM_SMI_COMMON 15
+#define CLK_MM_DSI0 16
+#define CLK_MM_DISP_FAKE_ENG0 17
+#define CLK_MM_DISP_FAKE_ENG1 18
+#define CLK_MM_SMI_GALS 19
+#define CLK_MM_SMI_IOMMU 20
+#define CLK_MM_DISP_RDMA1 21
+#define CLK_MM_DISP_DPI 22
+#define CLK_MM_DSI0_DSI_CK_DOMAIN 23
+#define CLK_MM_DISP_26M 24
+#define CLK_MM_NR_CLK 25
+
+/* WPESYS */
+
+#define CLK_WPE_CK_EN 0
+#define CLK_WPE_SMI_LARB8_CK_EN 1
+#define CLK_WPE_SYS_EVENT_TX_CK_EN 2
+#define CLK_WPE_SMI_LARB8_PCLK_EN 3
+#define CLK_WPE_NR_CLK 4
+
+/* IMGSYS1 */
+
+#define CLK_IMG1_LARB9_IMG1 0
+#define CLK_IMG1_LARB10_IMG1 1
+#define CLK_IMG1_DIP 2
+#define CLK_IMG1_GALS_IMG1 3
+#define CLK_IMG1_NR_CLK 4
+
+/* IMGSYS2 */
+
+#define CLK_IMG2_LARB9_IMG2 0
+#define CLK_IMG2_LARB10_IMG2 1
+#define CLK_IMG2_MFB 2
+#define CLK_IMG2_WPE 3
+#define CLK_IMG2_MSS 4
+#define CLK_IMG2_GALS_IMG2 5
+#define CLK_IMG2_NR_CLK 6
+
+/* VDECSYS */
+
+#define CLK_VDEC_LARB1_CKEN 0
+#define CLK_VDEC_LAT_CKEN 1
+#define CLK_VDEC_LAT_ACTIVE 2
+#define CLK_VDEC_LAT_CKEN_ENG 3
+#define CLK_VDEC_MINI_MDP_CKEN_CFG_RG 4
+#define CLK_VDEC_CKEN 5
+#define CLK_VDEC_ACTIVE 6
+#define CLK_VDEC_CKEN_ENG 7
+#define CLK_VDEC_NR_CLK 8
+
+/* VENCSYS */
+
+#define CLK_VENC_CKE0_LARB 0
+#define CLK_VENC_CKE1_VENC 1
+#define CLK_VENC_CKE2_JPGENC 2
+#define CLK_VENC_CKE5_GALS 3
+#define CLK_VENC_NR_CLK 4
+
+/* CAMSYS */
+
+#define CLK_CAM_LARB13 0
+#define CLK_CAM_DFP_VAD 1
+#define CLK_CAM_LARB14 2
+#define CLK_CAM 3
+#define CLK_CAMTG 4
+#define CLK_CAM_SENINF 5
+#define CLK_CAMSV1 6
+#define CLK_CAMSV2 7
+#define CLK_CAMSV3 8
+#define CLK_CAM_CCU0 9
+#define CLK_CAM_CCU1 10
+#define CLK_CAM_MRAW0 11
+#define CLK_CAM_FAKE_ENG 12
+#define CLK_CAM_CCU_GALS 13
+#define CLK_CAM2MM_GALS 14
+#define CLK_CAM_NR_CLK 15
+
+/* CAMSYS_RAWA */
+
+#define CLK_CAM_RAWA_LARBX_RAWA 0
+#define CLK_CAM_RAWA 1
+#define CLK_CAM_RAWA_CAMTG_RAWA 2
+#define CLK_CAM_RAWA_NR_CLK 3
+
+/* CAMSYS_RAWB */
+
+#define CLK_CAM_RAWB_LARBX_RAWB 0
+#define CLK_CAM_RAWB 1
+#define CLK_CAM_RAWB_CAMTG_RAWB 2
+#define CLK_CAM_RAWB_NR_CLK 3
+
+/* MDPSYS */
+
+#define CLK_MDP_RDMA0 0
+#define CLK_MDP_TDSHP0 1
+#define CLK_MDP_IMG_DL_ASYNC0 2
+#define CLK_MDP_IMG_DL_ASYNC1 3
+#define CLK_MDP_DISP_RDMA 4
+#define CLK_MDP_HMS 5
+#define CLK_MDP_SMI0 6
+#define CLK_MDP_APB_BUS 7
+#define CLK_MDP_WROT0 8
+#define CLK_MDP_RSZ0 9
+#define CLK_MDP_HDR0 10
+#define CLK_MDP_MUTEX0 11
+#define CLK_MDP_WROT1 12
+#define CLK_MDP_RSZ1 13
+#define CLK_MDP_FAKE_ENG0 14
+#define CLK_MDP_AAL0 15
+#define CLK_MDP_DISP_WDMA 16
+#define CLK_MDP_COLOR 17
+#define CLK_MDP_IMG_DL_ASYNC2 18
+#define CLK_MDP_IMG_DL_RELAY0_ASYNC0 19
+#define CLK_MDP_IMG_DL_RELAY1_ASYNC1 20
+#define CLK_MDP_IMG_DL_RELAY2_ASYNC2 21
+#define CLK_MDP_NR_CLK 22
+
+/* IPESYS */
+
+#define CLK_IPE_LARB19 0
+#define CLK_IPE_LARB20 1
+#define CLK_IPE_SMI_SUBCOM 2
+#define CLK_IPE_FD 3
+#define CLK_IPE_FE 4
+#define CLK_IPE_RSC 5
+#define CLK_IPE_DPE 6
+#define CLK_IPE_GALS_IPE 7
+#define CLK_IPE_NR_CLK 8
+
+#endif /* _DT_BINDINGS_CLK_MT8186_H */
--
2.18.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [v1 02/16] clk: mediatek: Add dt-bindings of MT8186 clocks
2022-01-10 13:44 ` [v1 02/16] clk: mediatek: Add dt-bindings of MT8186 clocks Chun-Jie Chen
@ 2022-01-10 15:52 ` AngeloGioacchino Del Regno
2022-01-22 0:27 ` Rob Herring
1 sibling, 0 replies; 39+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-01-10 15:52 UTC (permalink / raw)
To: Chun-Jie Chen, Matthias Brugger, Stephen Boyd, Nicolas Boichat,
Rob Herring
Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group
Il 10/01/22 14:44, Chun-Jie Chen ha scritto:
> Add MT8186 clock dt-bindings, includes topckgen, apmixedsys,
> infracfg_ao, mcusys and subsystem clocks.
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Hello Chun-Jie,
I think that this patch should be squashed with patch 01/16, as this
is dt-bindings as much as the yaml that you're introducing.
Regards,
- Angelo
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [v1 02/16] clk: mediatek: Add dt-bindings of MT8186 clocks
2022-01-10 13:44 ` [v1 02/16] clk: mediatek: Add dt-bindings of MT8186 clocks Chun-Jie Chen
2022-01-10 15:52 ` AngeloGioacchino Del Regno
@ 2022-01-22 0:27 ` Rob Herring
2022-02-09 1:43 ` Chun-Jie Chen
1 sibling, 1 reply; 39+ messages in thread
From: Rob Herring @ 2022-01-22 0:27 UTC (permalink / raw)
To: Chun-Jie Chen
Cc: Matthias Brugger, Stephen Boyd, Nicolas Boichat,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group
On Mon, Jan 10, 2022 at 09:44:02PM +0800, Chun-Jie Chen wrote:
> Add MT8186 clock dt-bindings, includes topckgen, apmixedsys,
> infracfg_ao, mcusys and subsystem clocks.
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> ---
> include/dt-bindings/clock/mt8186-clk.h | 445 +++++++++++++++++++++++++
> 1 file changed, 445 insertions(+)
> create mode 100644 include/dt-bindings/clock/mt8186-clk.h
As mentioned, squash with patch 1.
>
> diff --git a/include/dt-bindings/clock/mt8186-clk.h b/include/dt-bindings/clock/mt8186-clk.h
> new file mode 100644
> index 000000000000..6a291750cea4
> --- /dev/null
> +++ b/include/dt-bindings/clock/mt8186-clk.h
> @@ -0,0 +1,445 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
Dual license please.
> +/*
> + * Copyright (c) 2022 MediaTek Inc.
> + * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_MT8186_H
> +#define _DT_BINDINGS_CLK_MT8186_H
> +
> +/* MCUSYS */
> +
> +#define CLK_MCU_ARMPLL_LL_SEL 0
> +#define CLK_MCU_ARMPLL_BL_SEL 1
> +#define CLK_MCU_ARMPLL_BUS_SEL 2
> +#define CLK_MCU_NR_CLK 3
> +
> +/* TOPCKGEN */
> +
> +#define CLK_TOP_AXI 0
> +#define CLK_TOP_SCP 1
> +#define CLK_TOP_MFG 2
> +#define CLK_TOP_CAMTG 3
> +#define CLK_TOP_CAMTG1 4
> +#define CLK_TOP_CAMTG2 5
> +#define CLK_TOP_CAMTG3 6
> +#define CLK_TOP_CAMTG4 7
> +#define CLK_TOP_CAMTG5 8
> +#define CLK_TOP_CAMTG6 9
> +#define CLK_TOP_UART 10
> +#define CLK_TOP_SPI 11
> +#define CLK_TOP_MSDC50_0_HCLK 12
> +#define CLK_TOP_MSDC50_0 13
> +#define CLK_TOP_MSDC30_1 14
> +#define CLK_TOP_AUDIO 15
> +#define CLK_TOP_AUD_INTBUS 16
> +#define CLK_TOP_AUD_1 17
> +#define CLK_TOP_AUD_2 18
> +#define CLK_TOP_AUD_ENGEN1 19
> +#define CLK_TOP_AUD_ENGEN2 20
> +#define CLK_TOP_DISP_PWM 21
> +#define CLK_TOP_SSPM 22
> +#define CLK_TOP_DXCC 23
> +#define CLK_TOP_USB_TOP 24
> +#define CLK_TOP_SRCK 25
> +#define CLK_TOP_SPM 26
> +#define CLK_TOP_I2C 27
> +#define CLK_TOP_PWM 28
> +#define CLK_TOP_SENINF 29
> +#define CLK_TOP_SENINF1 30
> +#define CLK_TOP_SENINF2 31
> +#define CLK_TOP_SENINF3 32
> +#define CLK_TOP_AES_MSDCFDE 33
> +#define CLK_TOP_PWRAP_ULPOSC 34
> +#define CLK_TOP_CAMTM 35
> +#define CLK_TOP_VENC 36
> +#define CLK_TOP_CAM 37
> +#define CLK_TOP_IMG1 38
> +#define CLK_TOP_IPE 39
> +#define CLK_TOP_DPMAIF 40
> +#define CLK_TOP_VDEC 41
> +#define CLK_TOP_DISP 42
> +#define CLK_TOP_MDP 43
> +#define CLK_TOP_AUDIO_H 44
> +#define CLK_TOP_UFS 45
> +#define CLK_TOP_AES_FDE 46
> +#define CLK_TOP_AUDIODSP 47
> +#define CLK_TOP_DVFSRC 48
> +#define CLK_TOP_DSI_OCC 49
> +#define CLK_TOP_SPMI_MST 50
> +#define CLK_TOP_SPINOR 51
> +#define CLK_TOP_NNA 52
> +#define CLK_TOP_NNA1 53
> +#define CLK_TOP_NNA2 54
> +#define CLK_TOP_SSUSB_XHCI 55
> +#define CLK_TOP_SSUSB_TOP_1P 56
> +#define CLK_TOP_SSUSB_XHCI_1P 57
> +#define CLK_TOP_WPE 58
> +#define CLK_TOP_DPI 59
> +#define CLK_TOP_U3_OCC_250M 60
> +#define CLK_TOP_U3_OCC_500M 61
> +#define CLK_TOP_ADSP_BUS 62
> +#define CLK_TOP_APLL_I2S0_MCK_SEL 63
> +#define CLK_TOP_APLL_I2S1_MCK_SEL 64
> +#define CLK_TOP_APLL_I2S2_MCK_SEL 65
> +#define CLK_TOP_APLL_I2S4_MCK_SEL 66
> +#define CLK_TOP_APLL_TDMOUT_MCK_SEL 67
> +#define CLK_TOP_MAINPLL_D2 68
> +#define CLK_TOP_MAINPLL_D2_D2 69
> +#define CLK_TOP_MAINPLL_D2_D4 70
> +#define CLK_TOP_MAINPLL_D2_D16 71
> +#define CLK_TOP_MAINPLL_D3 72
> +#define CLK_TOP_MAINPLL_D3_D2 73
> +#define CLK_TOP_MAINPLL_D3_D4 74
> +#define CLK_TOP_MAINPLL_D5 75
> +#define CLK_TOP_MAINPLL_D5_D2 76
> +#define CLK_TOP_MAINPLL_D5_D4 77
> +#define CLK_TOP_MAINPLL_D7 78
> +#define CLK_TOP_MAINPLL_D7_D2 79
> +#define CLK_TOP_MAINPLL_D7_D4 80
> +#define CLK_TOP_UNIVPLL 81
> +#define CLK_TOP_UNIVPLL_D2 82
> +#define CLK_TOP_UNIVPLL_D2_D2 83
> +#define CLK_TOP_UNIVPLL_D2_D4 84
> +#define CLK_TOP_UNIVPLL_D3 85
> +#define CLK_TOP_UNIVPLL_D3_D2 86
> +#define CLK_TOP_UNIVPLL_D3_D4 87
> +#define CLK_TOP_UNIVPLL_D3_D8 88
> +#define CLK_TOP_UNIVPLL_D3_D32 89
> +#define CLK_TOP_UNIVPLL_D5 90
> +#define CLK_TOP_UNIVPLL_D5_D2 91
> +#define CLK_TOP_UNIVPLL_D5_D4 92
> +#define CLK_TOP_UNIVPLL_D7 93
> +#define CLK_TOP_UNIVPLL_192M 94
> +#define CLK_TOP_UNIVPLL_192M_D4 95
> +#define CLK_TOP_UNIVPLL_192M_D8 96
> +#define CLK_TOP_UNIVPLL_192M_D16 97
> +#define CLK_TOP_UNIVPLL_192M_D32 98
> +#define CLK_TOP_APLL1_D2 99
> +#define CLK_TOP_APLL1_D4 100
> +#define CLK_TOP_APLL1_D8 101
> +#define CLK_TOP_APLL2_D2 102
> +#define CLK_TOP_APLL2_D4 103
> +#define CLK_TOP_APLL2_D8 104
> +#define CLK_TOP_MMPLL_D2 105
> +#define CLK_TOP_TVDPLL_D2 106
> +#define CLK_TOP_TVDPLL_D4 107
> +#define CLK_TOP_TVDPLL_D8 108
> +#define CLK_TOP_TVDPLL_D16 109
> +#define CLK_TOP_TVDPLL_D32 110
> +#define CLK_TOP_MSDCPLL_D2 111
> +#define CLK_TOP_ULPOSC1 112
> +#define CLK_TOP_ULPOSC1_D2 113
> +#define CLK_TOP_ULPOSC1_D4 114
> +#define CLK_TOP_ULPOSC1_D8 115
> +#define CLK_TOP_ULPOSC1_D10 116
> +#define CLK_TOP_ULPOSC1_D16 117
> +#define CLK_TOP_ULPOSC1_D32 118
> +#define CLK_TOP_ADSPPLL_D2 119
> +#define CLK_TOP_ADSPPLL_D4 120
> +#define CLK_TOP_ADSPPLL_D8 121
> +#define CLK_TOP_NNAPLL_D2 122
> +#define CLK_TOP_NNAPLL_D4 123
> +#define CLK_TOP_NNAPLL_D8 124
> +#define CLK_TOP_NNA2PLL_D2 125
> +#define CLK_TOP_NNA2PLL_D4 126
> +#define CLK_TOP_NNA2PLL_D8 127
> +#define CLK_TOP_F_BIST2FPC 128
> +#define CLK_TOP_466M_FMEM 129
> +#define CLK_TOP_MPLL 130
> +#define CLK_TOP_APLL12_CK_DIV0 131
> +#define CLK_TOP_APLL12_CK_DIV1 132
> +#define CLK_TOP_APLL12_CK_DIV2 133
> +#define CLK_TOP_APLL12_CK_DIV4 134
> +#define CLK_TOP_APLL12_CK_DIV_TDMOUT_M 135
> +#define CLK_TOP_NR_CLK 136
> +
> +/* INFRACFG_AO */
> +
> +#define CLK_INFRA_AO_PMIC_TMR 0
> +#define CLK_INFRA_AO_PMIC_AP 1
> +#define CLK_INFRA_AO_PMIC_MD 2
> +#define CLK_INFRA_AO_PMIC_CONN 3
> +#define CLK_INFRA_AO_SCP_CORE 4
> +#define CLK_INFRA_AO_SEJ 5
> +#define CLK_INFRA_AO_APXGPT 6
> +#define CLK_INFRA_AO_ICUSB 7
> +#define CLK_INFRA_AO_GCE 8
> +#define CLK_INFRA_AO_THERM 9
> +#define CLK_INFRA_AO_I2C_AP 10
> +#define CLK_INFRA_AO_I2C_CCU 11
> +#define CLK_INFRA_AO_I2C_SSPM 12
> +#define CLK_INFRA_AO_I2C_RSV 13
> +#define CLK_INFRA_AO_PWM_HCLK 14
> +#define CLK_INFRA_AO_PWM1 15
> +#define CLK_INFRA_AO_PWM2 16
> +#define CLK_INFRA_AO_PWM3 17
> +#define CLK_INFRA_AO_PWM4 18
> +#define CLK_INFRA_AO_PWM5 19
> +#define CLK_INFRA_AO_PWM 20
> +#define CLK_INFRA_AO_UART0 21
> +#define CLK_INFRA_AO_UART1 22
> +#define CLK_INFRA_AO_UART2 23
> +#define CLK_INFRA_AO_GCE_26M 24
> +#define CLK_INFRA_AO_CQ_DMA_FPC 25
> +#define CLK_INFRA_AO_BTIF 26
> +#define CLK_INFRA_AO_SPI0 27
> +#define CLK_INFRA_AO_MSDC0 28
> +#define CLK_INFRA_AO_MSDCFDE 29
> +#define CLK_INFRA_AO_MSDC1 30
> +#define CLK_INFRA_AO_DVFSRC 31
> +#define CLK_INFRA_AO_GCPU 32
> +#define CLK_INFRA_AO_TRNG 33
> +#define CLK_INFRA_AO_AUXADC 34
> +#define CLK_INFRA_AO_CPUM 35
> +#define CLK_INFRA_AO_CCIF1_AP 36
> +#define CLK_INFRA_AO_CCIF1_MD 37
> +#define CLK_INFRA_AO_AUXADC_MD 38
> +#define CLK_INFRA_AO_AP_DMA 39
> +#define CLK_INFRA_AO_XIU 40
> +#define CLK_INFRA_AO_DEVICE_APC 41
> +#define CLK_INFRA_AO_CCIF_AP 42
> +#define CLK_INFRA_AO_DEBUGTOP 43
> +#define CLK_INFRA_AO_AUDIO 44
> +#define CLK_INFRA_AO_CCIF_MD 45
> +#define CLK_INFRA_AO_DXCC_SEC_CORE 46
> +#define CLK_INFRA_AO_DXCC_AO 47
> +#define CLK_INFRA_AO_IMP_IIC 48
> +#define CLK_INFRA_AO_DRAMC_F26M 49
> +#define CLK_INFRA_AO_RG_PWM_FBCLK6 50
> +#define CLK_INFRA_AO_SSUSB_TOP_HCLK 51
> +#define CLK_INFRA_AO_DISP_PWM 52
> +#define CLK_INFRA_AO_CLDMA_BCLK 53
> +#define CLK_INFRA_AO_AUDIO_26M_BCLK 54
> +#define CLK_INFRA_AO_SSUSB_TOP_P1_HCLK 55
> +#define CLK_INFRA_AO_SPI1 56
> +#define CLK_INFRA_AO_I2C4 57
> +#define CLK_INFRA_AO_MODEM_TEMP_SHARE 58
> +#define CLK_INFRA_AO_SPI2 59
> +#define CLK_INFRA_AO_SPI3 60
> +#define CLK_INFRA_AO_SSUSB_TOP_REF 61
> +#define CLK_INFRA_AO_SSUSB_TOP_XHCI 62
> +#define CLK_INFRA_AO_SSUSB_TOP_P1_REF 63
> +#define CLK_INFRA_AO_SSUSB_TOP_P1_XHCI 64
> +#define CLK_INFRA_AO_SSPM 65
> +#define CLK_INFRA_AO_SSUSB_TOP_P1_SYS 66
> +#define CLK_INFRA_AO_I2C5 67
> +#define CLK_INFRA_AO_I2C5_ARBITER 68
> +#define CLK_INFRA_AO_I2C5_IMM 69
> +#define CLK_INFRA_AO_I2C1_ARBITER 70
> +#define CLK_INFRA_AO_I2C1_IMM 71
> +#define CLK_INFRA_AO_I2C2_ARBITER 72
> +#define CLK_INFRA_AO_I2C2_IMM 73
> +#define CLK_INFRA_AO_SPI4 74
> +#define CLK_INFRA_AO_SPI5 75
> +#define CLK_INFRA_AO_CQ_DMA 76
> +#define CLK_INFRA_AO_BIST2FPC 77
> +#define CLK_INFRA_AO_MSDC0_SELF 78
> +#define CLK_INFRA_AO_SPINOR 79
> +#define CLK_INFRA_AO_SSPM_26M_SELF 80
> +#define CLK_INFRA_AO_SSPM_32K_SELF 81
> +#define CLK_INFRA_AO_I2C6 82
> +#define CLK_INFRA_AO_AP_MSDC0 83
> +#define CLK_INFRA_AO_MD_MSDC0 84
> +#define CLK_INFRA_AO_MSDC0_SRC 85
> +#define CLK_INFRA_AO_MSDC1_SRC 86
> +#define CLK_INFRA_AO_SEJ_F13M 87
> +#define CLK_INFRA_AO_AES_TOP0_BCLK 88
> +#define CLK_INFRA_AO_MCU_PM_BCLK 89
> +#define CLK_INFRA_AO_CCIF2_AP 90
> +#define CLK_INFRA_AO_CCIF2_MD 91
> +#define CLK_INFRA_AO_CCIF3_AP 92
> +#define CLK_INFRA_AO_CCIF3_MD 93
> +#define CLK_INFRA_AO_FADSP_26M 94
> +#define CLK_INFRA_AO_FADSP_32K 95
> +#define CLK_INFRA_AO_CCIF4_AP 96
> +#define CLK_INFRA_AO_CCIF4_MD 97
> +#define CLK_INFRA_AO_FADSP 98
> +#define CLK_INFRA_AO_FLASHIF_133M 99
> +#define CLK_INFRA_AO_FLASHIF_66M 100
> +#define CLK_INFRA_AO_NR_CLK 101
> +
> +/* APMIXEDSYS */
> +
> +#define CLK_APMIXED_ARMPLL_LL 0
> +#define CLK_APMIXED_ARMPLL_BL 1
> +#define CLK_APMIXED_CCIPLL 2
> +#define CLK_APMIXED_MAINPLL 3
> +#define CLK_APMIXED_UNIV2PLL 4
> +#define CLK_APMIXED_MSDCPLL 5
> +#define CLK_APMIXED_MMPLL 6
> +#define CLK_APMIXED_NNAPLL 7
> +#define CLK_APMIXED_NNA2PLL 8
> +#define CLK_APMIXED_ADSPPLL 9
> +#define CLK_APMIXED_MFGPLL 10
> +#define CLK_APMIXED_TVDPLL 11
> +#define CLK_APMIXED_APLL1 12
> +#define CLK_APMIXED_APLL2 13
> +#define CLK_APMIXED_NR_CLK 14
> +
> +/* IMP_IIC_WRAP */
> +
> +#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0 0
> +#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1 1
> +#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2 2
> +#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3 3
> +#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4 4
> +#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5 5
> +#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6 6
> +#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7 7
> +#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8 8
> +#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9 9
> +#define CLK_IMP_IIC_WRAP_NR_CLK 10
> +
> +/* MFGCFG */
> +
> +#define CLK_MFG_BG3D 0
> +#define CLK_MFG_NR_CLK 1
> +
> +/* MMSYS */
> +
> +#define CLK_MM_DISP_MUTEX0 0
> +#define CLK_MM_APB_MM_BUS 1
> +#define CLK_MM_DISP_OVL0 2
> +#define CLK_MM_DISP_RDMA0 3
> +#define CLK_MM_DISP_OVL0_2L 4
> +#define CLK_MM_DISP_WDMA0 5
> +#define CLK_MM_DISP_RSZ0 6
> +#define CLK_MM_DISP_AAL0 7
> +#define CLK_MM_DISP_CCORR0 8
> +#define CLK_MM_DISP_COLOR0 9
> +#define CLK_MM_SMI_INFRA 10
> +#define CLK_MM_DISP_DSC_WRAP0 11
> +#define CLK_MM_DISP_GAMMA0 12
> +#define CLK_MM_DISP_POSTMASK0 13
> +#define CLK_MM_DISP_DITHER0 14
> +#define CLK_MM_SMI_COMMON 15
> +#define CLK_MM_DSI0 16
> +#define CLK_MM_DISP_FAKE_ENG0 17
> +#define CLK_MM_DISP_FAKE_ENG1 18
> +#define CLK_MM_SMI_GALS 19
> +#define CLK_MM_SMI_IOMMU 20
> +#define CLK_MM_DISP_RDMA1 21
> +#define CLK_MM_DISP_DPI 22
> +#define CLK_MM_DSI0_DSI_CK_DOMAIN 23
> +#define CLK_MM_DISP_26M 24
> +#define CLK_MM_NR_CLK 25
> +
> +/* WPESYS */
> +
> +#define CLK_WPE_CK_EN 0
> +#define CLK_WPE_SMI_LARB8_CK_EN 1
> +#define CLK_WPE_SYS_EVENT_TX_CK_EN 2
> +#define CLK_WPE_SMI_LARB8_PCLK_EN 3
> +#define CLK_WPE_NR_CLK 4
> +
> +/* IMGSYS1 */
> +
> +#define CLK_IMG1_LARB9_IMG1 0
> +#define CLK_IMG1_LARB10_IMG1 1
> +#define CLK_IMG1_DIP 2
> +#define CLK_IMG1_GALS_IMG1 3
> +#define CLK_IMG1_NR_CLK 4
> +
> +/* IMGSYS2 */
> +
> +#define CLK_IMG2_LARB9_IMG2 0
> +#define CLK_IMG2_LARB10_IMG2 1
> +#define CLK_IMG2_MFB 2
> +#define CLK_IMG2_WPE 3
> +#define CLK_IMG2_MSS 4
> +#define CLK_IMG2_GALS_IMG2 5
> +#define CLK_IMG2_NR_CLK 6
> +
> +/* VDECSYS */
> +
> +#define CLK_VDEC_LARB1_CKEN 0
> +#define CLK_VDEC_LAT_CKEN 1
> +#define CLK_VDEC_LAT_ACTIVE 2
> +#define CLK_VDEC_LAT_CKEN_ENG 3
> +#define CLK_VDEC_MINI_MDP_CKEN_CFG_RG 4
> +#define CLK_VDEC_CKEN 5
> +#define CLK_VDEC_ACTIVE 6
> +#define CLK_VDEC_CKEN_ENG 7
> +#define CLK_VDEC_NR_CLK 8
> +
> +/* VENCSYS */
> +
> +#define CLK_VENC_CKE0_LARB 0
> +#define CLK_VENC_CKE1_VENC 1
> +#define CLK_VENC_CKE2_JPGENC 2
> +#define CLK_VENC_CKE5_GALS 3
> +#define CLK_VENC_NR_CLK 4
> +
> +/* CAMSYS */
> +
> +#define CLK_CAM_LARB13 0
> +#define CLK_CAM_DFP_VAD 1
> +#define CLK_CAM_LARB14 2
> +#define CLK_CAM 3
> +#define CLK_CAMTG 4
> +#define CLK_CAM_SENINF 5
> +#define CLK_CAMSV1 6
> +#define CLK_CAMSV2 7
> +#define CLK_CAMSV3 8
> +#define CLK_CAM_CCU0 9
> +#define CLK_CAM_CCU1 10
> +#define CLK_CAM_MRAW0 11
> +#define CLK_CAM_FAKE_ENG 12
> +#define CLK_CAM_CCU_GALS 13
> +#define CLK_CAM2MM_GALS 14
> +#define CLK_CAM_NR_CLK 15
> +
> +/* CAMSYS_RAWA */
> +
> +#define CLK_CAM_RAWA_LARBX_RAWA 0
> +#define CLK_CAM_RAWA 1
> +#define CLK_CAM_RAWA_CAMTG_RAWA 2
> +#define CLK_CAM_RAWA_NR_CLK 3
> +
> +/* CAMSYS_RAWB */
> +
> +#define CLK_CAM_RAWB_LARBX_RAWB 0
> +#define CLK_CAM_RAWB 1
> +#define CLK_CAM_RAWB_CAMTG_RAWB 2
> +#define CLK_CAM_RAWB_NR_CLK 3
> +
> +/* MDPSYS */
> +
> +#define CLK_MDP_RDMA0 0
> +#define CLK_MDP_TDSHP0 1
> +#define CLK_MDP_IMG_DL_ASYNC0 2
> +#define CLK_MDP_IMG_DL_ASYNC1 3
> +#define CLK_MDP_DISP_RDMA 4
> +#define CLK_MDP_HMS 5
> +#define CLK_MDP_SMI0 6
> +#define CLK_MDP_APB_BUS 7
> +#define CLK_MDP_WROT0 8
> +#define CLK_MDP_RSZ0 9
> +#define CLK_MDP_HDR0 10
> +#define CLK_MDP_MUTEX0 11
> +#define CLK_MDP_WROT1 12
> +#define CLK_MDP_RSZ1 13
> +#define CLK_MDP_FAKE_ENG0 14
> +#define CLK_MDP_AAL0 15
> +#define CLK_MDP_DISP_WDMA 16
> +#define CLK_MDP_COLOR 17
> +#define CLK_MDP_IMG_DL_ASYNC2 18
> +#define CLK_MDP_IMG_DL_RELAY0_ASYNC0 19
> +#define CLK_MDP_IMG_DL_RELAY1_ASYNC1 20
> +#define CLK_MDP_IMG_DL_RELAY2_ASYNC2 21
> +#define CLK_MDP_NR_CLK 22
> +
> +/* IPESYS */
> +
> +#define CLK_IPE_LARB19 0
> +#define CLK_IPE_LARB20 1
> +#define CLK_IPE_SMI_SUBCOM 2
> +#define CLK_IPE_FD 3
> +#define CLK_IPE_FE 4
> +#define CLK_IPE_RSC 5
> +#define CLK_IPE_DPE 6
> +#define CLK_IPE_GALS_IPE 7
> +#define CLK_IPE_NR_CLK 8
> +
> +#endif /* _DT_BINDINGS_CLK_MT8186_H */
> --
> 2.18.0
>
>
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [v1 02/16] clk: mediatek: Add dt-bindings of MT8186 clocks
2022-01-22 0:27 ` Rob Herring
@ 2022-02-09 1:43 ` Chun-Jie Chen
0 siblings, 0 replies; 39+ messages in thread
From: Chun-Jie Chen @ 2022-02-09 1:43 UTC (permalink / raw)
To: Rob Herring
Cc: Matthias Brugger, Stephen Boyd, Nicolas Boichat,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group
On Fri, 2022-01-21 at 18:27 -0600, Rob Herring wrote:
> On Mon, Jan 10, 2022 at 09:44:02PM +0800, Chun-Jie Chen wrote:
> > Add MT8186 clock dt-bindings, includes topckgen, apmixedsys,
> > infracfg_ao, mcusys and subsystem clocks.
> >
> > Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> > ---
> > include/dt-bindings/clock/mt8186-clk.h | 445
> > +++++++++++++++++++++++++
> > 1 file changed, 445 insertions(+)
> > create mode 100644 include/dt-bindings/clock/mt8186-clk.h
>
> As mentioned, squash with patch 1.
>
I will squash the patch with patch 1.
> >
> > diff --git a/include/dt-bindings/clock/mt8186-clk.h b/include/dt-
> > bindings/clock/mt8186-clk.h
> > new file mode 100644
> > index 000000000000..6a291750cea4
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/mt8186-clk.h
> > @@ -0,0 +1,445 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
>
> Dual license please.
>
I will change to dual license in next patch.
Thanks!
Best Regards,
Chun-Jie
> > +/*
> > + * Copyright (c) 2022 MediaTek Inc.
> > + * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> > + */
> > +
> > +#ifndef _DT_BINDINGS_CLK_MT8186_H
> > +#define _DT_BINDINGS_CLK_MT8186_H
> > +
> > +/* MCUSYS */
> > +
> > +#define CLK_MCU_ARMPLL_LL_SEL 0
> > +#define CLK_MCU_ARMPLL_BL_SEL 1
> > +#define CLK_MCU_ARMPLL_BUS_SEL 2
> > +#define CLK_MCU_NR_CLK 3
> > +
> > +/* TOPCKGEN */
> > +
> > +#define CLK_TOP_AXI 0
> > +#define CLK_TOP_SCP 1
> > +#define CLK_TOP_MFG 2
> > +#define CLK_TOP_CAMTG 3
> > +#define CLK_TOP_CAMTG1 4
> > +#define CLK_TOP_CAMTG2 5
> > +#define CLK_TOP_CAMTG3 6
> > +#define CLK_TOP_CAMTG4 7
> > +#define CLK_TOP_CAMTG5 8
> > +#define CLK_TOP_CAMTG6 9
> > +#define CLK_TOP_UART 10
> > +#define CLK_TOP_SPI 11
> > +#define CLK_TOP_MSDC50_0_HCLK 12
> > +#define CLK_TOP_MSDC50_0 13
> > +#define CLK_TOP_MSDC30_1 14
> > +#define CLK_TOP_AUDIO 15
> > +#define CLK_TOP_AUD_INTBUS 16
> > +#define CLK_TOP_AUD_1 17
> > +#define CLK_TOP_AUD_2 18
> > +#define CLK_TOP_AUD_ENGEN1 19
> > +#define CLK_TOP_AUD_ENGEN2 20
> > +#define CLK_TOP_DISP_PWM 21
> > +#define CLK_TOP_SSPM 22
> > +#define CLK_TOP_DXCC 23
> > +#define CLK_TOP_USB_TOP 24
> > +#define CLK_TOP_SRCK 25
> > +#define CLK_TOP_SPM 26
> > +#define CLK_TOP_I2C 27
> > +#define CLK_TOP_PWM 28
> > +#define CLK_TOP_SENINF 29
> > +#define CLK_TOP_SENINF1 30
> > +#define CLK_TOP_SENINF2 31
> > +#define CLK_TOP_SENINF3 32
> > +#define CLK_TOP_AES_MSDCFDE 33
> > +#define CLK_TOP_PWRAP_ULPOSC 34
> > +#define CLK_TOP_CAMTM 35
> > +#define CLK_TOP_VENC 36
> > +#define CLK_TOP_CAM 37
> > +#define CLK_TOP_IMG1 38
> > +#define CLK_TOP_IPE 39
> > +#define CLK_TOP_DPMAIF 40
> > +#define CLK_TOP_VDEC 41
> > +#define CLK_TOP_DISP 42
> > +#define CLK_TOP_MDP 43
> > +#define CLK_TOP_AUDIO_H 44
> > +#define CLK_TOP_UFS 45
> > +#define CLK_TOP_AES_FDE 46
> > +#define CLK_TOP_AUDIODSP 47
> > +#define CLK_TOP_DVFSRC 48
> > +#define CLK_TOP_DSI_OCC 49
> > +#define CLK_TOP_SPMI_MST 50
> > +#define CLK_TOP_SPINOR 51
> > +#define CLK_TOP_NNA 52
> > +#define CLK_TOP_NNA1 53
> > +#define CLK_TOP_NNA2 54
> > +#define CLK_TOP_SSUSB_XHCI 55
> > +#define CLK_TOP_SSUSB_TOP_1P 56
> > +#define CLK_TOP_SSUSB_XHCI_1P 57
> > +#define CLK_TOP_WPE 58
> > +#define CLK_TOP_DPI 59
> > +#define CLK_TOP_U3_OCC_250M 60
> > +#define CLK_TOP_U3_OCC_500M 61
> > +#define CLK_TOP_ADSP_BUS 62
> > +#define CLK_TOP_APLL_I2S0_MCK_SEL 63
> > +#define CLK_TOP_APLL_I2S1_MCK_SEL 64
> > +#define CLK_TOP_APLL_I2S2_MCK_SEL 65
> > +#define CLK_TOP_APLL_I2S4_MCK_SEL 66
> > +#define CLK_TOP_APLL_TDMOUT_MCK_SEL 67
> > +#define CLK_TOP_MAINPLL_D2 68
> > +#define CLK_TOP_MAINPLL_D2_D2 69
> > +#define CLK_TOP_MAINPLL_D2_D4 70
> > +#define CLK_TOP_MAINPLL_D2_D16 71
> > +#define CLK_TOP_MAINPLL_D3 72
> > +#define CLK_TOP_MAINPLL_D3_D2 73
> > +#define CLK_TOP_MAINPLL_D3_D4 74
> > +#define CLK_TOP_MAINPLL_D5 75
> > +#define CLK_TOP_MAINPLL_D5_D2 76
> > +#define CLK_TOP_MAINPLL_D5_D4 77
> > +#define CLK_TOP_MAINPLL_D7 78
> > +#define CLK_TOP_MAINPLL_D7_D2 79
> > +#define CLK_TOP_MAINPLL_D7_D4 80
> > +#define CLK_TOP_UNIVPLL 81
> > +#define CLK_TOP_UNIVPLL_D2 82
> > +#define CLK_TOP_UNIVPLL_D2_D2 83
> > +#define CLK_TOP_UNIVPLL_D2_D4 84
> > +#define CLK_TOP_UNIVPLL_D3 85
> > +#define CLK_TOP_UNIVPLL_D3_D2 86
> > +#define CLK_TOP_UNIVPLL_D3_D4 87
> > +#define CLK_TOP_UNIVPLL_D3_D8 88
> > +#define CLK_TOP_UNIVPLL_D3_D32 89
> > +#define CLK_TOP_UNIVPLL_D5 90
> > +#define CLK_TOP_UNIVPLL_D5_D2 91
> > +#define CLK_TOP_UNIVPLL_D5_D4 92
> > +#define CLK_TOP_UNIVPLL_D7 93
> > +#define CLK_TOP_UNIVPLL_192M 94
> > +#define CLK_TOP_UNIVPLL_192M_D4 95
> > +#define CLK_TOP_UNIVPLL_192M_D8 96
> > +#define CLK_TOP_UNIVPLL_192M_D16 97
> > +#define CLK_TOP_UNIVPLL_192M_D32 98
> > +#define CLK_TOP_APLL1_D2 99
> > +#define CLK_TOP_APLL1_D4 100
> > +#define CLK_TOP_APLL1_D8 101
> > +#define CLK_TOP_APLL2_D2 102
> > +#define CLK_TOP_APLL2_D4 103
> > +#define CLK_TOP_APLL2_D8 104
> > +#define CLK_TOP_MMPLL_D2 105
> > +#define CLK_TOP_TVDPLL_D2 106
> > +#define CLK_TOP_TVDPLL_D4 107
> > +#define CLK_TOP_TVDPLL_D8 108
> > +#define CLK_TOP_TVDPLL_D16 109
> > +#define CLK_TOP_TVDPLL_D32 110
> > +#define CLK_TOP_MSDCPLL_D2 111
> > +#define CLK_TOP_ULPOSC1 112
> > +#define CLK_TOP_ULPOSC1_D2 113
> > +#define CLK_TOP_ULPOSC1_D4 114
> > +#define CLK_TOP_ULPOSC1_D8 115
> > +#define CLK_TOP_ULPOSC1_D10 116
> > +#define CLK_TOP_ULPOSC1_D16 117
> > +#define CLK_TOP_ULPOSC1_D32 118
> > +#define CLK_TOP_ADSPPLL_D2 119
> > +#define CLK_TOP_ADSPPLL_D4 120
> > +#define CLK_TOP_ADSPPLL_D8 121
> > +#define CLK_TOP_NNAPLL_D2 122
> > +#define CLK_TOP_NNAPLL_D4 123
> > +#define CLK_TOP_NNAPLL_D8 124
> > +#define CLK_TOP_NNA2PLL_D2 125
> > +#define CLK_TOP_NNA2PLL_D4 126
> > +#define CLK_TOP_NNA2PLL_D8 127
> > +#define CLK_TOP_F_BIST2FPC 128
> > +#define CLK_TOP_466M_FMEM 129
> > +#define CLK_TOP_MPLL 130
> > +#define CLK_TOP_APLL12_CK_DIV0 131
> > +#define CLK_TOP_APLL12_CK_DIV1 132
> > +#define CLK_TOP_APLL12_CK_DIV2 133
> > +#define CLK_TOP_APLL12_CK_DIV4 134
> > +#define CLK_TOP_APLL12_CK_DIV_TDMOUT_M 135
> > +#define CLK_TOP_NR_CLK 136
> > +
> > +/* INFRACFG_AO */
> > +
> > +#define CLK_INFRA_AO_PMIC_TMR 0
> > +#define CLK_INFRA_AO_PMIC_AP 1
> > +#define CLK_INFRA_AO_PMIC_MD 2
> > +#define CLK_INFRA_AO_PMIC_CONN 3
> > +#define CLK_INFRA_AO_SCP_CORE 4
> > +#define CLK_INFRA_AO_SEJ 5
> > +#define CLK_INFRA_AO_APXGPT 6
> > +#define CLK_INFRA_AO_ICUSB 7
> > +#define CLK_INFRA_AO_GCE 8
> > +#define CLK_INFRA_AO_THERM 9
> > +#define CLK_INFRA_AO_I2C_AP 10
> > +#define CLK_INFRA_AO_I2C_CCU 11
> > +#define CLK_INFRA_AO_I2C_SSPM 12
> > +#define CLK_INFRA_AO_I2C_RSV 13
> > +#define CLK_INFRA_AO_PWM_HCLK 14
> > +#define CLK_INFRA_AO_PWM1 15
> > +#define CLK_INFRA_AO_PWM2 16
> > +#define CLK_INFRA_AO_PWM3 17
> > +#define CLK_INFRA_AO_PWM4 18
> > +#define CLK_INFRA_AO_PWM5 19
> > +#define CLK_INFRA_AO_PWM 20
> > +#define CLK_INFRA_AO_UART0 21
> > +#define CLK_INFRA_AO_UART1 22
> > +#define CLK_INFRA_AO_UART2 23
> > +#define CLK_INFRA_AO_GCE_26M 24
> > +#define CLK_INFRA_AO_CQ_DMA_FPC 25
> > +#define CLK_INFRA_AO_BTIF 26
> > +#define CLK_INFRA_AO_SPI0 27
> > +#define CLK_INFRA_AO_MSDC0 28
> > +#define CLK_INFRA_AO_MSDCFDE 29
> > +#define CLK_INFRA_AO_MSDC1 30
> > +#define CLK_INFRA_AO_DVFSRC 31
> > +#define CLK_INFRA_AO_GCPU 32
> > +#define CLK_INFRA_AO_TRNG 33
> > +#define CLK_INFRA_AO_AUXADC 34
> > +#define CLK_INFRA_AO_CPUM 35
> > +#define CLK_INFRA_AO_CCIF1_AP 36
> > +#define CLK_INFRA_AO_CCIF1_MD 37
> > +#define CLK_INFRA_AO_AUXADC_MD 38
> > +#define CLK_INFRA_AO_AP_DMA 39
> > +#define CLK_INFRA_AO_XIU 40
> > +#define CLK_INFRA_AO_DEVICE_APC 41
> > +#define CLK_INFRA_AO_CCIF_AP 42
> > +#define CLK_INFRA_AO_DEBUGTOP 43
> > +#define CLK_INFRA_AO_AUDIO 44
> > +#define CLK_INFRA_AO_CCIF_MD 45
> > +#define CLK_INFRA_AO_DXCC_SEC_CORE 46
> > +#define CLK_INFRA_AO_DXCC_AO 47
> > +#define CLK_INFRA_AO_IMP_IIC 48
> > +#define CLK_INFRA_AO_DRAMC_F26M 49
> > +#define CLK_INFRA_AO_RG_PWM_FBCLK6 50
> > +#define CLK_INFRA_AO_SSUSB_TOP_HCLK 51
> > +#define CLK_INFRA_AO_DISP_PWM 52
> > +#define CLK_INFRA_AO_CLDMA_BCLK 53
> > +#define CLK_INFRA_AO_AUDIO_26M_BCLK 54
> > +#define CLK_INFRA_AO_SSUSB_TOP_P1_HCLK 55
> > +#define CLK_INFRA_AO_SPI1 56
> > +#define CLK_INFRA_AO_I2C4 57
> > +#define CLK_INFRA_AO_MODEM_TEMP_SHARE 58
> > +#define CLK_INFRA_AO_SPI2 59
> > +#define CLK_INFRA_AO_SPI3 60
> > +#define CLK_INFRA_AO_SSUSB_TOP_REF 61
> > +#define CLK_INFRA_AO_SSUSB_TOP_XHCI 62
> > +#define CLK_INFRA_AO_SSUSB_TOP_P1_REF 63
> > +#define CLK_INFRA_AO_SSUSB_TOP_P1_XHCI 64
> > +#define CLK_INFRA_AO_SSPM 65
> > +#define CLK_INFRA_AO_SSUSB_TOP_P1_SYS 66
> > +#define CLK_INFRA_AO_I2C5 67
> > +#define CLK_INFRA_AO_I2C5_ARBITER 68
> > +#define CLK_INFRA_AO_I2C5_IMM 69
> > +#define CLK_INFRA_AO_I2C1_ARBITER 70
> > +#define CLK_INFRA_AO_I2C1_IMM 71
> > +#define CLK_INFRA_AO_I2C2_ARBITER 72
> > +#define CLK_INFRA_AO_I2C2_IMM 73
> > +#define CLK_INFRA_AO_SPI4 74
> > +#define CLK_INFRA_AO_SPI5 75
> > +#define CLK_INFRA_AO_CQ_DMA 76
> > +#define CLK_INFRA_AO_BIST2FPC 77
> > +#define CLK_INFRA_AO_MSDC0_SELF 78
> > +#define CLK_INFRA_AO_SPINOR 79
> > +#define CLK_INFRA_AO_SSPM_26M_SELF 80
> > +#define CLK_INFRA_AO_SSPM_32K_SELF 81
> > +#define CLK_INFRA_AO_I2C6 82
> > +#define CLK_INFRA_AO_AP_MSDC0 83
> > +#define CLK_INFRA_AO_MD_MSDC0 84
> > +#define CLK_INFRA_AO_MSDC0_SRC 85
> > +#define CLK_INFRA_AO_MSDC1_SRC 86
> > +#define CLK_INFRA_AO_SEJ_F13M 87
> > +#define CLK_INFRA_AO_AES_TOP0_BCLK 88
> > +#define CLK_INFRA_AO_MCU_PM_BCLK 89
> > +#define CLK_INFRA_AO_CCIF2_AP 90
> > +#define CLK_INFRA_AO_CCIF2_MD 91
> > +#define CLK_INFRA_AO_CCIF3_AP 92
> > +#define CLK_INFRA_AO_CCIF3_MD 93
> > +#define CLK_INFRA_AO_FADSP_26M 94
> > +#define CLK_INFRA_AO_FADSP_32K 95
> > +#define CLK_INFRA_AO_CCIF4_AP 96
> > +#define CLK_INFRA_AO_CCIF4_MD 97
> > +#define CLK_INFRA_AO_FADSP 98
> > +#define CLK_INFRA_AO_FLASHIF_133M 99
> > +#define CLK_INFRA_AO_FLASHIF_66M 100
> > +#define CLK_INFRA_AO_NR_CLK 101
> > +
> > +/* APMIXEDSYS */
> > +
> > +#define CLK_APMIXED_ARMPLL_LL 0
> > +#define CLK_APMIXED_ARMPLL_BL 1
> > +#define CLK_APMIXED_CCIPLL 2
> > +#define CLK_APMIXED_MAINPLL 3
> > +#define CLK_APMIXED_UNIV2PLL 4
> > +#define CLK_APMIXED_MSDCPLL 5
> > +#define CLK_APMIXED_MMPLL 6
> > +#define CLK_APMIXED_NNAPLL 7
> > +#define CLK_APMIXED_NNA2PLL 8
> > +#define CLK_APMIXED_ADSPPLL 9
> > +#define CLK_APMIXED_MFGPLL 10
> > +#define CLK_APMIXED_TVDPLL 11
> > +#define CLK_APMIXED_APLL1 12
> > +#define CLK_APMIXED_APLL2 13
> > +#define CLK_APMIXED_NR_CLK 14
> > +
> > +/* IMP_IIC_WRAP */
> > +
> > +#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0 0
> > +#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1 1
> > +#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2 2
> > +#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3 3
> > +#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4 4
> > +#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5 5
> > +#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6 6
> > +#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7 7
> > +#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8 8
> > +#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9 9
> > +#define CLK_IMP_IIC_WRAP_NR_CLK 10
> > +
> > +/* MFGCFG */
> > +
> > +#define CLK_MFG_BG3D 0
> > +#define CLK_MFG_NR_CLK 1
> > +
> > +/* MMSYS */
> > +
> > +#define CLK_MM_DISP_MUTEX0 0
> > +#define CLK_MM_APB_MM_BUS 1
> > +#define CLK_MM_DISP_OVL0 2
> > +#define CLK_MM_DISP_RDMA0 3
> > +#define CLK_MM_DISP_OVL0_2L 4
> > +#define CLK_MM_DISP_WDMA0 5
> > +#define CLK_MM_DISP_RSZ0 6
> > +#define CLK_MM_DISP_AAL0 7
> > +#define CLK_MM_DISP_CCORR0 8
> > +#define CLK_MM_DISP_COLOR0 9
> > +#define CLK_MM_SMI_INFRA 10
> > +#define CLK_MM_DISP_DSC_WRAP0 11
> > +#define CLK_MM_DISP_GAMMA0 12
> > +#define CLK_MM_DISP_POSTMASK0 13
> > +#define CLK_MM_DISP_DITHER0 14
> > +#define CLK_MM_SMI_COMMON 15
> > +#define CLK_MM_DSI0 16
> > +#define CLK_MM_DISP_FAKE_ENG0 17
> > +#define CLK_MM_DISP_FAKE_ENG1 18
> > +#define CLK_MM_SMI_GALS 19
> > +#define CLK_MM_SMI_IOMMU 20
> > +#define CLK_MM_DISP_RDMA1 21
> > +#define CLK_MM_DISP_DPI 22
> > +#define CLK_MM_DSI0_DSI_CK_DOMAIN 23
> > +#define CLK_MM_DISP_26M 24
> > +#define CLK_MM_NR_CLK 25
> > +
> > +/* WPESYS */
> > +
> > +#define CLK_WPE_CK_EN 0
> > +#define CLK_WPE_SMI_LARB8_CK_EN 1
> > +#define CLK_WPE_SYS_EVENT_TX_CK_EN 2
> > +#define CLK_WPE_SMI_LARB8_PCLK_EN 3
> > +#define CLK_WPE_NR_CLK 4
> > +
> > +/* IMGSYS1 */
> > +
> > +#define CLK_IMG1_LARB9_IMG1 0
> > +#define CLK_IMG1_LARB10_IMG1 1
> > +#define CLK_IMG1_DIP 2
> > +#define CLK_IMG1_GALS_IMG1 3
> > +#define CLK_IMG1_NR_CLK 4
> > +
> > +/* IMGSYS2 */
> > +
> > +#define CLK_IMG2_LARB9_IMG2 0
> > +#define CLK_IMG2_LARB10_IMG2 1
> > +#define CLK_IMG2_MFB 2
> > +#define CLK_IMG2_WPE 3
> > +#define CLK_IMG2_MSS 4
> > +#define CLK_IMG2_GALS_IMG2 5
> > +#define CLK_IMG2_NR_CLK 6
> > +
> > +/* VDECSYS */
> > +
> > +#define CLK_VDEC_LARB1_CKEN 0
> > +#define CLK_VDEC_LAT_CKEN 1
> > +#define CLK_VDEC_LAT_ACTIVE 2
> > +#define CLK_VDEC_LAT_CKEN_ENG 3
> > +#define CLK_VDEC_MINI_MDP_CKEN_CFG_RG 4
> > +#define CLK_VDEC_CKEN 5
> > +#define CLK_VDEC_ACTIVE 6
> > +#define CLK_VDEC_CKEN_ENG 7
> > +#define CLK_VDEC_NR_CLK 8
> > +
> > +/* VENCSYS */
> > +
> > +#define CLK_VENC_CKE0_LARB 0
> > +#define CLK_VENC_CKE1_VENC 1
> > +#define CLK_VENC_CKE2_JPGENC 2
> > +#define CLK_VENC_CKE5_GALS 3
> > +#define CLK_VENC_NR_CLK 4
> > +
> > +/* CAMSYS */
> > +
> > +#define CLK_CAM_LARB13 0
> > +#define CLK_CAM_DFP_VAD 1
> > +#define CLK_CAM_LARB14 2
> > +#define CLK_CAM 3
> > +#define CLK_CAMTG 4
> > +#define CLK_CAM_SENINF 5
> > +#define CLK_CAMSV1 6
> > +#define CLK_CAMSV2 7
> > +#define CLK_CAMSV3 8
> > +#define CLK_CAM_CCU0 9
> > +#define CLK_CAM_CCU1 10
> > +#define CLK_CAM_MRAW0 11
> > +#define CLK_CAM_FAKE_ENG 12
> > +#define CLK_CAM_CCU_GALS 13
> > +#define CLK_CAM2MM_GALS 14
> > +#define CLK_CAM_NR_CLK 15
> > +
> > +/* CAMSYS_RAWA */
> > +
> > +#define CLK_CAM_RAWA_LARBX_RAWA 0
> > +#define CLK_CAM_RAWA 1
> > +#define CLK_CAM_RAWA_CAMTG_RAWA 2
> > +#define CLK_CAM_RAWA_NR_CLK 3
> > +
> > +/* CAMSYS_RAWB */
> > +
> > +#define CLK_CAM_RAWB_LARBX_RAWB 0
> > +#define CLK_CAM_RAWB 1
> > +#define CLK_CAM_RAWB_CAMTG_RAWB 2
> > +#define CLK_CAM_RAWB_NR_CLK 3
> > +
> > +/* MDPSYS */
> > +
> > +#define CLK_MDP_RDMA0 0
> > +#define CLK_MDP_TDSHP0 1
> > +#define CLK_MDP_IMG_DL_ASYNC0 2
> > +#define CLK_MDP_IMG_DL_ASYNC1 3
> > +#define CLK_MDP_DISP_RDMA 4
> > +#define CLK_MDP_HMS 5
> > +#define CLK_MDP_SMI0 6
> > +#define CLK_MDP_APB_BUS 7
> > +#define CLK_MDP_WROT0 8
> > +#define CLK_MDP_RSZ0 9
> > +#define CLK_MDP_HDR0 10
> > +#define CLK_MDP_MUTEX0 11
> > +#define CLK_MDP_WROT1 12
> > +#define CLK_MDP_RSZ1 13
> > +#define CLK_MDP_FAKE_ENG0 14
> > +#define CLK_MDP_AAL0 15
> > +#define CLK_MDP_DISP_WDMA 16
> > +#define CLK_MDP_COLOR 17
> > +#define CLK_MDP_IMG_DL_ASYNC2 18
> > +#define CLK_MDP_IMG_DL_RELAY0_ASYNC0 19
> > +#define CLK_MDP_IMG_DL_RELAY1_ASYNC1 20
> > +#define CLK_MDP_IMG_DL_RELAY2_ASYNC2 21
> > +#define CLK_MDP_NR_CLK 22
> > +
> > +/* IPESYS */
> > +
> > +#define CLK_IPE_LARB19 0
> > +#define CLK_IPE_LARB20 1
> > +#define CLK_IPE_SMI_SUBCOM 2
> > +#define CLK_IPE_FD 3
> > +#define CLK_IPE_FE 4
> > +#define CLK_IPE_RSC 5
> > +#define CLK_IPE_DPE 6
> > +#define CLK_IPE_GALS_IPE 7
> > +#define CLK_IPE_NR_CLK 8
> > +
> > +#endif /* _DT_BINDINGS_CLK_MT8186_H */
> > --
> > 2.18.0
> >
> >
^ permalink raw reply [flat|nested] 39+ messages in thread
* [v1 03/16] clk: mediatek: Add MT8186 mcusys clock support
[not found] <20220110134416.5191-1-chun-jie.chen@mediatek.com>
2022-01-10 13:44 ` [v1 01/16] dt-bindings: ARM: Mediatek: Add new document bindings of MT8186 clock Chun-Jie Chen
2022-01-10 13:44 ` [v1 02/16] clk: mediatek: Add dt-bindings of MT8186 clocks Chun-Jie Chen
@ 2022-01-10 13:44 ` Chun-Jie Chen
2022-01-10 15:51 ` AngeloGioacchino Del Regno
2022-01-10 18:39 ` kernel test robot
2022-01-10 13:44 ` [v1 04/16] clk: mediatek: Add MT8186 topckgen " Chun-Jie Chen
` (12 subsequent siblings)
15 siblings, 2 replies; 39+ messages in thread
From: Chun-Jie Chen @ 2022-01-10 13:44 UTC (permalink / raw)
To: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring
Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group,
Chun-Jie Chen
Add MT8186 mcusys clock controller which provides muxes
to select the clock source of APMCU.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
drivers/clk/mediatek/Kconfig | 8 +++
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8186-mcu.c | 86 +++++++++++++++++++++++++++
3 files changed, 95 insertions(+)
create mode 100644 drivers/clk/mediatek/clk-mt8186-mcu.c
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 3ce6fb04d8ff..7218165b6a44 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -495,6 +495,14 @@ config COMMON_CLK_MT8183_VENCSYS
help
This driver supports MediaTek MT8183 vencsys clocks.
+config COMMON_CLK_MT8186
+ bool "Clock driver for MediaTek MT8186"
+ depends on ARM64 || COMPILE_TEST
+ select COMMON_CLK_MEDIATEK
+ default ARCH_MEDIATEK
+ help
+ This driver supports MediaTek MT8186 clocks.
+
config COMMON_CLK_MT8192
bool "Clock driver for MediaTek MT8192"
depends on ARM64 || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index dc96038a0155..0ae3828f69fb 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -67,6 +67,7 @@ obj-$(CONFIG_COMMON_CLK_MT8183_MFGCFG) += clk-mt8183-mfgcfg.o
obj-$(CONFIG_COMMON_CLK_MT8183_MMSYS) += clk-mt8183-mm.o
obj-$(CONFIG_COMMON_CLK_MT8183_VDECSYS) += clk-mt8183-vdec.o
obj-$(CONFIG_COMMON_CLK_MT8183_VENCSYS) += clk-mt8183-venc.o
+obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8186-mcu.c b/drivers/clk/mediatek/clk-mt8186-mcu.c
new file mode 100644
index 000000000000..293176633f65
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8186-mcu.c
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2022 MediaTek Inc.
+// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
+
+#include "clk-mtk.h"
+
+#include <dt-bindings/clock/mt8186-clk.h>
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+static DEFINE_SPINLOCK(mt8186_clk_lock);
+
+static const char * const mcu_armpll_ll_parents[] = {
+ "clk26m",
+ "armpll_ll",
+ "mainpll",
+ "univpll_d2"
+};
+
+static const char * const mcu_armpll_bl_parents[] = {
+ "clk26m",
+ "armpll_bl",
+ "mainpll",
+ "univpll_d2"
+};
+
+static const char * const mcu_armpll_bus_parents[] = {
+ "clk26m",
+ "ccipll",
+ "mainpll",
+ "univpll_d2"
+};
+
+static struct mtk_composite mcu_muxes[] = {
+ /* CPU_PLLDIV_CFG0 */
+ MUX(CLK_MCU_ARMPLL_LL_SEL, "mcu_armpll_ll_sel", mcu_armpll_ll_parents, 0x2A0, 9, 2),
+ /* CPU_PLLDIV_CFG1 */
+ MUX(CLK_MCU_ARMPLL_BL_SEL, "mcu_armpll_bl_sel", mcu_armpll_bl_parents, 0x2A4, 9, 2),
+ /* BUS_PLLDIV_CFG */
+ MUX(CLK_MCU_ARMPLL_BUS_SEL, "mcu_armpll_bus_sel", mcu_armpll_bus_parents, 0x2E0, 9, 2),
+};
+
+static const struct of_device_id of_match_clk_mt8186_mcu[] = {
+ { .compatible = "mediatek,mt8186-mcusys", },
+ {}
+};
+
+static int clk_mt8186_mcu_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+ int r;
+ void __iomem *base;
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK);
+ if (!clk_data)
+ return -ENOMEM;
+
+ mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base,
+ &mt8186_clk_lock, clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ goto unregister_clk;
+
+ return r;
+
+unregister_clk:
+ mtk_clk_unregister(clk_data);
+ mtk_free_clk_data(clk_data);
+ return r;
+}
+
+static struct platform_driver clk_mt8186_mcu_drv = {
+ .probe = clk_mt8186_mcu_probe,
+ .driver = {
+ .name = "clk-mt8186-mcu",
+ .of_match_table = of_match_clk_mt8186_mcu,
+ },
+};
+builtin_platform_driver(clk_mt8186_mcu_drv);
--
2.18.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [v1 03/16] clk: mediatek: Add MT8186 mcusys clock support
2022-01-10 13:44 ` [v1 03/16] clk: mediatek: Add MT8186 mcusys clock support Chun-Jie Chen
@ 2022-01-10 15:51 ` AngeloGioacchino Del Regno
2022-01-10 18:39 ` kernel test robot
1 sibling, 0 replies; 39+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-01-10 15:51 UTC (permalink / raw)
To: Chun-Jie Chen, Matthias Brugger, Stephen Boyd, Nicolas Boichat,
Rob Herring
Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group
Il 10/01/22 14:44, Chun-Jie Chen ha scritto:
> Add MT8186 mcusys clock controller which provides muxes
> to select the clock source of APMCU.
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [v1 03/16] clk: mediatek: Add MT8186 mcusys clock support
2022-01-10 13:44 ` [v1 03/16] clk: mediatek: Add MT8186 mcusys clock support Chun-Jie Chen
2022-01-10 15:51 ` AngeloGioacchino Del Regno
@ 2022-01-10 18:39 ` kernel test robot
1 sibling, 0 replies; 39+ messages in thread
From: kernel test robot @ 2022-01-10 18:39 UTC (permalink / raw)
To: Chun-Jie Chen, Matthias Brugger, Stephen Boyd, Nicolas Boichat,
Rob Herring
Cc: kbuild-all, linux-arm-kernel, linux-kernel, linux-mediatek,
linux-clk, devicetree, srv_heupstream
Hi Chun-Jie,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on clk/clk-next]
[also build test ERROR on robh/for-next v5.16 next-20220110]
[cannot apply to mbgg-mediatek/for-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Chun-Jie-Chen/dt-bindings-ARM-Mediatek-Add-new-document-bindings-of-MT8186-clock/20220110-224451
base: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
config: nios2-allyesconfig (https://download.01.org/0day-ci/archive/20220111/202201110231.DNu9pn4H-lkp@intel.com/config)
compiler: nios2-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/d28b64e80990fd336192ccdd31676120bf4e2696
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Chun-Jie-Chen/dt-bindings-ARM-Mediatek-Add-new-document-bindings-of-MT8186-clock/20220110-224451
git checkout d28b64e80990fd336192ccdd31676120bf4e2696
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=nios2 SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
drivers/clk/mediatek/clk-mt8186-mcu.c: In function 'clk_mt8186_mcu_probe':
>> drivers/clk/mediatek/clk-mt8186-mcu.c:74:9: error: implicit declaration of function 'mtk_clk_unregister'; did you mean 'devm_clk_unregister'? [-Werror=implicit-function-declaration]
74 | mtk_clk_unregister(clk_data);
| ^~~~~~~~~~~~~~~~~~
| devm_clk_unregister
cc1: some warnings being treated as errors
vim +74 drivers/clk/mediatek/clk-mt8186-mcu.c
48
49 static int clk_mt8186_mcu_probe(struct platform_device *pdev)
50 {
51 struct clk_onecell_data *clk_data;
52 struct device_node *node = pdev->dev.of_node;
53 int r;
54 void __iomem *base;
55
56 base = devm_platform_ioremap_resource(pdev, 0);
57 if (IS_ERR(base))
58 return PTR_ERR(base);
59
60 clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK);
61 if (!clk_data)
62 return -ENOMEM;
63
64 mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base,
65 &mt8186_clk_lock, clk_data);
66
67 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
68 if (r)
69 goto unregister_clk;
70
71 return r;
72
73 unregister_clk:
> 74 mtk_clk_unregister(clk_data);
75 mtk_free_clk_data(clk_data);
76 return r;
77 }
78
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
^ permalink raw reply [flat|nested] 39+ messages in thread
* [v1 04/16] clk: mediatek: Add MT8186 topckgen clock support
[not found] <20220110134416.5191-1-chun-jie.chen@mediatek.com>
` (2 preceding siblings ...)
2022-01-10 13:44 ` [v1 03/16] clk: mediatek: Add MT8186 mcusys clock support Chun-Jie Chen
@ 2022-01-10 13:44 ` Chun-Jie Chen
2022-01-10 15:50 ` AngeloGioacchino Del Regno
2022-01-10 21:13 ` kernel test robot
2022-01-10 13:44 ` [v1 05/16] clk: mediatek: Add MT8186 infrastructure " Chun-Jie Chen
` (11 subsequent siblings)
15 siblings, 2 replies; 39+ messages in thread
From: Chun-Jie Chen @ 2022-01-10 13:44 UTC (permalink / raw)
To: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring
Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group,
Chun-Jie Chen
Add MT8186 topckgen clock controller which provides muxes, dividers
to handle variety clock selection in other IP blocks.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
drivers/clk/mediatek/Makefile | 2 +-
drivers/clk/mediatek/clk-mt8186-topckgen.c | 737 +++++++++++++++++++++
2 files changed, 738 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mediatek/clk-mt8186-topckgen.c
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 0ae3828f69fb..a5166f0860bd 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -67,7 +67,7 @@ obj-$(CONFIG_COMMON_CLK_MT8183_MFGCFG) += clk-mt8183-mfgcfg.o
obj-$(CONFIG_COMMON_CLK_MT8183_MMSYS) += clk-mt8183-mm.o
obj-$(CONFIG_COMMON_CLK_MT8183_VDECSYS) += clk-mt8183-vdec.o
obj-$(CONFIG_COMMON_CLK_MT8183_VENCSYS) += clk-mt8183-venc.o
-obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o
+obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8186-topckgen.c b/drivers/clk/mediatek/clk-mt8186-topckgen.c
new file mode 100644
index 000000000000..096178bed8de
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8186-topckgen.c
@@ -0,0 +1,737 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2022 MediaTek Inc.
+// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
+
+#include "clk-mtk.h"
+#include "clk-mux.h"
+
+#include <dt-bindings/clock/mt8186-clk.h>
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+static DEFINE_SPINLOCK(mt8186_clk_lock);
+
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+ FIXED_CLK(CLK_TOP_ULPOSC1, "ulposc1", NULL, 250000000),
+ FIXED_CLK(CLK_TOP_466M_FMEM, "hd_466m_fmem_ck", NULL, 466000000),
+ FIXED_CLK(CLK_TOP_MPLL, "mpll", NULL, 208000000),
+};
+
+static const struct mtk_fixed_factor top_divs[] = {
+ FACTOR(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll", 1, 2),
+ FACTOR(CLK_TOP_MAINPLL_D2_D2, "mainpll_d2_d2", "mainpll_d2", 1, 2),
+ FACTOR(CLK_TOP_MAINPLL_D2_D4, "mainpll_d2_d4", "mainpll_d2", 1, 4),
+ FACTOR(CLK_TOP_MAINPLL_D2_D16, "mainpll_d2_d16", "mainpll_d2", 1, 16),
+ FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3),
+ FACTOR(CLK_TOP_MAINPLL_D3_D2, "mainpll_d3_d2", "mainpll_d3", 1, 2),
+ FACTOR(CLK_TOP_MAINPLL_D3_D4, "mainpll_d3_d4", "mainpll_d3", 1, 4),
+ FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5),
+ FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2),
+ FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4),
+ FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7),
+ FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2),
+ FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4),
+ FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2),
+ FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
+ FACTOR(CLK_TOP_UNIVPLL_D2_D2, "univpll_d2_d2", "univpll_d2", 1, 2),
+ FACTOR(CLK_TOP_UNIVPLL_D2_D4, "univpll_d2_d4", "univpll_d2", 1, 4),
+ FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
+ FACTOR(CLK_TOP_UNIVPLL_D3_D2, "univpll_d3_d2", "univpll_d3", 1, 2),
+ FACTOR(CLK_TOP_UNIVPLL_D3_D4, "univpll_d3_d4", "univpll_d3", 1, 4),
+ FACTOR(CLK_TOP_UNIVPLL_D3_D8, "univpll_d3_d8", "univpll_d3", 1, 8),
+ FACTOR(CLK_TOP_UNIVPLL_D3_D32, "univpll_d3_d32", "univpll_d3", 1, 32),
+ FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
+ FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2),
+ FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4),
+ FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
+ FACTOR(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univ2pll", 1, 13),
+ FACTOR(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll_192m", 1, 4),
+ FACTOR(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll_192m", 1, 8),
+ FACTOR(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll_192m", 1, 16),
+ FACTOR(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll_192m", 1, 32),
+ FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 2),
+ FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4),
+ FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1, 8),
+ FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2),
+ FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
+ FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1, 8),
+ FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
+ FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll", 1, 2),
+ FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
+ FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1, 8),
+ FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1, 16),
+ FACTOR(CLK_TOP_TVDPLL_D32, "tvdpll_d32", "tvdpll", 1, 32),
+ FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
+ FACTOR(CLK_TOP_ULPOSC1_D2, "ulposc1_d2", "ulposc1", 1, 2),
+ FACTOR(CLK_TOP_ULPOSC1_D4, "ulposc1_d4", "ulposc1", 1, 4),
+ FACTOR(CLK_TOP_ULPOSC1_D8, "ulposc1_d8", "ulposc1", 1, 8),
+ FACTOR(CLK_TOP_ULPOSC1_D10, "ulposc1_d10", "ulposc1", 1, 10),
+ FACTOR(CLK_TOP_ULPOSC1_D16, "ulposc1_d16", "ulposc1", 1, 16),
+ FACTOR(CLK_TOP_ULPOSC1_D32, "ulposc1_d32", "ulposc1", 1, 32),
+ FACTOR(CLK_TOP_ADSPPLL_D2, "adsppll_d2", "adsppll", 1, 2),
+ FACTOR(CLK_TOP_ADSPPLL_D4, "adsppll_d4", "adsppll", 1, 4),
+ FACTOR(CLK_TOP_ADSPPLL_D8, "adsppll_d8", "adsppll", 1, 8),
+ FACTOR(CLK_TOP_NNAPLL_D2, "nnapll_d2", "nnapll", 1, 2),
+ FACTOR(CLK_TOP_NNAPLL_D4, "nnapll_d4", "nnapll", 1, 4),
+ FACTOR(CLK_TOP_NNAPLL_D8, "nnapll_d8", "nnapll", 1, 8),
+ FACTOR(CLK_TOP_NNA2PLL_D2, "nna2pll_d2", "nna2pll", 1, 2),
+ FACTOR(CLK_TOP_NNA2PLL_D4, "nna2pll_d4", "nna2pll", 1, 4),
+ FACTOR(CLK_TOP_NNA2PLL_D8, "nna2pll_d8", "nna2pll", 1, 8),
+ FACTOR(CLK_TOP_F_BIST2FPC, "f_bist2fpc_ck", "univpll_d3_d2", 1, 1),
+};
+
+static const char * const axi_parents[] = {
+ "clk26m",
+ "mainpll_d7",
+ "mainpll_d2_d4",
+ "univpll_d7"
+};
+
+static const char * const scp_parents[] = {
+ "clk26m",
+ "mainpll_d2_d4",
+ "mainpll_d5",
+ "mainpll_d2_d2",
+ "mainpll_d3",
+ "univpll_d3"
+};
+
+static const char * const mfg_parents[] = {
+ "clk26m",
+ "mfgpll",
+ "mainpll_d3",
+ "mainpll_d5"
+};
+
+static const char * const camtg_parents[] = {
+ "clk26m",
+ "univpll_192m_d8",
+ "univpll_d3_d8",
+ "univpll_192m_d4",
+ "univpll_d3_d32",
+ "univpll_192m_d16",
+ "univpll_192m_d32"
+};
+
+static const char * const uart_parents[] = {
+ "clk26m",
+ "univpll_d3_d8"
+};
+
+static const char * const spi_parents[] = {
+ "clk26m",
+ "mainpll_d5_d4",
+ "mainpll_d3_d4",
+ "mainpll_d5_d2",
+ "mainpll_d2_d4",
+ "mainpll_d7",
+ "mainpll_d3_d2",
+ "mainpll_d5"
+};
+
+static const char * const msdc5hclk_parents[] = {
+ "clk26m",
+ "mainpll_d2_d2",
+ "mainpll_d7",
+ "mainpll_d3_d2"
+};
+
+static const char * const msdc50_0_parents[] = {
+ "clk26m",
+ "msdcpll",
+ "univpll_d3",
+ "msdcpll_d2",
+ "mainpll_d7",
+ "mainpll_d3_d2",
+ "univpll_d2_d2"
+};
+
+static const char * const msdc30_1_parents[] = {
+ "clk26m",
+ "msdcpll_d2",
+ "univpll_d3_d2",
+ "mainpll_d3_d2",
+ "mainpll_d7"
+};
+
+static const char * const audio_parents[] = {
+ "clk26m",
+ "mainpll_d5_d4",
+ "mainpll_d7_d4",
+ "mainpll_d2_d16"
+};
+
+static const char * const aud_intbus_parents[] = {
+ "clk26m",
+ "mainpll_d2_d4",
+ "mainpll_d7_d2"
+};
+
+static const char * const aud_1_parents[] = {
+ "clk26m",
+ "apll1"
+};
+
+static const char * const aud_2_parents[] = {
+ "clk26m",
+ "apll2"
+};
+
+static const char * const aud_engen1_parents[] = {
+ "clk26m",
+ "apll1_d2",
+ "apll1_d4",
+ "apll1_d8"
+};
+
+static const char * const aud_engen2_parents[] = {
+ "clk26m",
+ "apll2_d2",
+ "apll2_d4",
+ "apll2_d8"
+};
+
+static const char * const disp_pwm_parents[] = {
+ "clk26m",
+ "univpll_d5_d2",
+ "univpll_d3_d4",
+ "ulposc1_d2",
+ "ulposc1_d8"
+};
+
+static const char * const sspm_parents[] = {
+ "clk26m",
+ "mainpll_d2_d2",
+ "mainpll_d3_d2",
+ "mainpll_d5",
+ "mainpll_d3"
+};
+
+static const char * const dxcc_parents[] = {
+ "clk26m",
+ "mainpll_d2_d2",
+ "mainpll_d2_d4"
+};
+
+static const char * const usb_parents[] = {
+ "clk26m",
+ "univpll_d5_d4",
+ "univpll_d5_d2"
+};
+
+static const char * const srck_parents[] = {
+ "clk32k",
+ "clk26m",
+ "ulposc1_d10"
+};
+
+static const char * const spm_parents[] = {
+ "clk32k",
+ "ulposc1_d10",
+ "clk26m",
+ "mainpll_d7_d2"
+};
+
+static const char * const i2c_parents[] = {
+ "clk26m",
+ "univpll_d5_d4",
+ "univpll_d3_d4",
+ "univpll_d5_d2"
+};
+
+static const char * const pwm_parents[] = {
+ "clk26m",
+ "univpll_d3_d8",
+ "univpll_d3_d4",
+ "univpll_d2_d4"
+};
+
+static const char * const seninf_parents[] = {
+ "clk26m",
+ "univpll_d2_d4",
+ "univpll_d2_d2",
+ "univpll_d3_d2"
+};
+
+static const char * const aes_msdcfde_parents[] = {
+ "clk26m",
+ "univpll_d3",
+ "mainpll_d3",
+ "univpll_d2_d2",
+ "mainpll_d2_d2",
+ "mainpll_d2_d4"
+};
+
+static const char * const pwrap_ulposc_parents[] = {
+ "clk26m",
+ "univpll_d5_d4",
+ "ulposc1_d4",
+ "ulposc1_d8",
+ "ulposc1_d10",
+ "ulposc1_d16",
+ "ulposc1_d32"
+};
+
+static const char * const camtm_parents[] = {
+ "clk26m",
+ "univpll_d2_d4",
+ "univpll_d3_d2"
+};
+
+static const char * const venc_parents[] = {
+ "clk26m",
+ "mmpll",
+ "mainpll_d2_d2",
+ "mainpll_d2",
+ "univpll_d3",
+ "univpll_d2_d2",
+ "mainpll_d3",
+ "mmpll"
+};
+
+static const char * const isp_parents[] = {
+ "clk26m",
+ "mainpll_d2",
+ "mainpll_d2_d2",
+ "univpll_d3",
+ "mainpll_d3",
+ "mmpll",
+ "univpll_d5",
+ "univpll_d2_d2",
+ "mmpll_d2"
+};
+
+static const char * const dpmaif_parents[] = {
+ "clk26m",
+ "univpll_d2_d2",
+ "mainpll_d3",
+ "mainpll_d2_d2",
+ "univpll_d3_d2"
+};
+
+static const char * const vdec_parents[] = {
+ "clk26m",
+ "mainpll_d3",
+ "mainpll_d2_d2",
+ "univpll_d5",
+ "mainpll_d2",
+ "univpll_d3",
+ "univpll_d2_d2"
+};
+
+static const char * const disp_parents[] = {
+ "clk26m",
+ "univpll_d3_d2",
+ "mainpll_d5",
+ "univpll_d5",
+ "univpll_d2_d2",
+ "mainpll_d3",
+ "univpll_d3",
+ "mainpll_d2",
+ "mmpll"
+};
+
+static const char * const mdp_parents[] = {
+ "clk26m",
+ "mainpll_d5",
+ "univpll_d5",
+ "mainpll_d2_d2",
+ "univpll_d2_d2",
+ "mainpll_d3",
+ "univpll_d3",
+ "mainpll_d2",
+ "mmpll"
+};
+
+static const char * const audio_h_parents[] = {
+ "clk26m",
+ "univpll_d7",
+ "apll1",
+ "apll2"
+};
+
+static const char * const ufs_parents[] = {
+ "clk26m",
+ "mainpll_d7",
+ "univpll_d2_d4",
+ "mainpll_d2_d4"
+};
+
+static const char * const aes_fde_parents[] = {
+ "clk26m",
+ "univpll_d3",
+ "mainpll_d2_d2",
+ "univpll_d5"
+};
+
+static const char * const audiodsp_parents[] = {
+ "clk26m",
+ "ulposc1_d10",
+ "adsppll",
+ "adsppll_d2",
+ "adsppll_d4",
+ "adsppll_d8"
+};
+
+static const char * const dvfsrc_parents[] = {
+ "clk26m",
+ "ulposc1_d10",
+};
+
+static const char * const dsi_occ_parents[] = {
+ "clk26m",
+ "univpll_d3_d2",
+ "mpll",
+ "mainpll_d5"
+};
+
+static const char * const spmi_mst_parents[] = {
+ "clk26m",
+ "univpll_d5_d4",
+ "ulposc1_d4",
+ "ulposc1_d8",
+ "ulposc1_d10",
+ "ulposc1_d16",
+ "ulposc1_d32"
+};
+
+static const char * const spinor_parents[] = {
+ "clk26m",
+ "clk13m",
+ "mainpll_d7_d4",
+ "univpll_d3_d8",
+ "univpll_d5_d4",
+ "mainpll_d7_d2"
+};
+
+static const char * const nna_parents[] = {
+ "clk26m",
+ "univpll_d3_d8",
+ "mainpll_d2_d4",
+ "univpll_d3_d2",
+ "mainpll_d2_d2",
+ "univpll_d2_d2",
+ "mainpll_d3",
+ "univpll_d3",
+ "mmpll",
+ "mainpll_d2",
+ "univpll_d2",
+ "nnapll_d2",
+ "nnapll_d4",
+ "nnapll_d8",
+ "nnapll",
+ "nna2pll"
+};
+
+static const char * const nna2_parents[] = {
+ "clk26m",
+ "univpll_d3_d8",
+ "mainpll_d2_d4",
+ "univpll_d3_d2",
+ "mainpll_d2_d2",
+ "univpll_d2_d2",
+ "mainpll_d3",
+ "univpll_d3",
+ "mmpll",
+ "mainpll_d2",
+ "univpll_d2",
+ "nna2pll_d2",
+ "nna2pll_d4",
+ "nna2pll_d8",
+ "nnapll",
+ "nna2pll"
+};
+
+static const char * const ssusb_parents[] = {
+ "clk26m",
+ "univpll_d5_d4",
+ "univpll_d5_d2"
+};
+
+static const char * const wpe_parents[] = {
+ "clk26m",
+ "univpll_d3_d2",
+ "mainpll_d5",
+ "univpll_d5",
+ "univpll_d2_d2",
+ "mainpll_d3",
+ "univpll_d3",
+ "mainpll_d2",
+ "mmpll"
+};
+
+static const char * const dpi_parents[] = {
+ "clk26m",
+ "tvdpll",
+ "tvdpll_d2",
+ "tvdpll_d4",
+ "tvdpll_d8",
+ "tvdpll_d16",
+ "tvdpll_d32"
+};
+
+static const char * const u3_occ_250m_parents[] = {
+ "clk26m",
+ "univpll_d5"
+};
+
+static const char * const u3_occ_500m_parents[] = {
+ "clk26m",
+ "nna2pll_d2"
+};
+
+static const char * const adsp_bus_parents[] = {
+ "clk26m",
+ "ulposc1_d2",
+ "mainpll_d5",
+ "mainpll_d2_d2",
+ "mainpll_d3",
+ "mainpll_d2",
+ "univpll_d3"
+};
+
+static const char * const apll_mck_parents[] = {
+ "top_aud_1",
+ "top_aud_2"
+};
+
+static const struct mtk_mux top_mtk_muxes[] = {
+ /*
+ * CLK_CFG_0
+ * top_axi is bus clock, should not be closed by Linux.
+ * top_scp is main clock in always-on co-processor.
+ */
+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI, "top_axi", axi_parents,
+ 0x0040, 0x0044, 0x0048, 0, 2, 7, 0x0004, 0,
+ CLK_IS_CRITICAL),
+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SCP, "top_scp", scp_parents,
+ 0x0040, 0x0044, 0x0048, 8, 3, 15, 0x0004, 1,
+ CLK_IS_CRITICAL),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG, "top_mfg",
+ mfg_parents, 0x0040, 0x0044, 0x0048, 16, 2, 23, 0x0004, 2),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG, "top_camtg",
+ camtg_parents, 0x0040, 0x0044, 0x0048, 24, 3, 31, 0x0004, 3),
+ /* CLK_CFG_1 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG1, "top_camtg1",
+ camtg_parents, 0x0050, 0x0054, 0x0058, 0, 3, 7, 0x0004, 4),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2, "top_camtg2",
+ camtg_parents, 0x0050, 0x0054, 0x0058, 8, 3, 15, 0x0004, 5),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3, "top_camtg3",
+ camtg_parents, 0x0050, 0x0054, 0x0058, 16, 3, 23, 0x0004, 6),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG4, "top_camtg4",
+ camtg_parents, 0x0050, 0x0054, 0x0058, 24, 3, 31, 0x0004, 7),
+ /* CLK_CFG_2 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG5, "top_camtg5",
+ camtg_parents, 0x0060, 0x0064, 0x0068, 0, 3, 7, 0x0004, 8),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG6, "top_camtg6",
+ camtg_parents, 0x0060, 0x0064, 0x0068, 8, 3, 15, 0x0004, 9),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_UART, "top_uart",
+ uart_parents, 0x0060, 0x0064, 0x0068, 16, 1, 23, 0x0004, 10),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "top_spi",
+ spi_parents, 0x0060, 0x0064, 0x0068, 24, 3, 31, 0x0004, 11),
+ /* CLK_CFG_3 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK, "top_msdc5hclk",
+ msdc5hclk_parents, 0x0070, 0x0074, 0x0078, 0, 2, 7, 0x0004, 12),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0, "top_msdc50_0",
+ msdc50_0_parents, 0x0070, 0x0074, 0x0078, 8, 3, 15, 0x0004, 13),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1, "top_msdc30_1",
+ msdc30_1_parents, 0x0070, 0x0074, 0x0078, 16, 3, 23, 0x0004, 14),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO, "top_audio",
+ audio_parents, 0x0070, 0x0074, 0x0078, 24, 2, 31, 0x0004, 15),
+ /* CLK_CFG_4 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS, "top_aud_intbus",
+ aud_intbus_parents, 0x0080, 0x0084, 0x0088, 0, 2, 7, 0x0004, 16),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1, "top_aud_1",
+ aud_1_parents, 0x0080, 0x0084, 0x0088, 8, 1, 15, 0x0004, 17),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2, "top_aud_2",
+ aud_2_parents, 0x0080, 0x0084, 0x0088, 16, 1, 23, 0x0004, 18),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1, "top_aud_engen1",
+ aud_engen1_parents, 0x0080, 0x0084, 0x0088, 24, 2, 31, 0x0004, 19),
+ /*
+ * CLK_CFG_5
+ * top_sspm is main clock in always-on co-processor, should not be closed
+ * in Linux.
+ */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN2, "top_aud_engen2",
+ aud_engen2_parents, 0x0090, 0x0094, 0x0098, 0, 2, 7, 0x0004, 20),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM, "top_disp_pwm",
+ disp_pwm_parents, 0x0090, 0x0094, 0x0098, 8, 3, 15, 0x0004, 21),
+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SSPM, "top_sspm", sspm_parents,
+ 0x0090, 0x0094, 0x0098, 16, 3, 23, 0x0004, 22,
+ CLK_IS_CRITICAL),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC, "top_dxcc",
+ dxcc_parents, 0x0090, 0x0094, 0x0098, 24, 2, 31, 0x0004, 23),
+ /*
+ * CLK_CFG_6
+ * top_spm and top_srck are main clocks in always-on co-processor.
+ */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP, "top_usb",
+ usb_parents, 0x00a0, 0x00a4, 0x00a8, 0, 2, 7, 0x0004, 24),
+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SRCK, "top_srck", srck_parents,
+ 0x00a0, 0x00a4, 0x00a8, 8, 2, 15, 0x0004, 25,
+ CLK_IS_CRITICAL),
+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM, "top_spm", spm_parents,
+ 0x00a0, 0x00a4, 0x00a8, 16, 2, 23, 0x0004, 26,
+ CLK_IS_CRITICAL),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C, "top_i2c",
+ i2c_parents, 0x00a0, 0x00a4, 0x00a8, 24, 2, 31, 0x0004, 27),
+ /* CLK_CFG_7 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM, "top_pwm",
+ pwm_parents, 0x00b0, 0x00b4, 0x00b8, 0, 2, 7, 0x0004, 28),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF, "top_seninf",
+ seninf_parents, 0x00b0, 0x00b4, 0x00b8, 8, 2, 15, 0x0004, 29),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1, "top_seninf1",
+ seninf_parents, 0x00b0, 0x00b4, 0x00b8, 16, 2, 23, 0x0004, 30),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF2, "top_seninf2",
+ seninf_parents, 0x00b0, 0x00b4, 0x00b8, 24, 2, 31, 0x0008, 0),
+ /* CLK_CFG_8 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF3, "top_seninf3",
+ seninf_parents, 0x00c0, 0x00c4, 0x00c8, 0, 2, 7, 0x0008, 1),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE, "top_aes_msdcfde",
+ aes_msdcfde_parents, 0x00c0, 0x00c4, 0x00c8, 8, 3, 15, 0x0008, 2),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PWRAP_ULPOSC, "top_pwrap_ulposc",
+ pwrap_ulposc_parents, 0x00c0, 0x00c4, 0x00c8, 16, 3, 23, 0x0008, 3),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM, "top_camtm",
+ camtm_parents, 0x00c0, 0x00c4, 0x00c8, 24, 2, 31, 0x0008, 4),
+ /* CLK_CFG_9 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC, "top_venc",
+ venc_parents, 0x00d0, 0x00d4, 0x00d8, 0, 3, 7, 0x0008, 5),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM, "top_cam",
+ isp_parents, 0x00d0, 0x00d4, 0x00d8, 8, 4, 15, 0x0008, 6),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG1, "top_img1",
+ isp_parents, 0x00d0, 0x00d4, 0x00d8, 16, 4, 23, 0x0008, 7),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE, "top_ipe",
+ isp_parents, 0x00d0, 0x00d4, 0x00d8, 24, 4, 31, 0x0008, 8),
+ /* CLK_CFG_10 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DPMAIF, "top_dpmaif",
+ dpmaif_parents, 0x00e0, 0x00e4, 0x00e8, 0, 3, 7, 0x0008, 9),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC, "top_vdec",
+ vdec_parents, 0x00e0, 0x00e4, 0x00e8, 8, 3, 15, 0x0008, 10),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP, "top_disp",
+ disp_parents, 0x00e0, 0x00e4, 0x00e8, 16, 4, 23, 0x0008, 11),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MDP, "top_mdp",
+ mdp_parents, 0x00e0, 0x00e4, 0x00e8, 24, 4, 31, 0x0008, 12),
+ /* CLK_CFG_11 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_H, "top_audio_h",
+ audio_h_parents, 0x00ec, 0x00f0, 0x00f4, 0, 2, 7, 0x0008, 13),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS, "top_ufs",
+ ufs_parents, 0x00ec, 0x00f0, 0x00f4, 8, 2, 15, 0x0008, 14),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_FDE, "top_aes_fde",
+ aes_fde_parents, 0x00ec, 0x00f0, 0x00f4, 16, 2, 23, 0x0008, 15),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIODSP, "top_audiodsp",
+ audiodsp_parents, 0x00ec, 0x00f0, 0x00f4, 24, 3, 31, 0x0008, 16),
+ /*
+ * CLK_CFG_12
+ * dvfsrc is for internal DVFS usage, should not be closed in Linux.
+ */
+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DVFSRC, "top_dvfsrc", dvfsrc_parents,
+ 0x0100, 0x0104, 0x0108, 0, 1, 7, 0x0008, 17,
+ CLK_IS_CRITICAL),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DSI_OCC, "top_dsi_occ",
+ dsi_occ_parents, 0x0100, 0x0104, 0x0108, 8, 2, 15, 0x0008, 18),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_MST, "top_spmi_mst",
+ spmi_mst_parents, 0x0100, 0x0104, 0x0108, 16, 3, 23, 0x0008, 19),
+ /* CLK_CFG_13 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINOR, "top_spinor",
+ spinor_parents, 0x0110, 0x0114, 0x0118, 0, 3, 6, 0x0008, 20),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NNA, "top_nna",
+ nna_parents, 0x0110, 0x0114, 0x0118, 7, 4, 14, 0x0008, 21),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NNA1, "top_nna1",
+ nna_parents, 0x0110, 0x0114, 0x0118, 15, 4, 22, 0x0008, 22),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NNA2, "top_nna2",
+ nna2_parents, 0x0110, 0x0114, 0x0118, 23, 4, 30, 0x0008, 23),
+ /* CLK_CFG_14 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI, "top_ssusb_xhci",
+ ssusb_parents, 0x0120, 0x0124, 0x0128, 0, 2, 5, 0x0008, 24),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_TOP_1P, "top_ssusb_1p",
+ ssusb_parents, 0x0120, 0x0124, 0x0128, 6, 2, 11, 0x0008, 25),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_1P, "top_ssusb_xhci_1p",
+ ssusb_parents, 0x0120, 0x0124, 0x0128, 12, 2, 17, 0x0008, 26),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_WPE, "top_wpe",
+ wpe_parents, 0x0120, 0x0124, 0x0128, 18, 4, 25, 0x0008, 27),
+ /* CLK_CFG_15 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI, "top_dpi",
+ dpi_parents, 0x0180, 0x0184, 0x0188, 0, 3, 6, 0x0008, 28),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_U3_OCC_250M, "top_u3_occ_250m",
+ u3_occ_250m_parents, 0x0180, 0x0184, 0x0188, 7, 1, 11, 0x0008, 29),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_U3_OCC_500M, "top_u3_occ_500m",
+ u3_occ_500m_parents, 0x0180, 0x0184, 0x0188, 12, 1, 16, 0x0008, 30),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP_BUS, "top_adsp_bus",
+ adsp_bus_parents, 0x0180, 0x0184, 0x0188, 17, 3, 23, 0x0008, 31),
+};
+
+static struct mtk_composite top_muxes[] = {
+ /* CLK_AUDDIV_0 */
+ MUX(CLK_TOP_APLL_I2S0_MCK_SEL, "apll_i2s0_mck_sel", apll_mck_parents, 0x0320, 16, 1),
+ MUX(CLK_TOP_APLL_I2S1_MCK_SEL, "apll_i2s1_mck_sel", apll_mck_parents, 0x0320, 17, 1),
+ MUX(CLK_TOP_APLL_I2S2_MCK_SEL, "apll_i2s2_mck_sel", apll_mck_parents, 0x0320, 18, 1),
+ MUX(CLK_TOP_APLL_I2S4_MCK_SEL, "apll_i2s4_mck_sel", apll_mck_parents, 0x0320, 19, 1),
+ MUX(CLK_TOP_APLL_TDMOUT_MCK_SEL, "apll_tdmout_mck_sel", apll_mck_parents,
+ 0x0320, 20, 1),
+};
+
+static const struct mtk_composite top_adj_divs[] = {
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV0, "apll12_div0", "apll_i2s0_mck_sel",
+ 0x0320, 0, 0x0328, 8, 0),
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV1, "apll12_div1", "apll_i2s1_mck_sel",
+ 0x0320, 1, 0x0328, 8, 8),
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV2, "apll12_div2", "apll_i2s2_mck_sel",
+ 0x0320, 2, 0x0328, 8, 16),
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV4, "apll12_div4", "apll_i2s4_mck_sel",
+ 0x0320, 3, 0x0328, 8, 24),
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV_TDMOUT_M, "apll12_div_tdmout_m", "apll_tdmout_mck_sel",
+ 0x0320, 4, 0x0334, 8, 0),
+};
+
+static const struct of_device_id of_match_clk_mt8186_topck[] = {
+ { .compatible = "mediatek,mt8186-topckgen", },
+ {}
+};
+
+static int clk_mt8186_topck_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+ int r;
+ void __iomem *base;
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
+ if (!clk_data)
+ return -ENOMEM;
+
+ mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
+ clk_data);
+ mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
+ mtk_clk_register_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), node,
+ &mt8186_clk_lock, clk_data);
+
+ mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
+ &mt8186_clk_lock, clk_data);
+ mtk_clk_register_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), base,
+ &mt8186_clk_lock, clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ goto unregister_clk;
+
+ return r;
+
+unregister_clk:
+ mtk_clk_unregister(clk_data);
+ mtk_free_clk_data(clk_data);
+ return r;
+}
+
+static struct platform_driver clk_mt8186_topck_drv = {
+ .probe = clk_mt8186_topck_probe,
+ .driver = {
+ .name = "clk-mt8186-topck",
+ .of_match_table = of_match_clk_mt8186_topck,
+ },
+};
+builtin_platform_driver(clk_mt8186_topck_drv);
--
2.18.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [v1 04/16] clk: mediatek: Add MT8186 topckgen clock support
2022-01-10 13:44 ` [v1 04/16] clk: mediatek: Add MT8186 topckgen " Chun-Jie Chen
@ 2022-01-10 15:50 ` AngeloGioacchino Del Regno
2022-01-10 21:13 ` kernel test robot
1 sibling, 0 replies; 39+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-01-10 15:50 UTC (permalink / raw)
To: Chun-Jie Chen, Matthias Brugger, Stephen Boyd, Nicolas Boichat,
Rob Herring
Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group
Il 10/01/22 14:44, Chun-Jie Chen ha scritto:
> Add MT8186 topckgen clock controller which provides muxes, dividers
> to handle variety clock selection in other IP blocks.
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [v1 04/16] clk: mediatek: Add MT8186 topckgen clock support
2022-01-10 13:44 ` [v1 04/16] clk: mediatek: Add MT8186 topckgen " Chun-Jie Chen
2022-01-10 15:50 ` AngeloGioacchino Del Regno
@ 2022-01-10 21:13 ` kernel test robot
1 sibling, 0 replies; 39+ messages in thread
From: kernel test robot @ 2022-01-10 21:13 UTC (permalink / raw)
To: Chun-Jie Chen, Matthias Brugger, Stephen Boyd, Nicolas Boichat,
Rob Herring
Cc: kbuild-all, linux-arm-kernel, linux-kernel, linux-mediatek,
linux-clk, devicetree, srv_heupstream
Hi Chun-Jie,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on clk/clk-next]
[also build test ERROR on robh/for-next v5.16 next-20220110]
[cannot apply to mbgg-mediatek/for-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Chun-Jie-Chen/dt-bindings-ARM-Mediatek-Add-new-document-bindings-of-MT8186-clock/20220110-224451
base: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
config: nios2-allyesconfig (https://download.01.org/0day-ci/archive/20220111/202201110556.oB2sYNXm-lkp@intel.com/config)
compiler: nios2-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/265a72ef3e3b41a62f280049219cf4efe1d79171
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Chun-Jie-Chen/dt-bindings-ARM-Mediatek-Add-new-document-bindings-of-MT8186-clock/20220110-224451
git checkout 265a72ef3e3b41a62f280049219cf4efe1d79171
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=nios2 SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
drivers/clk/mediatek/clk-mt8186-topckgen.c: In function 'clk_mt8186_topck_probe':
>> drivers/clk/mediatek/clk-mt8186-topckgen.c:725:9: error: implicit declaration of function 'mtk_clk_unregister'; did you mean 'devm_clk_unregister'? [-Werror=implicit-function-declaration]
725 | mtk_clk_unregister(clk_data);
| ^~~~~~~~~~~~~~~~~~
| devm_clk_unregister
cc1: some warnings being treated as errors
vim +725 drivers/clk/mediatek/clk-mt8186-topckgen.c
691
692 static int clk_mt8186_topck_probe(struct platform_device *pdev)
693 {
694 struct clk_onecell_data *clk_data;
695 struct device_node *node = pdev->dev.of_node;
696 int r;
697 void __iomem *base;
698
699 base = devm_platform_ioremap_resource(pdev, 0);
700 if (IS_ERR(base))
701 return PTR_ERR(base);
702
703 clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
704 if (!clk_data)
705 return -ENOMEM;
706
707 mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
708 clk_data);
709 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
710 mtk_clk_register_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), node,
711 &mt8186_clk_lock, clk_data);
712
713 mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
714 &mt8186_clk_lock, clk_data);
715 mtk_clk_register_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), base,
716 &mt8186_clk_lock, clk_data);
717
718 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
719 if (r)
720 goto unregister_clk;
721
722 return r;
723
724 unregister_clk:
> 725 mtk_clk_unregister(clk_data);
726 mtk_free_clk_data(clk_data);
727 return r;
728 }
729
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
^ permalink raw reply [flat|nested] 39+ messages in thread
* [v1 05/16] clk: mediatek: Add MT8186 infrastructure clock support
[not found] <20220110134416.5191-1-chun-jie.chen@mediatek.com>
` (3 preceding siblings ...)
2022-01-10 13:44 ` [v1 04/16] clk: mediatek: Add MT8186 topckgen " Chun-Jie Chen
@ 2022-01-10 13:44 ` Chun-Jie Chen
2022-01-10 15:50 ` AngeloGioacchino Del Regno
2022-01-10 13:44 ` [v1 06/16] clk: mediatek: Add MT8186 apmixedsys " Chun-Jie Chen
` (10 subsequent siblings)
15 siblings, 1 reply; 39+ messages in thread
From: Chun-Jie Chen @ 2022-01-10 13:44 UTC (permalink / raw)
To: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring
Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group,
Chun-Jie Chen
Add MT8186 infrastructure clock controller which provides
clock gate control for basic IP like pwm, uart, spi and so on.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
drivers/clk/mediatek/Makefile | 2 +-
drivers/clk/mediatek/clk-mt8186-infra_ao.c | 215 +++++++++++++++++++++
2 files changed, 216 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mediatek/clk-mt8186-infra_ao.c
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index a5166f0860bd..54957094843e 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -67,7 +67,7 @@ obj-$(CONFIG_COMMON_CLK_MT8183_MFGCFG) += clk-mt8183-mfgcfg.o
obj-$(CONFIG_COMMON_CLK_MT8183_MMSYS) += clk-mt8183-mm.o
obj-$(CONFIG_COMMON_CLK_MT8183_VDECSYS) += clk-mt8183-vdec.o
obj-$(CONFIG_COMMON_CLK_MT8183_VENCSYS) += clk-mt8183-venc.o
-obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o
+obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt8186-infra_ao.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8186-infra_ao.c b/drivers/clk/mediatek/clk-mt8186-infra_ao.c
new file mode 100644
index 000000000000..cd2bc99bc9bf
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8186-infra_ao.c
@@ -0,0 +1,215 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2022 MediaTek Inc.
+// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+#include <dt-bindings/clock/mt8186-clk.h>
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+static const struct mtk_gate_regs infra_ao0_cg_regs = {
+ .set_ofs = 0x80,
+ .clr_ofs = 0x84,
+ .sta_ofs = 0x90,
+};
+
+static const struct mtk_gate_regs infra_ao1_cg_regs = {
+ .set_ofs = 0x88,
+ .clr_ofs = 0x8c,
+ .sta_ofs = 0x94,
+};
+
+static const struct mtk_gate_regs infra_ao2_cg_regs = {
+ .set_ofs = 0xa4,
+ .clr_ofs = 0xa8,
+ .sta_ofs = 0xac,
+};
+
+static const struct mtk_gate_regs infra_ao3_cg_regs = {
+ .set_ofs = 0xc0,
+ .clr_ofs = 0xc4,
+ .sta_ofs = 0xc8,
+};
+
+#define GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, _flag) \
+ GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \
+ &mtk_clk_gate_ops_setclr, _flag)
+
+#define GATE_INFRA_AO0(_id, _name, _parent, _shift) \
+ GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0)
+
+#define GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, _flag) \
+ GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao1_cg_regs, _shift, \
+ &mtk_clk_gate_ops_setclr, _flag)
+
+#define GATE_INFRA_AO1(_id, _name, _parent, _shift) \
+ GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0)
+
+#define GATE_INFRA_AO2_FLAGS(_id, _name, _parent, _shift, _flag) \
+ GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao2_cg_regs, _shift, \
+ &mtk_clk_gate_ops_setclr, _flag)
+
+#define GATE_INFRA_AO2(_id, _name, _parent, _shift) \
+ GATE_INFRA_AO2_FLAGS(_id, _name, _parent, _shift, 0)
+
+ #define GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, _flag) \
+ GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao3_cg_regs, _shift, \
+ &mtk_clk_gate_ops_setclr, _flag)
+
+#define GATE_INFRA_AO3(_id, _name, _parent, _shift) \
+ GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, 0)
+
+static const struct mtk_gate infra_ao_clks[] = {
+ /* INFRA_AO0 */
+ GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_TMR, "infra_ao_pmic_tmr", "top_pwrap_ulposc", 0),
+ GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_AP, "infra_ao_pmic_ap", "top_pwrap_ulposc", 1),
+ GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_MD, "infra_ao_pmic_md", "top_pwrap_ulposc", 2),
+ GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_CONN, "infra_ao_pmic_conn", "top_pwrap_ulposc", 3),
+ /* infra_ao_scp_core are main clock in always-on co-processor. */
+ GATE_INFRA_AO0_FLAGS(CLK_INFRA_AO_SCP_CORE,
+ "infra_ao_scp_core", "top_scp", 4, CLK_IS_CRITICAL),
+ /* infra_ao_sej is main clock is for secure engine with JTAG support */
+ GATE_INFRA_AO0_FLAGS(CLK_INFRA_AO_SEJ,
+ "infra_ao_sej", "top_axi", 5, CLK_IS_CRITICAL),
+ GATE_INFRA_AO0(CLK_INFRA_AO_APXGPT, "infra_ao_apxgpt", "top_axi", 6),
+ GATE_INFRA_AO0(CLK_INFRA_AO_ICUSB, "infra_ao_icusb", "top_axi", 8),
+ GATE_INFRA_AO0(CLK_INFRA_AO_GCE, "infra_ao_gce", "top_axi", 9),
+ GATE_INFRA_AO0(CLK_INFRA_AO_THERM, "infra_ao_therm", "top_axi", 10),
+ GATE_INFRA_AO0(CLK_INFRA_AO_I2C_AP, "infra_ao_i2c_ap", "top_i2c", 11),
+ GATE_INFRA_AO0(CLK_INFRA_AO_I2C_CCU, "infra_ao_i2c_ccu", "top_i2c", 12),
+ GATE_INFRA_AO0(CLK_INFRA_AO_I2C_SSPM, "infra_ao_i2c_sspm", "top_i2c", 13),
+ GATE_INFRA_AO0(CLK_INFRA_AO_I2C_RSV, "infra_ao_i2c_rsv", "top_i2c", 14),
+ GATE_INFRA_AO0(CLK_INFRA_AO_PWM_HCLK, "infra_ao_pwm_hclk", "top_axi", 15),
+ GATE_INFRA_AO0(CLK_INFRA_AO_PWM1, "infra_ao_pwm1", "top_pwm", 16),
+ GATE_INFRA_AO0(CLK_INFRA_AO_PWM2, "infra_ao_pwm2", "top_pwm", 17),
+ GATE_INFRA_AO0(CLK_INFRA_AO_PWM3, "infra_ao_pwm3", "top_pwm", 18),
+ GATE_INFRA_AO0(CLK_INFRA_AO_PWM4, "infra_ao_pwm4", "top_pwm", 19),
+ GATE_INFRA_AO0(CLK_INFRA_AO_PWM5, "infra_ao_pwm5", "top_pwm", 20),
+ GATE_INFRA_AO0(CLK_INFRA_AO_PWM, "infra_ao_pwm", "top_pwm", 21),
+ GATE_INFRA_AO0(CLK_INFRA_AO_UART0, "infra_ao_uart0", "top_uart", 22),
+ GATE_INFRA_AO0(CLK_INFRA_AO_UART1, "infra_ao_uart1", "top_uart", 23),
+ GATE_INFRA_AO0(CLK_INFRA_AO_UART2, "infra_ao_uart2", "top_uart", 24),
+ GATE_INFRA_AO0(CLK_INFRA_AO_GCE_26M, "infra_ao_gce_26m", "clk26m", 27),
+ GATE_INFRA_AO0(CLK_INFRA_AO_CQ_DMA_FPC, "infra_ao_dma", "top_axi", 28),
+ GATE_INFRA_AO0(CLK_INFRA_AO_BTIF, "infra_ao_btif", "top_axi", 31),
+ /* INFRA_AO1 */
+ GATE_INFRA_AO1(CLK_INFRA_AO_SPI0, "infra_ao_spi0", "top_spi", 1),
+ GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0, "infra_ao_msdc0", "top_msdc5hclk", 2),
+ GATE_INFRA_AO1(CLK_INFRA_AO_MSDCFDE, "infra_ao_msdcfde", "top_aes_msdcfde", 3),
+ GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1, "infra_ao_msdc1", "top_axi", 4),
+ /* infra_ao_dvfsrc is for internal DVFS usage, should not be handled by Linux */
+ GATE_INFRA_AO1_FLAGS(CLK_INFRA_AO_DVFSRC,
+ "infra_ao_dvfsrc", "top_dvfsrc", 7, CLK_IS_CRITICAL),
+ GATE_INFRA_AO1(CLK_INFRA_AO_GCPU, "infra_ao_gcpu", "top_axi", 8),
+ GATE_INFRA_AO1(CLK_INFRA_AO_TRNG, "infra_ao_trng", "top_axi", 9),
+ GATE_INFRA_AO1(CLK_INFRA_AO_AUXADC, "infra_ao_auxadc", "clk26m", 10),
+ GATE_INFRA_AO1(CLK_INFRA_AO_CPUM, "infra_ao_cpum", "top_axi", 11),
+ GATE_INFRA_AO1(CLK_INFRA_AO_CCIF1_AP, "infra_ao_ccif1_ap", "top_axi", 12),
+ GATE_INFRA_AO1(CLK_INFRA_AO_CCIF1_MD, "infra_ao_ccif1_md", "top_axi", 13),
+ GATE_INFRA_AO1(CLK_INFRA_AO_AUXADC_MD, "infra_ao_auxadc_md", "clk26m", 14),
+ GATE_INFRA_AO1(CLK_INFRA_AO_AP_DMA, "infra_ao_ap_dma", "top_axi", 18),
+ GATE_INFRA_AO1(CLK_INFRA_AO_XIU, "infra_ao_xiu", "top_axi", 19),
+ /* infra_ao_device_apc is for device access permission control module */
+ GATE_INFRA_AO1_FLAGS(CLK_INFRA_AO_DEVICE_APC,
+ "infra_ao_dapc", "top_axi", 20, CLK_IS_CRITICAL),
+ GATE_INFRA_AO1(CLK_INFRA_AO_CCIF_AP, "infra_ao_ccif_ap", "top_axi", 23),
+ GATE_INFRA_AO1(CLK_INFRA_AO_DEBUGTOP, "infra_ao_debugtop", "top_axi", 24),
+ GATE_INFRA_AO1(CLK_INFRA_AO_AUDIO, "infra_ao_audio", "top_axi", 25),
+ GATE_INFRA_AO1(CLK_INFRA_AO_CCIF_MD, "infra_ao_ccif_md", "top_axi", 26),
+ GATE_INFRA_AO1(CLK_INFRA_AO_DXCC_SEC_CORE, "infra_ao_secore", "top_dxcc", 27),
+ GATE_INFRA_AO1(CLK_INFRA_AO_DXCC_AO, "infra_ao_dxcc_ao", "top_dxcc", 28),
+ GATE_INFRA_AO1(CLK_INFRA_AO_IMP_IIC, "infra_ao_imp_iic", "top_axi", 29),
+ GATE_INFRA_AO1(CLK_INFRA_AO_DRAMC_F26M, "infra_ao_dramc26", "clk26m", 31),
+ /* INFRA_AO2 */
+ GATE_INFRA_AO2(CLK_INFRA_AO_RG_PWM_FBCLK6, "infra_ao_pwm_fbclk6", "clk26m", 0),
+ GATE_INFRA_AO2(CLK_INFRA_AO_SSUSB_TOP_HCLK, "infra_ao_ssusb_hclk", "top_axi", 1),
+ GATE_INFRA_AO2(CLK_INFRA_AO_DISP_PWM, "infra_ao_disp_pwm", "top_disp_pwm", 2),
+ GATE_INFRA_AO2(CLK_INFRA_AO_CLDMA_BCLK, "infra_ao_cldmabclk", "top_axi", 3),
+ GATE_INFRA_AO2(CLK_INFRA_AO_AUDIO_26M_BCLK, "infra_ao_audio26m", "clk26m", 4),
+ GATE_INFRA_AO2(CLK_INFRA_AO_SSUSB_TOP_P1_HCLK, "infra_ao_ssusb_p1_hclk", "top_axi", 5),
+ GATE_INFRA_AO2(CLK_INFRA_AO_SPI1, "infra_ao_spi1", "top_spi", 6),
+ GATE_INFRA_AO2(CLK_INFRA_AO_I2C4, "infra_ao_i2c4", "top_i2c", 7),
+ GATE_INFRA_AO2(CLK_INFRA_AO_MODEM_TEMP_SHARE, "infra_ao_mdtemp", "clk26m", 8),
+ GATE_INFRA_AO2(CLK_INFRA_AO_SPI2, "infra_ao_spi2", "top_spi", 9),
+ GATE_INFRA_AO2(CLK_INFRA_AO_SPI3, "infra_ao_spi3", "top_spi", 10),
+ GATE_INFRA_AO2(CLK_INFRA_AO_SSUSB_TOP_REF, "infra_ao_ssusb_ref", "clk26m", 11),
+ GATE_INFRA_AO2(CLK_INFRA_AO_SSUSB_TOP_XHCI, "infra_ao_ssusb_xhci", "top_ssusb_xhci", 12),
+ GATE_INFRA_AO2(CLK_INFRA_AO_SSUSB_TOP_P1_REF, "infra_ao_ssusb_p1_ref", "clk26m", 13),
+ GATE_INFRA_AO2(CLK_INFRA_AO_SSUSB_TOP_P1_XHCI,
+ "infra_ao_ssusb_p1_xhci", "top_ssusb_xhci_1p", 14),
+ /* infra_ao_sspm is main clock in co-processor, should not be closed in Linux. */
+ GATE_INFRA_AO2_FLAGS(CLK_INFRA_AO_SSPM, "infra_ao_sspm", "top_sspm", 15, CLK_IS_CRITICAL),
+ GATE_INFRA_AO2(CLK_INFRA_AO_SSUSB_TOP_P1_SYS,
+ "infra_ao_ssusb_p1_sys", "top_ssusb_1p", 16),
+ GATE_INFRA_AO2(CLK_INFRA_AO_I2C5, "infra_ao_i2c5", "top_i2c", 18),
+ GATE_INFRA_AO2(CLK_INFRA_AO_I2C5_ARBITER, "infra_ao_i2c5a", "top_i2c", 19),
+ GATE_INFRA_AO2(CLK_INFRA_AO_I2C5_IMM, "infra_ao_i2c5_imm", "top_i2c", 20),
+ GATE_INFRA_AO2(CLK_INFRA_AO_I2C1_ARBITER, "infra_ao_i2c1a", "top_i2c", 21),
+ GATE_INFRA_AO2(CLK_INFRA_AO_I2C1_IMM, "infra_ao_i2c1_imm", "top_i2c", 22),
+ GATE_INFRA_AO2(CLK_INFRA_AO_I2C2_ARBITER, "infra_ao_i2c2a", "top_i2c", 23),
+ GATE_INFRA_AO2(CLK_INFRA_AO_I2C2_IMM, "infra_ao_i2c2_imm", "top_i2c", 24),
+ GATE_INFRA_AO2(CLK_INFRA_AO_SPI4, "infra_ao_spi4", "top_spi", 25),
+ GATE_INFRA_AO2(CLK_INFRA_AO_SPI5, "infra_ao_spi5", "top_spi", 26),
+ GATE_INFRA_AO2(CLK_INFRA_AO_CQ_DMA, "infra_ao_cq_dma", "top_axi", 27),
+ GATE_INFRA_AO2(CLK_INFRA_AO_BIST2FPC, "infra_ao_bist2fpc", "f_bist2fpc_ck", 28),
+ /* INFRA_AO3 */
+ GATE_INFRA_AO3(CLK_INFRA_AO_MSDC0_SELF, "infra_ao_msdc0sf", "top_msdc50_0", 0),
+ GATE_INFRA_AO3(CLK_INFRA_AO_SPINOR, "infra_ao_spinor", "top_spinor", 1),
+ /*
+ * infra_ao_sspm_26m/infra_ao_sspm_32k are main clocks in co-processor,
+ * should not be closed in Linux.
+ */
+ GATE_INFRA_AO3_FLAGS(CLK_INFRA_AO_SSPM_26M_SELF, "infra_ao_sspm_26m", "clk26m", 3,
+ CLK_IS_CRITICAL),
+ GATE_INFRA_AO3_FLAGS(CLK_INFRA_AO_SSPM_32K_SELF, "infra_ao_sspm_32k", "clk32k", 4,
+ CLK_IS_CRITICAL),
+ GATE_INFRA_AO3(CLK_INFRA_AO_I2C6, "infra_ao_i2c6", "top_i2c", 6),
+ GATE_INFRA_AO3(CLK_INFRA_AO_AP_MSDC0, "infra_ao_ap_msdc0", "top_axi", 7),
+ GATE_INFRA_AO3(CLK_INFRA_AO_MD_MSDC0, "infra_ao_md_msdc0", "top_axi", 8),
+ GATE_INFRA_AO3(CLK_INFRA_AO_MSDC0_SRC, "infra_ao_msdc0_clk", "top_msdc50_0", 9),
+ GATE_INFRA_AO3(CLK_INFRA_AO_MSDC1_SRC, "infra_ao_msdc1_clk", "top_msdc30_1", 10),
+ /* infra_ao_sej_f13m is main clock is for secure engine with JTAG support */
+ GATE_INFRA_AO3_FLAGS(CLK_INFRA_AO_SEJ_F13M,
+ "infra_ao_sej_f13m", "clk26m", 15, CLK_IS_CRITICAL),
+ /* infra_ao_aes_top0_bclk is for secure encryption */
+ GATE_INFRA_AO3_FLAGS(CLK_INFRA_AO_AES_TOP0_BCLK,
+ "infra_ao_aes_top0_bclk", "top_axi", 16, CLK_IS_CRITICAL),
+ GATE_INFRA_AO3(CLK_INFRA_AO_MCU_PM_BCLK, "infra_ao_mcu_pm_bclk", "top_axi", 17),
+ GATE_INFRA_AO3(CLK_INFRA_AO_CCIF2_AP, "infra_ao_ccif2_ap", "top_axi", 18),
+ GATE_INFRA_AO3(CLK_INFRA_AO_CCIF2_MD, "infra_ao_ccif2_md", "top_axi", 19),
+ GATE_INFRA_AO3(CLK_INFRA_AO_CCIF3_AP, "infra_ao_ccif3_ap", "top_axi", 20),
+ GATE_INFRA_AO3(CLK_INFRA_AO_CCIF3_MD, "infra_ao_ccif3_md", "top_axi", 21),
+ GATE_INFRA_AO3(CLK_INFRA_AO_FADSP_26M, "infra_ao_fadsp_26m", "clk26m", 22),
+ GATE_INFRA_AO3(CLK_INFRA_AO_FADSP_32K, "infra_ao_fadsp_32k", "clk32k", 23),
+ GATE_INFRA_AO3(CLK_INFRA_AO_CCIF4_AP, "infra_ao_ccif4_ap", "top_axi", 24),
+ GATE_INFRA_AO3(CLK_INFRA_AO_CCIF4_MD, "infra_ao_ccif4_md", "top_axi", 25),
+ GATE_INFRA_AO3(CLK_INFRA_AO_FADSP, "infra_ao_fadsp", "top_audiodsp", 27),
+ GATE_INFRA_AO3(CLK_INFRA_AO_FLASHIF_133M, "infra_ao_flashif_133m", "top_axi", 28),
+ GATE_INFRA_AO3(CLK_INFRA_AO_FLASHIF_66M, "infra_ao_flashif_66m", "top_axi", 29),
+};
+
+static const struct mtk_clk_desc infra_ao_desc = {
+ .clks = infra_ao_clks,
+ .num_clks = ARRAY_SIZE(infra_ao_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8186_infra_ao[] = {
+ {
+ .compatible = "mediatek,mt8186-infracfg_ao",
+ .data = &infra_ao_desc,
+ }, {
+ /* sentinel */
+ }
+};
+
+static struct platform_driver clk_mt8186_infra_ao_drv = {
+ .probe = mtk_clk_simple_probe,
+ .driver = {
+ .name = "clk-mt8186-infra-ao",
+ .of_match_table = of_match_clk_mt8186_infra_ao,
+ },
+};
+builtin_platform_driver(clk_mt8186_infra_ao_drv);
--
2.18.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [v1 05/16] clk: mediatek: Add MT8186 infrastructure clock support
2022-01-10 13:44 ` [v1 05/16] clk: mediatek: Add MT8186 infrastructure " Chun-Jie Chen
@ 2022-01-10 15:50 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 39+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-01-10 15:50 UTC (permalink / raw)
To: Chun-Jie Chen, Matthias Brugger, Stephen Boyd, Nicolas Boichat,
Rob Herring
Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group
Il 10/01/22 14:44, Chun-Jie Chen ha scritto:
> Add MT8186 infrastructure clock controller which provides
> clock gate control for basic IP like pwm, uart, spi and so on.
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
^ permalink raw reply [flat|nested] 39+ messages in thread
* [v1 06/16] clk: mediatek: Add MT8186 apmixedsys clock support
[not found] <20220110134416.5191-1-chun-jie.chen@mediatek.com>
` (4 preceding siblings ...)
2022-01-10 13:44 ` [v1 05/16] clk: mediatek: Add MT8186 infrastructure " Chun-Jie Chen
@ 2022-01-10 13:44 ` Chun-Jie Chen
2022-01-10 15:50 ` AngeloGioacchino Del Regno
2022-01-11 0:06 ` kernel test robot
2022-01-10 13:44 ` [v1 07/16] clk: mediatek: Add MT8186 imp i2c wrapper " Chun-Jie Chen
` (9 subsequent siblings)
15 siblings, 2 replies; 39+ messages in thread
From: Chun-Jie Chen @ 2022-01-10 13:44 UTC (permalink / raw)
To: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring
Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group,
Chun-Jie Chen
Add MT8186 apmixedsys clock controller which provides Plls
generated from SoC.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
drivers/clk/mediatek/Makefile | 3 +-
drivers/clk/mediatek/clk-mt8186-apmixedsys.c | 114 +++++++++++++++++++
2 files changed, 116 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mediatek/clk-mt8186-apmixedsys.c
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 54957094843e..b139acdff591 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -67,7 +67,8 @@ obj-$(CONFIG_COMMON_CLK_MT8183_MFGCFG) += clk-mt8183-mfgcfg.o
obj-$(CONFIG_COMMON_CLK_MT8183_MMSYS) += clk-mt8183-mm.o
obj-$(CONFIG_COMMON_CLK_MT8183_VDECSYS) += clk-mt8183-vdec.o
obj-$(CONFIG_COMMON_CLK_MT8183_VENCSYS) += clk-mt8183-venc.o
-obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt8186-infra_ao.o
+obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt8186-infra_ao.o \
+ clk-mt8186-apmixedsys.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8186-apmixedsys.c b/drivers/clk/mediatek/clk-mt8186-apmixedsys.c
new file mode 100644
index 000000000000..50bb04e9953d
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8186-apmixedsys.c
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2022 MediaTek Inc.
+// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
+
+#include "clk-mtk.h"
+
+#include <dt-bindings/clock/mt8186-clk.h>
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#define MT8186_PLL_FMAX (3800UL * MHZ)
+#define MT8186_PLL_FMIN (1500UL * MHZ)
+#define MT8186_INTEGER_BITS (8)
+
+#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
+ _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \
+ _tuner_reg, _tuner_en_reg, _tuner_en_bit, \
+ _pcw_reg) { \
+ .id = _id, \
+ .name = _name, \
+ .reg = _reg, \
+ .pwr_reg = _pwr_reg, \
+ .en_mask = _en_mask, \
+ .flags = _flags, \
+ .rst_bar_mask = _rst_bar_mask, \
+ .fmax = MT8186_PLL_FMAX, \
+ .fmin = MT8186_PLL_FMIN, \
+ .pcwbits = _pcwbits, \
+ .pcwibits = MT8186_INTEGER_BITS, \
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .tuner_reg = _tuner_reg, \
+ .tuner_en_reg = _tuner_en_reg, \
+ .tuner_en_bit = _tuner_en_bit, \
+ .pcw_reg = _pcw_reg, \
+ .pcw_shift = 0, \
+ .pcw_chg_reg = 0, \
+ .en_reg = 0, \
+ .pll_en_bit = 0, \
+ }
+
+static const struct mtk_pll_data plls[] = {
+ /*
+ * armpll_ll/armpll_bl/ccipll are main clock source of AP MCU,
+ * should not be closed in Linux world.
+ */
+ PLL(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0204, 0x0210, 0,
+ PLL_AO, 0, 22, 0x0208, 24, 0, 0, 0, 0x0208),
+ PLL(CLK_APMIXED_ARMPLL_BL, "armpll_bl", 0x0214, 0x0220, 0,
+ PLL_AO, 0, 22, 0x0218, 24, 0, 0, 0, 0x0218),
+ PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x0224, 0x0230, 0,
+ PLL_AO, 0, 22, 0x0228, 24, 0, 0, 0, 0x0228),
+ PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0244, 0x0250, 0xff000000,
+ HAVE_RST_BAR, BIT(23), 22, 0x0248, 24, 0, 0, 0, 0x0248),
+ PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0324, 0x0330, 0xff000000,
+ HAVE_RST_BAR, BIT(23), 22, 0x0328, 24, 0, 0, 0, 0x0328),
+ PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x038C, 0x0398, 0,
+ 0, 0, 22, 0x0390, 24, 0, 0, 0, 0x0390),
+ PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0254, 0x0260, 0,
+ 0, 0, 22, 0x0258, 24, 0, 0, 0, 0x0258),
+ PLL(CLK_APMIXED_NNAPLL, "nnapll", 0x035C, 0x0368, 0,
+ 0, 0, 22, 0x0360, 24, 0, 0, 0, 0x0360),
+ PLL(CLK_APMIXED_NNA2PLL, "nna2pll", 0x036C, 0x0378, 0,
+ 0, 0, 22, 0x0370, 24, 0, 0, 0, 0x0370),
+ PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x0304, 0x0310, 0,
+ 0, 0, 22, 0x0308, 24, 0, 0, 0, 0x0308),
+ PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0314, 0x0320, 0,
+ 0, 0, 22, 0x0318, 24, 0, 0, 0, 0x0318),
+ PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0264, 0x0270, 0,
+ 0, 0, 22, 0x0268, 24, 0, 0, 0, 0x0268),
+ PLL(CLK_APMIXED_APLL1, "apll1", 0x0334, 0x0344, 0,
+ 0, 0, 32, 0x0338, 24, 0x0040, 0x000C, 0, 0x033C),
+ PLL(CLK_APMIXED_APLL2, "apll2", 0x0348, 0x0358, 0,
+ 0, 0, 32, 0x034C, 24, 0x0044, 0x000C, 5, 0x0350),
+};
+
+static const struct of_device_id of_match_clk_mt8186_apmixed[] = {
+ { .compatible = "mediatek,mt8186-apmixedsys", },
+ {}
+};
+
+static int clk_mt8186_apmixed_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+ int r;
+
+ clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
+ if (!clk_data)
+ return -ENOMEM;
+
+ mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ goto unregister_clk;
+
+ return r;
+
+unregister_clk:
+ mtk_clk_unregister(clk_data);
+ mtk_free_clk_data(clk_data);
+ return r;
+}
+
+static struct platform_driver clk_mt8186_apmixed_drv = {
+ .probe = clk_mt8186_apmixed_probe,
+ .driver = {
+ .name = "clk-mt8186-apmixed",
+ .of_match_table = of_match_clk_mt8186_apmixed,
+ },
+};
+builtin_platform_driver(clk_mt8186_apmixed_drv);
--
2.18.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [v1 06/16] clk: mediatek: Add MT8186 apmixedsys clock support
2022-01-10 13:44 ` [v1 06/16] clk: mediatek: Add MT8186 apmixedsys " Chun-Jie Chen
@ 2022-01-10 15:50 ` AngeloGioacchino Del Regno
2022-01-11 0:06 ` kernel test robot
1 sibling, 0 replies; 39+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-01-10 15:50 UTC (permalink / raw)
To: Chun-Jie Chen, Matthias Brugger, Stephen Boyd, Nicolas Boichat,
Rob Herring
Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group
Il 10/01/22 14:44, Chun-Jie Chen ha scritto:
> Add MT8186 apmixedsys clock controller which provides Plls
> generated from SoC.
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [v1 06/16] clk: mediatek: Add MT8186 apmixedsys clock support
2022-01-10 13:44 ` [v1 06/16] clk: mediatek: Add MT8186 apmixedsys " Chun-Jie Chen
2022-01-10 15:50 ` AngeloGioacchino Del Regno
@ 2022-01-11 0:06 ` kernel test robot
1 sibling, 0 replies; 39+ messages in thread
From: kernel test robot @ 2022-01-11 0:06 UTC (permalink / raw)
To: Chun-Jie Chen, Matthias Brugger, Stephen Boyd, Nicolas Boichat,
Rob Herring
Cc: kbuild-all, linux-arm-kernel, linux-kernel, linux-mediatek,
linux-clk, devicetree, srv_heupstream
Hi Chun-Jie,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on clk/clk-next]
[also build test ERROR on robh/for-next v5.16 next-20220110]
[cannot apply to mbgg-mediatek/for-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Chun-Jie-Chen/dt-bindings-ARM-Mediatek-Add-new-document-bindings-of-MT8186-clock/20220110-224451
base: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
config: nios2-allyesconfig (https://download.01.org/0day-ci/archive/20220111/202201110701.jdDbg8yY-lkp@intel.com/config)
compiler: nios2-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/2b9fcab7333544a52a4e5fd9e42764e1f1e7a7b1
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Chun-Jie-Chen/dt-bindings-ARM-Mediatek-Add-new-document-bindings-of-MT8186-clock/20220110-224451
git checkout 2b9fcab7333544a52a4e5fd9e42764e1f1e7a7b1
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=nios2 SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
drivers/clk/mediatek/clk-mt8186-apmixedsys.c: In function 'clk_mt8186_apmixed_probe':
>> drivers/clk/mediatek/clk-mt8186-apmixedsys.c:102:9: error: implicit declaration of function 'mtk_clk_unregister'; did you mean 'devm_clk_unregister'? [-Werror=implicit-function-declaration]
102 | mtk_clk_unregister(clk_data);
| ^~~~~~~~~~~~~~~~~~
| devm_clk_unregister
cc1: some warnings being treated as errors
vim +102 drivers/clk/mediatek/clk-mt8186-apmixedsys.c
82
83 static int clk_mt8186_apmixed_probe(struct platform_device *pdev)
84 {
85 struct clk_onecell_data *clk_data;
86 struct device_node *node = pdev->dev.of_node;
87 int r;
88
89 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
90 if (!clk_data)
91 return -ENOMEM;
92
93 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
94
95 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
96 if (r)
97 goto unregister_clk;
98
99 return r;
100
101 unregister_clk:
> 102 mtk_clk_unregister(clk_data);
103 mtk_free_clk_data(clk_data);
104 return r;
105 }
106
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
^ permalink raw reply [flat|nested] 39+ messages in thread
* [v1 07/16] clk: mediatek: Add MT8186 imp i2c wrapper clock support
[not found] <20220110134416.5191-1-chun-jie.chen@mediatek.com>
` (5 preceding siblings ...)
2022-01-10 13:44 ` [v1 06/16] clk: mediatek: Add MT8186 apmixedsys " Chun-Jie Chen
@ 2022-01-10 13:44 ` Chun-Jie Chen
2022-01-10 15:50 ` AngeloGioacchino Del Regno
2022-01-10 13:44 ` [v1 08/16] clk: mediatek: Add MT8186 mfgsys " Chun-Jie Chen
` (8 subsequent siblings)
15 siblings, 1 reply; 39+ messages in thread
From: Chun-Jie Chen @ 2022-01-10 13:44 UTC (permalink / raw)
To: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring
Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group,
Chun-Jie Chen
Add MT8186 imp i2c wrapper clock controllers which provide clock gate
control in i2c IP blocks.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
drivers/clk/mediatek/Makefile | 2 +-
.../clk/mediatek/clk-mt8186-imp_iic_wrap.c | 66 +++++++++++++++++++
2 files changed, 67 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mediatek/clk-mt8186-imp_iic_wrap.c
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index b139acdff591..8f8240e4d8d0 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -68,7 +68,7 @@ obj-$(CONFIG_COMMON_CLK_MT8183_MMSYS) += clk-mt8183-mm.o
obj-$(CONFIG_COMMON_CLK_MT8183_VDECSYS) += clk-mt8183-vdec.o
obj-$(CONFIG_COMMON_CLK_MT8183_VENCSYS) += clk-mt8183-venc.o
obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt8186-infra_ao.o \
- clk-mt8186-apmixedsys.o
+ clk-mt8186-apmixedsys.o clk-mt8186-imp_iic_wrap.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8186-imp_iic_wrap.c b/drivers/clk/mediatek/clk-mt8186-imp_iic_wrap.c
new file mode 100644
index 000000000000..18aee488df69
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8186-imp_iic_wrap.c
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2022 MediaTek Inc.
+// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+#include <dt-bindings/clock/mt8186-clk.h>
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+static const struct mtk_gate_regs imp_iic_wrap_cg_regs = {
+ .set_ofs = 0xe08,
+ .clr_ofs = 0xe04,
+ .sta_ofs = 0xe00,
+};
+
+#define GATE_IMP_IIC_WRAP(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &imp_iic_wrap_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate imp_iic_wrap_clks[] = {
+ GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0,
+ "imp_iic_wrap_ap_clock_i2c0", "infra_ao_i2c_ap", 0),
+ GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1,
+ "imp_iic_wrap_ap_clock_i2c1", "infra_ao_i2c_ap", 1),
+ GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2,
+ "imp_iic_wrap_ap_clock_i2c2", "infra_ao_i2c_ap", 2),
+ GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3,
+ "imp_iic_wrap_ap_clock_i2c3", "infra_ao_i2c_ap", 3),
+ GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4,
+ "imp_iic_wrap_ap_clock_i2c4", "infra_ao_i2c_ap", 4),
+ GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5,
+ "imp_iic_wrap_ap_clock_i2c5", "infra_ao_i2c_ap", 5),
+ GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6,
+ "imp_iic_wrap_ap_clock_i2c6", "infra_ao_i2c_ap", 6),
+ GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7,
+ "imp_iic_wrap_ap_clock_i2c7", "infra_ao_i2c_ap", 7),
+ GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8,
+ "imp_iic_wrap_ap_clock_i2c8", "infra_ao_i2c_ap", 8),
+ GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9,
+ "imp_iic_wrap_ap_clock_i2c9", "infra_ao_i2c_ap", 9),
+};
+
+static const struct mtk_clk_desc imp_iic_wrap_desc = {
+ .clks = imp_iic_wrap_clks,
+ .num_clks = ARRAY_SIZE(imp_iic_wrap_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8186_imp_iic_wrap[] = {
+ {
+ .compatible = "mediatek,mt8186-imp_iic_wrap",
+ .data = &imp_iic_wrap_desc,
+ }, {
+ /* sentinel */
+ }
+};
+
+static struct platform_driver clk_mt8186_imp_iic_wrap_drv = {
+ .probe = mtk_clk_simple_probe,
+ .driver = {
+ .name = "clk-mt8186-imp_iic_wrap",
+ .of_match_table = of_match_clk_mt8186_imp_iic_wrap,
+ },
+};
+builtin_platform_driver(clk_mt8186_imp_iic_wrap_drv);
--
2.18.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [v1 07/16] clk: mediatek: Add MT8186 imp i2c wrapper clock support
2022-01-10 13:44 ` [v1 07/16] clk: mediatek: Add MT8186 imp i2c wrapper " Chun-Jie Chen
@ 2022-01-10 15:50 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 39+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-01-10 15:50 UTC (permalink / raw)
To: Chun-Jie Chen, Matthias Brugger, Stephen Boyd, Nicolas Boichat,
Rob Herring
Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group
Il 10/01/22 14:44, Chun-Jie Chen ha scritto:
> Add MT8186 imp i2c wrapper clock controllers which provide clock gate
> control in i2c IP blocks.
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
^ permalink raw reply [flat|nested] 39+ messages in thread
* [v1 08/16] clk: mediatek: Add MT8186 mfgsys clock support
[not found] <20220110134416.5191-1-chun-jie.chen@mediatek.com>
` (6 preceding siblings ...)
2022-01-10 13:44 ` [v1 07/16] clk: mediatek: Add MT8186 imp i2c wrapper " Chun-Jie Chen
@ 2022-01-10 13:44 ` Chun-Jie Chen
2022-01-10 15:50 ` AngeloGioacchino Del Regno
2022-01-10 13:44 ` [v1 09/16] clk: mediatek: Add MT8186 mmsys " Chun-Jie Chen
` (7 subsequent siblings)
15 siblings, 1 reply; 39+ messages in thread
From: Chun-Jie Chen @ 2022-01-10 13:44 UTC (permalink / raw)
To: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring
Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group,
Chun-Jie Chen
Add MT8186 mfg clock controller which provides clock gate
control for GPU.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
drivers/clk/mediatek/Makefile | 3 +-
drivers/clk/mediatek/clk-mt8186-mfg.c | 47 +++++++++++++++++++++++++++
2 files changed, 49 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mediatek/clk-mt8186-mfg.c
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 8f8240e4d8d0..9477b5694c32 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -68,7 +68,8 @@ obj-$(CONFIG_COMMON_CLK_MT8183_MMSYS) += clk-mt8183-mm.o
obj-$(CONFIG_COMMON_CLK_MT8183_VDECSYS) += clk-mt8183-vdec.o
obj-$(CONFIG_COMMON_CLK_MT8183_VENCSYS) += clk-mt8183-venc.o
obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt8186-infra_ao.o \
- clk-mt8186-apmixedsys.o clk-mt8186-imp_iic_wrap.o
+ clk-mt8186-apmixedsys.o clk-mt8186-imp_iic_wrap.o \
+ clk-mt8186-mfg.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8186-mfg.c b/drivers/clk/mediatek/clk-mt8186-mfg.c
new file mode 100644
index 000000000000..63417a040a7e
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8186-mfg.c
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2022 MediaTek Inc.
+// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+#include <dt-bindings/clock/mt8186-clk.h>
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+static const struct mtk_gate_regs mfg_cg_regs = {
+ .set_ofs = 0x4,
+ .clr_ofs = 0x8,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_MFG(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate mfg_clks[] = {
+ GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "top_mfg", 0),
+};
+
+static const struct mtk_clk_desc mfg_desc = {
+ .clks = mfg_clks,
+ .num_clks = ARRAY_SIZE(mfg_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8186_mfg[] = {
+ {
+ .compatible = "mediatek,mt8186-mfgsys",
+ .data = &mfg_desc,
+ }, {
+ /* sentinel */
+ }
+};
+
+static struct platform_driver clk_mt8186_mfg_drv = {
+ .probe = mtk_clk_simple_probe,
+ .driver = {
+ .name = "clk-mt8186-mfg",
+ .of_match_table = of_match_clk_mt8186_mfg,
+ },
+};
+builtin_platform_driver(clk_mt8186_mfg_drv);
--
2.18.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [v1 08/16] clk: mediatek: Add MT8186 mfgsys clock support
2022-01-10 13:44 ` [v1 08/16] clk: mediatek: Add MT8186 mfgsys " Chun-Jie Chen
@ 2022-01-10 15:50 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 39+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-01-10 15:50 UTC (permalink / raw)
To: Chun-Jie Chen, Matthias Brugger, Stephen Boyd, Nicolas Boichat,
Rob Herring
Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group
Il 10/01/22 14:44, Chun-Jie Chen ha scritto:
> Add MT8186 mfg clock controller which provides clock gate
> control for GPU.
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
^ permalink raw reply [flat|nested] 39+ messages in thread
* [v1 09/16] clk: mediatek: Add MT8186 mmsys clock support
[not found] <20220110134416.5191-1-chun-jie.chen@mediatek.com>
` (7 preceding siblings ...)
2022-01-10 13:44 ` [v1 08/16] clk: mediatek: Add MT8186 mfgsys " Chun-Jie Chen
@ 2022-01-10 13:44 ` Chun-Jie Chen
2022-01-10 15:50 ` AngeloGioacchino Del Regno
2022-01-10 13:44 ` [v1 10/16] clk: mediatek: Add MT8186 wpesys " Chun-Jie Chen
` (6 subsequent siblings)
15 siblings, 1 reply; 39+ messages in thread
From: Chun-Jie Chen @ 2022-01-10 13:44 UTC (permalink / raw)
To: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring
Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group,
Chun-Jie Chen
Add MT8186 mmsys clock controller which provides clock gate
control in video system. This is integrated with mtk-mmsys
driver which will populate device by platform_device_register_data
to start mmsys clock driver.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
drivers/clk/mediatek/Makefile | 2 +-
drivers/clk/mediatek/clk-mt8186-mm.c | 97 ++++++++++++++++++++++++++++
2 files changed, 98 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mediatek/clk-mt8186-mm.c
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 9477b5694c32..b34d89e757cb 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -69,7 +69,7 @@ obj-$(CONFIG_COMMON_CLK_MT8183_VDECSYS) += clk-mt8183-vdec.o
obj-$(CONFIG_COMMON_CLK_MT8183_VENCSYS) += clk-mt8183-venc.o
obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt8186-infra_ao.o \
clk-mt8186-apmixedsys.o clk-mt8186-imp_iic_wrap.o \
- clk-mt8186-mfg.o
+ clk-mt8186-mfg.o clk-mt8186-mm.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8186-mm.c b/drivers/clk/mediatek/clk-mt8186-mm.c
new file mode 100644
index 000000000000..1c1a9ae1d0c2
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8186-mm.c
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2022 MediaTek Inc.
+// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+#include <dt-bindings/clock/mt8186-clk.h>
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+static const struct mtk_gate_regs mm0_cg_regs = {
+ .set_ofs = 0x104,
+ .clr_ofs = 0x108,
+ .sta_ofs = 0x100,
+};
+
+static const struct mtk_gate_regs mm1_cg_regs = {
+ .set_ofs = 0x1a4,
+ .clr_ofs = 0x1a8,
+ .sta_ofs = 0x1a0,
+};
+
+#define GATE_MM0(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+#define GATE_MM1(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate mm_clks[] = {
+ /* MM0 */
+ GATE_MM0(CLK_MM_DISP_MUTEX0, "mm_disp_mutex0", "top_disp", 0),
+ GATE_MM0(CLK_MM_APB_MM_BUS, "mm_apb_mm_bus", "top_disp", 1),
+ GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "top_disp", 2),
+ GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "top_disp", 3),
+ GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "top_disp", 4),
+ GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "top_disp", 5),
+ GATE_MM0(CLK_MM_DISP_RSZ0, "mm_disp_rsz0", "top_disp", 7),
+ GATE_MM0(CLK_MM_DISP_AAL0, "mm_disp_aal0", "top_disp", 8),
+ GATE_MM0(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0", "top_disp", 9),
+ GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "top_disp", 10),
+ GATE_MM0(CLK_MM_SMI_INFRA, "mm_smi_infra", "top_disp", 11),
+ GATE_MM0(CLK_MM_DISP_DSC_WRAP0, "mm_disp_dsc_wrap0", "top_disp", 12),
+ GATE_MM0(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0", "top_disp", 13),
+ GATE_MM0(CLK_MM_DISP_POSTMASK0, "mm_disp_postmask0", "top_disp", 14),
+ GATE_MM0(CLK_MM_DISP_DITHER0, "mm_disp_dither0", "top_disp", 16),
+ GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "top_disp", 17),
+ GATE_MM0(CLK_MM_DSI0, "mm_dsi0", "top_disp", 19),
+ GATE_MM0(CLK_MM_DISP_FAKE_ENG0, "mm_disp_fake_eng0", "top_disp", 20),
+ GATE_MM0(CLK_MM_DISP_FAKE_ENG1, "mm_disp_fake_eng1", "top_disp", 21),
+ GATE_MM0(CLK_MM_SMI_GALS, "mm_smi_gals", "top_disp", 22),
+ GATE_MM0(CLK_MM_SMI_IOMMU, "mm_smi_iommu", "top_disp", 24),
+ GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "top_disp", 25),
+ GATE_MM0(CLK_MM_DISP_DPI, "mm_disp_dpi", "top_disp", 26),
+ /* MM1 */
+ GATE_MM1(CLK_MM_DSI0_DSI_CK_DOMAIN, "mm_dsi0_dsi_domain", "top_disp", 0),
+ GATE_MM1(CLK_MM_DISP_26M, "mm_disp_26m_ck", "top_disp", 10),
+};
+
+static int clk_mt8186_mm_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *node = dev->parent->of_node;
+ struct clk_onecell_data *clk_data;
+ int r;
+
+ clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
+ if (!clk_data)
+ return -ENOMEM;
+
+ r = mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), clk_data);
+ if (r)
+ goto free_mm_data;
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ goto unregister_clk;
+
+ return r;
+
+unregister_clk:
+ mtk_clk_unregister(clk_data);
+
+free_mm_data:
+ mtk_free_clk_data(clk_data);
+ return r;
+}
+
+
+static struct platform_driver clk_mt8186_mm_drv = {
+ .probe = clk_mt8186_mm_probe,
+ .driver = {
+ .name = "clk-mt8186-mm",
+ },
+};
+builtin_platform_driver(clk_mt8186_mm_drv);
--
2.18.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [v1 09/16] clk: mediatek: Add MT8186 mmsys clock support
2022-01-10 13:44 ` [v1 09/16] clk: mediatek: Add MT8186 mmsys " Chun-Jie Chen
@ 2022-01-10 15:50 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 39+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-01-10 15:50 UTC (permalink / raw)
To: Chun-Jie Chen, Matthias Brugger, Stephen Boyd, Nicolas Boichat,
Rob Herring
Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group
Il 10/01/22 14:44, Chun-Jie Chen ha scritto:
> Add MT8186 mmsys clock controller which provides clock gate
> control in video system. This is integrated with mtk-mmsys
> driver which will populate device by platform_device_register_data
> to start mmsys clock driver.
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
^ permalink raw reply [flat|nested] 39+ messages in thread
* [v1 10/16] clk: mediatek: Add MT8186 wpesys clock support
[not found] <20220110134416.5191-1-chun-jie.chen@mediatek.com>
` (8 preceding siblings ...)
2022-01-10 13:44 ` [v1 09/16] clk: mediatek: Add MT8186 mmsys " Chun-Jie Chen
@ 2022-01-10 13:44 ` Chun-Jie Chen
2022-01-10 15:50 ` AngeloGioacchino Del Regno
2022-01-10 13:44 ` [v1 11/16] clk: mediatek: Add MT8186 imgsys " Chun-Jie Chen
` (5 subsequent siblings)
15 siblings, 1 reply; 39+ messages in thread
From: Chun-Jie Chen @ 2022-01-10 13:44 UTC (permalink / raw)
To: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring
Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group,
Chun-Jie Chen
Add MT8186 wpesys clock controllers which provide clock gate
control in Wrapping Engine.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
drivers/clk/mediatek/Makefile | 2 +-
drivers/clk/mediatek/clk-mt8186-wpe.c | 50 +++++++++++++++++++++++++++
2 files changed, 51 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mediatek/clk-mt8186-wpe.c
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index b34d89e757cb..380ab37ea151 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -69,7 +69,7 @@ obj-$(CONFIG_COMMON_CLK_MT8183_VDECSYS) += clk-mt8183-vdec.o
obj-$(CONFIG_COMMON_CLK_MT8183_VENCSYS) += clk-mt8183-venc.o
obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt8186-infra_ao.o \
clk-mt8186-apmixedsys.o clk-mt8186-imp_iic_wrap.o \
- clk-mt8186-mfg.o clk-mt8186-mm.o
+ clk-mt8186-mfg.o clk-mt8186-mm.o clk-mt8186-wpe.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8186-wpe.c b/drivers/clk/mediatek/clk-mt8186-wpe.c
new file mode 100644
index 000000000000..677c78571ecc
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8186-wpe.c
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2022 MediaTek Inc.
+// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+#include <dt-bindings/clock/mt8186-clk.h>
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+static const struct mtk_gate_regs wpe_cg_regs = {
+ .set_ofs = 0x0,
+ .clr_ofs = 0x0,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_WPE(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &wpe_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
+
+static const struct mtk_gate wpe_clks[] = {
+ GATE_WPE(CLK_WPE_CK_EN, "wpe", "top_wpe", 17),
+ GATE_WPE(CLK_WPE_SMI_LARB8_CK_EN, "wpe_smi_larb8", "top_wpe", 19),
+ GATE_WPE(CLK_WPE_SYS_EVENT_TX_CK_EN, "wpe_sys_event_tx", "top_wpe", 20),
+ GATE_WPE(CLK_WPE_SMI_LARB8_PCLK_EN, "wpe_smi_larb8_p_en", "top_wpe", 25),
+};
+
+static const struct mtk_clk_desc wpe_desc = {
+ .clks = wpe_clks,
+ .num_clks = ARRAY_SIZE(wpe_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8186_wpe[] = {
+ {
+ .compatible = "mediatek,mt8186-wpesys",
+ .data = &wpe_desc,
+ }, {
+ /* sentinel */
+ }
+};
+
+static struct platform_driver clk_mt8186_wpe_drv = {
+ .probe = mtk_clk_simple_probe,
+ .driver = {
+ .name = "clk-mt8186-wpe",
+ .of_match_table = of_match_clk_mt8186_wpe,
+ },
+};
+builtin_platform_driver(clk_mt8186_wpe_drv);
--
2.18.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [v1 10/16] clk: mediatek: Add MT8186 wpesys clock support
2022-01-10 13:44 ` [v1 10/16] clk: mediatek: Add MT8186 wpesys " Chun-Jie Chen
@ 2022-01-10 15:50 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 39+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-01-10 15:50 UTC (permalink / raw)
To: Chun-Jie Chen, Matthias Brugger, Stephen Boyd, Nicolas Boichat,
Rob Herring
Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group
Il 10/01/22 14:44, Chun-Jie Chen ha scritto:
> Add MT8186 wpesys clock controllers which provide clock gate
> control in Wrapping Engine.
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
^ permalink raw reply [flat|nested] 39+ messages in thread
* [v1 11/16] clk: mediatek: Add MT8186 imgsys clock support
[not found] <20220110134416.5191-1-chun-jie.chen@mediatek.com>
` (9 preceding siblings ...)
2022-01-10 13:44 ` [v1 10/16] clk: mediatek: Add MT8186 wpesys " Chun-Jie Chen
@ 2022-01-10 13:44 ` Chun-Jie Chen
2022-01-10 15:49 ` AngeloGioacchino Del Regno
2022-01-10 13:44 ` [v1 12/16] clk: mediatek: Add MT8186 vdecsys " Chun-Jie Chen
` (4 subsequent siblings)
15 siblings, 1 reply; 39+ messages in thread
From: Chun-Jie Chen @ 2022-01-10 13:44 UTC (permalink / raw)
To: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring
Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group,
Chun-Jie Chen
Add MT8186 imgsys clock controllers which provide clock gate
control for image IP blocks.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
drivers/clk/mediatek/Makefile | 3 +-
drivers/clk/mediatek/clk-mt8186-img.c | 67 +++++++++++++++++++++++++++
2 files changed, 69 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mediatek/clk-mt8186-img.c
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 380ab37ea151..9f89e36d9ddf 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -69,7 +69,8 @@ obj-$(CONFIG_COMMON_CLK_MT8183_VDECSYS) += clk-mt8183-vdec.o
obj-$(CONFIG_COMMON_CLK_MT8183_VENCSYS) += clk-mt8183-venc.o
obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt8186-infra_ao.o \
clk-mt8186-apmixedsys.o clk-mt8186-imp_iic_wrap.o \
- clk-mt8186-mfg.o clk-mt8186-mm.o clk-mt8186-wpe.o
+ clk-mt8186-mfg.o clk-mt8186-mm.o clk-mt8186-wpe.o \
+ clk-mt8186-img.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8186-img.c b/drivers/clk/mediatek/clk-mt8186-img.c
new file mode 100644
index 000000000000..d84f137867a2
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8186-img.c
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2022 MediaTek Inc.
+// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+#include <dt-bindings/clock/mt8186-clk.h>
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+static const struct mtk_gate_regs img_cg_regs = {
+ .set_ofs = 0x4,
+ .clr_ofs = 0x8,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_IMG(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate img1_clks[] = {
+ GATE_IMG(CLK_IMG1_LARB9_IMG1, "img1_larb9_img1", "top_img1", 0),
+ GATE_IMG(CLK_IMG1_LARB10_IMG1, "img1_larb10_img1", "top_img1", 1),
+ GATE_IMG(CLK_IMG1_DIP, "img1_dip", "top_img1", 2),
+ GATE_IMG(CLK_IMG1_GALS_IMG1, "img1_gals_img1", "top_img1", 12),
+};
+
+static const struct mtk_gate img2_clks[] = {
+ GATE_IMG(CLK_IMG2_LARB9_IMG2, "img2_larb9_img2", "top_img1", 0),
+ GATE_IMG(CLK_IMG2_LARB10_IMG2, "img2_larb10_img2", "top_img1", 1),
+ GATE_IMG(CLK_IMG2_MFB, "img2_mfb", "top_img1", 6),
+ GATE_IMG(CLK_IMG2_WPE, "img2_wpe", "top_img1", 7),
+ GATE_IMG(CLK_IMG2_MSS, "img2_mss", "top_img1", 8),
+ GATE_IMG(CLK_IMG2_GALS_IMG2, "img2_gals_img2", "top_img1", 12),
+};
+
+static const struct mtk_clk_desc img1_desc = {
+ .clks = img1_clks,
+ .num_clks = ARRAY_SIZE(img1_clks),
+};
+
+static const struct mtk_clk_desc img2_desc = {
+ .clks = img2_clks,
+ .num_clks = ARRAY_SIZE(img2_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8186_img[] = {
+ {
+ .compatible = "mediatek,mt8186-imgsys1",
+ .data = &img1_desc,
+ }, {
+ .compatible = "mediatek,mt8186-imgsys2",
+ .data = &img2_desc,
+ }, {
+ /* sentinel */
+ }
+};
+
+static struct platform_driver clk_mt8186_img_drv = {
+ .probe = mtk_clk_simple_probe,
+ .driver = {
+ .name = "clk-mt8186-img",
+ .of_match_table = of_match_clk_mt8186_img,
+ },
+};
+builtin_platform_driver(clk_mt8186_img_drv);
--
2.18.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [v1 11/16] clk: mediatek: Add MT8186 imgsys clock support
2022-01-10 13:44 ` [v1 11/16] clk: mediatek: Add MT8186 imgsys " Chun-Jie Chen
@ 2022-01-10 15:49 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 39+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-01-10 15:49 UTC (permalink / raw)
To: Chun-Jie Chen, Matthias Brugger, Stephen Boyd, Nicolas Boichat,
Rob Herring
Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group
Il 10/01/22 14:44, Chun-Jie Chen ha scritto:
> Add MT8186 imgsys clock controllers which provide clock gate
> control for image IP blocks.
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
^ permalink raw reply [flat|nested] 39+ messages in thread
* [v1 12/16] clk: mediatek: Add MT8186 vdecsys clock support
[not found] <20220110134416.5191-1-chun-jie.chen@mediatek.com>
` (10 preceding siblings ...)
2022-01-10 13:44 ` [v1 11/16] clk: mediatek: Add MT8186 imgsys " Chun-Jie Chen
@ 2022-01-10 13:44 ` Chun-Jie Chen
2022-01-10 15:49 ` AngeloGioacchino Del Regno
2022-01-10 13:44 ` [v1 13/16] clk: mediatek: Add MT8186 vencsys " Chun-Jie Chen
` (3 subsequent siblings)
15 siblings, 1 reply; 39+ messages in thread
From: Chun-Jie Chen @ 2022-01-10 13:44 UTC (permalink / raw)
To: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring
Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group,
Chun-Jie Chen
Add MT8186 vdec clock controller which provide clock gate
control for video decoder.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
drivers/clk/mediatek/Makefile | 2 +-
drivers/clk/mediatek/clk-mt8186-vdec.c | 87 ++++++++++++++++++++++++++
2 files changed, 88 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mediatek/clk-mt8186-vdec.c
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 9f89e36d9ddf..e29e6a661115 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -70,7 +70,7 @@ obj-$(CONFIG_COMMON_CLK_MT8183_VENCSYS) += clk-mt8183-venc.o
obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt8186-infra_ao.o \
clk-mt8186-apmixedsys.o clk-mt8186-imp_iic_wrap.o \
clk-mt8186-mfg.o clk-mt8186-mm.o clk-mt8186-wpe.o \
- clk-mt8186-img.o
+ clk-mt8186-img.o clk-mt8186-vdec.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8186-vdec.c b/drivers/clk/mediatek/clk-mt8186-vdec.c
new file mode 100644
index 000000000000..f0aa2c491a32
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8186-vdec.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2022 MediaTek Inc.
+// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8186-clk.h>
+
+static const struct mtk_gate_regs vdec0_cg_regs = {
+ .set_ofs = 0x0,
+ .clr_ofs = 0x4,
+ .sta_ofs = 0x0,
+};
+
+static const struct mtk_gate_regs vdec1_cg_regs = {
+ .set_ofs = 0x190,
+ .clr_ofs = 0x190,
+ .sta_ofs = 0x190,
+};
+
+static const struct mtk_gate_regs vdec2_cg_regs = {
+ .set_ofs = 0x200,
+ .clr_ofs = 0x204,
+ .sta_ofs = 0x200,
+};
+
+static const struct mtk_gate_regs vdec3_cg_regs = {
+ .set_ofs = 0x8,
+ .clr_ofs = 0xc,
+ .sta_ofs = 0x8,
+};
+
+#define GATE_VDEC0(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
+
+#define GATE_VDEC1(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
+
+#define GATE_VDEC2(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
+
+#define GATE_VDEC3(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &vdec3_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
+
+static const struct mtk_gate vdec_clks[] = {
+ /* VDEC0 */
+ GATE_VDEC0(CLK_VDEC_CKEN, "vdec_cken", "top_vdec", 0),
+ GATE_VDEC0(CLK_VDEC_ACTIVE, "vdec_active", "top_vdec", 4),
+ GATE_VDEC0(CLK_VDEC_CKEN_ENG, "vdec_cken_eng", "top_vdec", 8),
+ /* VDEC1 */
+ GATE_VDEC1(CLK_VDEC_MINI_MDP_CKEN_CFG_RG, "vdec_mini_mdp_cken_cfg_rg", "top_vdec", 0),
+ /* VDEC2 */
+ GATE_VDEC2(CLK_VDEC_LAT_CKEN, "vdec_lat_cken", "top_vdec", 0),
+ GATE_VDEC2(CLK_VDEC_LAT_ACTIVE, "vdec_lat_active", "top_vdec", 4),
+ GATE_VDEC2(CLK_VDEC_LAT_CKEN_ENG, "vdec_lat_cken_eng", "top_vdec", 8),
+ /* VDEC3 */
+ GATE_VDEC3(CLK_VDEC_LARB1_CKEN, "vdec_larb1_cken", "top_vdec", 0),
+};
+
+static const struct mtk_clk_desc vdec_desc = {
+ .clks = vdec_clks,
+ .num_clks = ARRAY_SIZE(vdec_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8186_vdec[] = {
+ {
+ .compatible = "mediatek,mt8186-vdecsys",
+ .data = &vdec_desc,
+ }, {
+ /* sentinel */
+ }
+};
+
+static struct platform_driver clk_mt8186_vdec_drv = {
+ .probe = mtk_clk_simple_probe,
+ .driver = {
+ .name = "clk-mt8186-vdec",
+ .of_match_table = of_match_clk_mt8186_vdec,
+ },
+};
+builtin_platform_driver(clk_mt8186_vdec_drv);
--
2.18.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [v1 12/16] clk: mediatek: Add MT8186 vdecsys clock support
2022-01-10 13:44 ` [v1 12/16] clk: mediatek: Add MT8186 vdecsys " Chun-Jie Chen
@ 2022-01-10 15:49 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 39+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-01-10 15:49 UTC (permalink / raw)
To: Chun-Jie Chen, Matthias Brugger, Stephen Boyd, Nicolas Boichat,
Rob Herring
Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group
Il 10/01/22 14:44, Chun-Jie Chen ha scritto:
> Add MT8186 vdec clock controller which provide clock gate
> control for video decoder.
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
^ permalink raw reply [flat|nested] 39+ messages in thread
* [v1 13/16] clk: mediatek: Add MT8186 vencsys clock support
[not found] <20220110134416.5191-1-chun-jie.chen@mediatek.com>
` (11 preceding siblings ...)
2022-01-10 13:44 ` [v1 12/16] clk: mediatek: Add MT8186 vdecsys " Chun-Jie Chen
@ 2022-01-10 13:44 ` Chun-Jie Chen
2022-01-10 15:49 ` AngeloGioacchino Del Regno
2022-01-10 13:44 ` [v1 14/16] clk: mediatek: Add MT8186 camsys " Chun-Jie Chen
` (2 subsequent siblings)
15 siblings, 1 reply; 39+ messages in thread
From: Chun-Jie Chen @ 2022-01-10 13:44 UTC (permalink / raw)
To: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring
Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group,
Chun-Jie Chen
Add MT8186 vencsys clock controller which provide clock gate
control for video encoder.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
drivers/clk/mediatek/Makefile | 2 +-
drivers/clk/mediatek/clk-mt8186-venc.c | 50 ++++++++++++++++++++++++++
2 files changed, 51 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mediatek/clk-mt8186-venc.c
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index e29e6a661115..c5d5a10734d0 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -70,7 +70,7 @@ obj-$(CONFIG_COMMON_CLK_MT8183_VENCSYS) += clk-mt8183-venc.o
obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt8186-infra_ao.o \
clk-mt8186-apmixedsys.o clk-mt8186-imp_iic_wrap.o \
clk-mt8186-mfg.o clk-mt8186-mm.o clk-mt8186-wpe.o \
- clk-mt8186-img.o clk-mt8186-vdec.o
+ clk-mt8186-img.o clk-mt8186-vdec.o clk-mt8186-venc.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8186-venc.c b/drivers/clk/mediatek/clk-mt8186-venc.c
new file mode 100644
index 000000000000..4cd69f9ebf76
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8186-venc.c
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2022 MediaTek Inc.
+// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+#include <dt-bindings/clock/mt8186-clk.h>
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+static const struct mtk_gate_regs venc_cg_regs = {
+ .set_ofs = 0x4,
+ .clr_ofs = 0x8,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_VENC(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
+
+static const struct mtk_gate venc_clks[] = {
+ GATE_VENC(CLK_VENC_CKE0_LARB, "venc_cke0_larb", "top_venc", 0),
+ GATE_VENC(CLK_VENC_CKE1_VENC, "venc_cke1_venc", "top_venc", 4),
+ GATE_VENC(CLK_VENC_CKE2_JPGENC, "venc_cke2_jpgenc", "top_venc", 8),
+ GATE_VENC(CLK_VENC_CKE5_GALS, "venc_cke5_gals", "top_venc", 28),
+};
+
+static const struct mtk_clk_desc venc_desc = {
+ .clks = venc_clks,
+ .num_clks = ARRAY_SIZE(venc_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8186_venc[] = {
+ {
+ .compatible = "mediatek,mt8186-vencsys",
+ .data = &venc_desc,
+ }, {
+ /* sentinel */
+ }
+};
+
+static struct platform_driver clk_mt8186_venc_drv = {
+ .probe = mtk_clk_simple_probe,
+ .driver = {
+ .name = "clk-mt8186-venc",
+ .of_match_table = of_match_clk_mt8186_venc,
+ },
+};
+builtin_platform_driver(clk_mt8186_venc_drv);
--
2.18.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [v1 13/16] clk: mediatek: Add MT8186 vencsys clock support
2022-01-10 13:44 ` [v1 13/16] clk: mediatek: Add MT8186 vencsys " Chun-Jie Chen
@ 2022-01-10 15:49 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 39+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-01-10 15:49 UTC (permalink / raw)
To: Chun-Jie Chen, Matthias Brugger, Stephen Boyd, Nicolas Boichat,
Rob Herring
Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group
Il 10/01/22 14:44, Chun-Jie Chen ha scritto:
> Add MT8186 vencsys clock controller which provide clock gate
> control for video encoder.
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
^ permalink raw reply [flat|nested] 39+ messages in thread
* [v1 14/16] clk: mediatek: Add MT8186 camsys clock support
[not found] <20220110134416.5191-1-chun-jie.chen@mediatek.com>
` (12 preceding siblings ...)
2022-01-10 13:44 ` [v1 13/16] clk: mediatek: Add MT8186 vencsys " Chun-Jie Chen
@ 2022-01-10 13:44 ` Chun-Jie Chen
2022-01-10 15:49 ` AngeloGioacchino Del Regno
2022-01-10 13:44 ` [v1 15/16] clk: mediatek: Add MT8186 mdpsys " Chun-Jie Chen
2022-01-10 13:44 ` [v1 16/16] clk: mediatek: Add MT8186 ipesys " Chun-Jie Chen
15 siblings, 1 reply; 39+ messages in thread
From: Chun-Jie Chen @ 2022-01-10 13:44 UTC (permalink / raw)
To: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring
Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group,
Chun-Jie Chen
Add MT8186 camsys clock controllers which provide clock gate
control for camera IP blocks.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
drivers/clk/mediatek/Makefile | 3 +-
drivers/clk/mediatek/clk-mt8186-cam.c | 89 +++++++++++++++++++++++++++
2 files changed, 91 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mediatek/clk-mt8186-cam.c
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index c5d5a10734d0..9190e17602eb 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -70,7 +70,8 @@ obj-$(CONFIG_COMMON_CLK_MT8183_VENCSYS) += clk-mt8183-venc.o
obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt8186-infra_ao.o \
clk-mt8186-apmixedsys.o clk-mt8186-imp_iic_wrap.o \
clk-mt8186-mfg.o clk-mt8186-mm.o clk-mt8186-wpe.o \
- clk-mt8186-img.o clk-mt8186-vdec.o clk-mt8186-venc.o
+ clk-mt8186-img.o clk-mt8186-vdec.o clk-mt8186-venc.o \
+ clk-mt8186-cam.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8186-cam.c b/drivers/clk/mediatek/clk-mt8186-cam.c
new file mode 100644
index 000000000000..5552fe5d428f
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8186-cam.c
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2022 MediaTek Inc.
+// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+#include <dt-bindings/clock/mt8186-clk.h>
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+static const struct mtk_gate_regs cam_cg_regs = {
+ .set_ofs = 0x4,
+ .clr_ofs = 0x8,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_CAM(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate cam_clks[] = {
+ GATE_CAM(CLK_CAM_LARB13, "cam_larb13", "top_cam", 0),
+ GATE_CAM(CLK_CAM_DFP_VAD, "cam_dfp_vad", "top_cam", 1),
+ GATE_CAM(CLK_CAM_LARB14, "cam_larb14", "top_cam", 2),
+ GATE_CAM(CLK_CAM, "cam", "top_cam", 6),
+ GATE_CAM(CLK_CAMTG, "camtg", "top_cam", 7),
+ GATE_CAM(CLK_CAM_SENINF, "cam_seninf", "top_cam", 8),
+ GATE_CAM(CLK_CAMSV1, "camsv1", "top_cam", 10),
+ GATE_CAM(CLK_CAMSV2, "camsv2", "top_cam", 11),
+ GATE_CAM(CLK_CAMSV3, "camsv3", "top_cam", 12),
+ GATE_CAM(CLK_CAM_CCU0, "cam_ccu0", "top_cam", 13),
+ GATE_CAM(CLK_CAM_CCU1, "cam_ccu1", "top_cam", 14),
+ GATE_CAM(CLK_CAM_MRAW0, "cam_mraw0", "top_cam", 15),
+ GATE_CAM(CLK_CAM_FAKE_ENG, "cam_fake_eng", "top_cam", 17),
+ GATE_CAM(CLK_CAM_CCU_GALS, "cam_ccu_gals", "top_cam", 18),
+ GATE_CAM(CLK_CAM2MM_GALS, "cam2mm_gals", "top_cam", 19),
+};
+
+static const struct mtk_gate cam_rawa_clks[] = {
+ GATE_CAM(CLK_CAM_RAWA_LARBX_RAWA, "cam_rawa_larbx_rawa", "top_cam", 0),
+ GATE_CAM(CLK_CAM_RAWA, "cam_rawa", "top_cam", 1),
+ GATE_CAM(CLK_CAM_RAWA_CAMTG_RAWA, "cam_rawa_camtg_rawa", "top_cam", 2),
+};
+
+static const struct mtk_gate cam_rawb_clks[] = {
+ GATE_CAM(CLK_CAM_RAWB_LARBX_RAWB, "cam_rawb_larbx_rawb", "top_cam", 0),
+ GATE_CAM(CLK_CAM_RAWB, "cam_rawb", "top_cam", 1),
+ GATE_CAM(CLK_CAM_RAWB_CAMTG_RAWB, "cam_rawb_camtg_rawb", "top_cam", 2),
+};
+
+static const struct mtk_clk_desc cam_desc = {
+ .clks = cam_clks,
+ .num_clks = ARRAY_SIZE(cam_clks),
+};
+
+static const struct mtk_clk_desc cam_rawa_desc = {
+ .clks = cam_rawa_clks,
+ .num_clks = ARRAY_SIZE(cam_rawa_clks),
+};
+
+static const struct mtk_clk_desc cam_rawb_desc = {
+ .clks = cam_rawb_clks,
+ .num_clks = ARRAY_SIZE(cam_rawb_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8186_cam[] = {
+ {
+ .compatible = "mediatek,mt8186-camsys",
+ .data = &cam_desc,
+ }, {
+ .compatible = "mediatek,mt8186-camsys_rawa",
+ .data = &cam_rawa_desc,
+ }, {
+ .compatible = "mediatek,mt8186-camsys_rawb",
+ .data = &cam_rawb_desc,
+ }, {
+ /* sentinel */
+ }
+};
+
+static struct platform_driver clk_mt8186_cam_drv = {
+ .probe = mtk_clk_simple_probe,
+ .driver = {
+ .name = "clk-mt8186-cam",
+ .of_match_table = of_match_clk_mt8186_cam,
+ },
+};
+builtin_platform_driver(clk_mt8186_cam_drv);
--
2.18.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [v1 14/16] clk: mediatek: Add MT8186 camsys clock support
2022-01-10 13:44 ` [v1 14/16] clk: mediatek: Add MT8186 camsys " Chun-Jie Chen
@ 2022-01-10 15:49 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 39+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-01-10 15:49 UTC (permalink / raw)
To: Chun-Jie Chen, Matthias Brugger, Stephen Boyd, Nicolas Boichat,
Rob Herring
Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group
Il 10/01/22 14:44, Chun-Jie Chen ha scritto:
> Add MT8186 camsys clock controllers which provide clock gate
> control for camera IP blocks.
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
^ permalink raw reply [flat|nested] 39+ messages in thread
* [v1 15/16] clk: mediatek: Add MT8186 mdpsys clock support
[not found] <20220110134416.5191-1-chun-jie.chen@mediatek.com>
` (13 preceding siblings ...)
2022-01-10 13:44 ` [v1 14/16] clk: mediatek: Add MT8186 camsys " Chun-Jie Chen
@ 2022-01-10 13:44 ` Chun-Jie Chen
2022-01-10 15:49 ` AngeloGioacchino Del Regno
2022-01-10 13:44 ` [v1 16/16] clk: mediatek: Add MT8186 ipesys " Chun-Jie Chen
15 siblings, 1 reply; 39+ messages in thread
From: Chun-Jie Chen @ 2022-01-10 13:44 UTC (permalink / raw)
To: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring
Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group,
Chun-Jie Chen
Add MT8186 mdpsys clock controller which provides clock gate
control in Multimedia Data Path.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
drivers/clk/mediatek/Makefile | 2 +-
drivers/clk/mediatek/clk-mt8186-mdp.c | 79 +++++++++++++++++++++++++++
2 files changed, 80 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mediatek/clk-mt8186-mdp.c
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 9190e17602eb..7320df02356c 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -71,7 +71,7 @@ obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt
clk-mt8186-apmixedsys.o clk-mt8186-imp_iic_wrap.o \
clk-mt8186-mfg.o clk-mt8186-mm.o clk-mt8186-wpe.o \
clk-mt8186-img.o clk-mt8186-vdec.o clk-mt8186-venc.o \
- clk-mt8186-cam.o
+ clk-mt8186-cam.o clk-mt8186-mdp.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8186-mdp.c b/drivers/clk/mediatek/clk-mt8186-mdp.c
new file mode 100644
index 000000000000..62f2f23c284b
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8186-mdp.c
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2022 MediaTek Inc.
+// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+#include <dt-bindings/clock/mt8186-clk.h>
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+static const struct mtk_gate_regs mdp0_cg_regs = {
+ .set_ofs = 0x104,
+ .clr_ofs = 0x108,
+ .sta_ofs = 0x100,
+};
+
+static const struct mtk_gate_regs mdp2_cg_regs = {
+ .set_ofs = 0x124,
+ .clr_ofs = 0x128,
+ .sta_ofs = 0x120,
+};
+
+#define GATE_MDP0(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &mdp0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+#define GATE_MDP2(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &mdp2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate mdp_clks[] = {
+ /* MDP0 */
+ GATE_MDP0(CLK_MDP_RDMA0, "mdp_rdma0", "top_mdp", 0),
+ GATE_MDP0(CLK_MDP_TDSHP0, "mdp_tdshp0", "top_mdp", 1),
+ GATE_MDP0(CLK_MDP_IMG_DL_ASYNC0, "mdp_img_dl_async0", "top_mdp", 2),
+ GATE_MDP0(CLK_MDP_IMG_DL_ASYNC1, "mdp_img_dl_async1", "top_mdp", 3),
+ GATE_MDP0(CLK_MDP_DISP_RDMA, "mdp_disp_rdma", "top_mdp", 4),
+ GATE_MDP0(CLK_MDP_HMS, "mdp_hms", "top_mdp", 5),
+ GATE_MDP0(CLK_MDP_SMI0, "mdp_smi0", "top_mdp", 6),
+ GATE_MDP0(CLK_MDP_APB_BUS, "mdp_apb_bus", "top_mdp", 7),
+ GATE_MDP0(CLK_MDP_WROT0, "mdp_wrot0", "top_mdp", 8),
+ GATE_MDP0(CLK_MDP_RSZ0, "mdp_rsz0", "top_mdp", 9),
+ GATE_MDP0(CLK_MDP_HDR0, "mdp_hdr0", "top_mdp", 10),
+ GATE_MDP0(CLK_MDP_MUTEX0, "mdp_mutex0", "top_mdp", 11),
+ GATE_MDP0(CLK_MDP_WROT1, "mdp_wrot1", "top_mdp", 12),
+ GATE_MDP0(CLK_MDP_RSZ1, "mdp_rsz1", "top_mdp", 13),
+ GATE_MDP0(CLK_MDP_FAKE_ENG0, "mdp_fake_eng0", "top_mdp", 14),
+ GATE_MDP0(CLK_MDP_AAL0, "mdp_aal0", "top_mdp", 15),
+ GATE_MDP0(CLK_MDP_DISP_WDMA, "mdp_disp_wdma", "top_mdp", 16),
+ GATE_MDP0(CLK_MDP_COLOR, "mdp_color", "top_mdp", 17),
+ GATE_MDP0(CLK_MDP_IMG_DL_ASYNC2, "mdp_img_dl_async2", "top_mdp", 18),
+ /* MDP2 */
+ GATE_MDP2(CLK_MDP_IMG_DL_RELAY0_ASYNC0, "mdp_img_dl_rel0_as0", "top_mdp", 0),
+ GATE_MDP2(CLK_MDP_IMG_DL_RELAY1_ASYNC1, "mdp_img_dl_rel1_as1", "top_mdp", 8),
+ GATE_MDP2(CLK_MDP_IMG_DL_RELAY2_ASYNC2, "mdp_img_dl_rel2_as2", "top_mdp", 24),
+};
+
+static const struct mtk_clk_desc mdp_desc = {
+ .clks = mdp_clks,
+ .num_clks = ARRAY_SIZE(mdp_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8186_mdp[] = {
+ {
+ .compatible = "mediatek,mt8186-mdpsys",
+ .data = &mdp_desc,
+ }, {
+ /* sentinel */
+ }
+};
+
+static struct platform_driver clk_mt8186_mdp_drv = {
+ .probe = mtk_clk_simple_probe,
+ .driver = {
+ .name = "clk-mt8186-mdp",
+ .of_match_table = of_match_clk_mt8186_mdp,
+ },
+};
+builtin_platform_driver(clk_mt8186_mdp_drv);
--
2.18.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [v1 15/16] clk: mediatek: Add MT8186 mdpsys clock support
2022-01-10 13:44 ` [v1 15/16] clk: mediatek: Add MT8186 mdpsys " Chun-Jie Chen
@ 2022-01-10 15:49 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 39+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-01-10 15:49 UTC (permalink / raw)
To: Chun-Jie Chen, Matthias Brugger, Stephen Boyd, Nicolas Boichat,
Rob Herring
Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group
Il 10/01/22 14:44, Chun-Jie Chen ha scritto:
> Add MT8186 mdpsys clock controller which provides clock gate
> control in Multimedia Data Path.
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
^ permalink raw reply [flat|nested] 39+ messages in thread
* [v1 16/16] clk: mediatek: Add MT8186 ipesys clock support
[not found] <20220110134416.5191-1-chun-jie.chen@mediatek.com>
` (14 preceding siblings ...)
2022-01-10 13:44 ` [v1 15/16] clk: mediatek: Add MT8186 mdpsys " Chun-Jie Chen
@ 2022-01-10 13:44 ` Chun-Jie Chen
2022-01-10 15:49 ` AngeloGioacchino Del Regno
15 siblings, 1 reply; 39+ messages in thread
From: Chun-Jie Chen @ 2022-01-10 13:44 UTC (permalink / raw)
To: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring
Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group,
Chun-Jie Chen
Add MT8186 ipesys clock controller which provides clock gate
control for Image Process Engine.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
drivers/clk/mediatek/Makefile | 2 +-
drivers/clk/mediatek/clk-mt8186-ipe.c | 54 +++++++++++++++++++++++++++
2 files changed, 55 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mediatek/clk-mt8186-ipe.c
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 7320df02356c..f370eb661c71 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -71,7 +71,7 @@ obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt
clk-mt8186-apmixedsys.o clk-mt8186-imp_iic_wrap.o \
clk-mt8186-mfg.o clk-mt8186-mm.o clk-mt8186-wpe.o \
clk-mt8186-img.o clk-mt8186-vdec.o clk-mt8186-venc.o \
- clk-mt8186-cam.o clk-mt8186-mdp.o
+ clk-mt8186-cam.o clk-mt8186-mdp.o clk-mt8186-ipe.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8186-ipe.c b/drivers/clk/mediatek/clk-mt8186-ipe.c
new file mode 100644
index 000000000000..3e9160309a15
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8186-ipe.c
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2022 MediaTek Inc.
+// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+#include <dt-bindings/clock/mt8186-clk.h>
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+static const struct mtk_gate_regs ipe_cg_regs = {
+ .set_ofs = 0x4,
+ .clr_ofs = 0x8,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_IPE(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &ipe_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate ipe_clks[] = {
+ GATE_IPE(CLK_IPE_LARB19, "ipe_larb19", "top_ipe", 0),
+ GATE_IPE(CLK_IPE_LARB20, "ipe_larb20", "top_ipe", 1),
+ GATE_IPE(CLK_IPE_SMI_SUBCOM, "ipe_smi_subcom", "top_ipe", 2),
+ GATE_IPE(CLK_IPE_FD, "ipe_fd", "top_ipe", 3),
+ GATE_IPE(CLK_IPE_FE, "ipe_fe", "top_ipe", 4),
+ GATE_IPE(CLK_IPE_RSC, "ipe_rsc", "top_ipe", 5),
+ GATE_IPE(CLK_IPE_DPE, "ipe_dpe", "top_ipe", 6),
+ GATE_IPE(CLK_IPE_GALS_IPE, "ipe_gals_ipe", "top_img1", 8),
+};
+
+static const struct mtk_clk_desc ipe_desc = {
+ .clks = ipe_clks,
+ .num_clks = ARRAY_SIZE(ipe_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8186_ipe[] = {
+ {
+ .compatible = "mediatek,mt8186-ipesys",
+ .data = &ipe_desc,
+ }, {
+ /* sentinel */
+ }
+};
+
+static struct platform_driver clk_mt8186_ipe_drv = {
+ .probe = mtk_clk_simple_probe,
+ .driver = {
+ .name = "clk-mt8186-ipe",
+ .of_match_table = of_match_clk_mt8186_ipe,
+ },
+};
+builtin_platform_driver(clk_mt8186_ipe_drv);
--
2.18.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [v1 16/16] clk: mediatek: Add MT8186 ipesys clock support
2022-01-10 13:44 ` [v1 16/16] clk: mediatek: Add MT8186 ipesys " Chun-Jie Chen
@ 2022-01-10 15:49 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 39+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-01-10 15:49 UTC (permalink / raw)
To: Chun-Jie Chen, Matthias Brugger, Stephen Boyd, Nicolas Boichat,
Rob Herring
Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group
Il 10/01/22 14:44, Chun-Jie Chen ha scritto:
> Add MT8186 ipesys clock controller which provides clock gate
> control for Image Process Engine.
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
^ permalink raw reply [flat|nested] 39+ messages in thread