* [PATCH v3 0/2] Expose new features for Intel processor
@ 2020-08-09 7:47 Cathy Zhang
2020-08-09 7:47 ` [PATCH v3 1/2] x86/cpufeatures: Enumerate TSX suspend load address tracking instructions Cathy Zhang
2020-08-09 7:47 ` [PATCH v3 2/2] x86/kvm: Expose new features for supported cpuid Cathy Zhang
0 siblings, 2 replies; 8+ messages in thread
From: Cathy Zhang @ 2020-08-09 7:47 UTC (permalink / raw)
To: kvm, linux-kernel, x86
Cc: pbonzini, sean.j.christopherson, gregkh, tglx, tony.luck,
dave.hansen, kyung.min.park, ricardo.neri-calderon, vkuznets,
wanpengli, jmattson, joro, mingo, bp, hpa, jpoimboe, ak,
ravi.v.shankar, Cathy Zhang
This patchset is to expose two new features, SERIALIZE and
TSX suspend load tracking to KVM CPUID for processors which
support them. KVM reports this information and guest can
make use of them finally.
Detailed information on the instructions and CPUID feature
flags can be found in the latest "extensions" manual [1].
This series applies on top of TIP tree as it depends on
https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git/commit/?id=85b23fbc7d88f8c6e3951721802d7845bc39663d
Changes since v2:
* Combine the two kvm patches into a single one.
* Provide features' overview introduction in kvm patch commit message.
* Get the latest kernel patches.
* Change definition from TSX_LDTRK to TSXLDTRK for TSX new feature.
* Change kernel patches Author to the owner.
* Remove SERIALIZE enumeration patch.
Reference:
[1]. https://software.intel.com/content/dam/develop/public/us/en/documents/architecture-instruction-set-extensions-programming-reference.pdf
Cathy Zhang (1):
x86/kvm: Expose new features for supported cpuid
Kyung Min Park (1):
x86/cpufeatures: Enumerate TSX suspend load address tracking
instructions
arch/x86/include/asm/cpufeatures.h | 1 +
arch/x86/kvm/cpuid.c | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
--
1.8.3.1
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH v3 1/2] x86/cpufeatures: Enumerate TSX suspend load address tracking instructions 2020-08-09 7:47 [PATCH v3 0/2] Expose new features for Intel processor Cathy Zhang @ 2020-08-09 7:47 ` Cathy Zhang 2020-08-09 7:47 ` [PATCH v3 2/2] x86/kvm: Expose new features for supported cpuid Cathy Zhang 1 sibling, 0 replies; 8+ messages in thread From: Cathy Zhang @ 2020-08-09 7:47 UTC (permalink / raw) To: kvm, linux-kernel, x86 Cc: pbonzini, sean.j.christopherson, gregkh, tglx, tony.luck, dave.hansen, kyung.min.park, ricardo.neri-calderon, vkuznets, wanpengli, jmattson, joro, mingo, bp, hpa, jpoimboe, ak, ravi.v.shankar, Cathy Zhang From: Kyung Min Park <kyung.min.park@intel.com> Intel TSX suspend load tracking instructions aim to give a way to choose which memory accesses do not need to be tracked in the TSX read set. Add TSX suspend load tracking CPUID feature flag TSXLDTRK for enumeration. A processor supports Intel TSX suspend load address tracking if CPUID.0x07.0x0:EDX[16] is present. Two instructions XSUSLDTRK, XRESLDTRK are available when this feature is present. The CPU feature flag is shown as "tsxldtrk" in /proc/cpuinfo. This instruction is currently documented in the the latest "extensions" manual (ISE). It will appear in the "main" manual (SDM) in the future. Signed-off-by: Kyung Min Park <kyung.min.park@intel.com> Signed-off-by: Cathy Zhang <cathy.zhang@intel.com> Reviewed-by: Tony Luck <tony.luck@intel.com> --- Changes since v2: * Shorten documentation names for readability. Links to documentation can be found in the cover letter. (Dave Hansen) --- arch/x86/include/asm/cpufeatures.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 2901d5d..83fc9d3 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -368,6 +368,7 @@ #define X86_FEATURE_MD_CLEAR (18*32+10) /* VERW clears CPU buffers */ #define X86_FEATURE_TSX_FORCE_ABORT (18*32+13) /* "" TSX_FORCE_ABORT */ #define X86_FEATURE_SERIALIZE (18*32+14) /* SERIALIZE instruction */ +#define X86_FEATURE_TSXLDTRK (18*32+16) /* TSX Suspend Load Address Tracking */ #define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */ #define X86_FEATURE_ARCH_LBR (18*32+19) /* Intel ARCH LBR */ #define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */ -- 1.8.3.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v3 2/2] x86/kvm: Expose new features for supported cpuid 2020-08-09 7:47 [PATCH v3 0/2] Expose new features for Intel processor Cathy Zhang 2020-08-09 7:47 ` [PATCH v3 1/2] x86/cpufeatures: Enumerate TSX suspend load address tracking instructions Cathy Zhang @ 2020-08-09 7:47 ` Cathy Zhang 2020-08-09 17:14 ` Paolo Bonzini 1 sibling, 1 reply; 8+ messages in thread From: Cathy Zhang @ 2020-08-09 7:47 UTC (permalink / raw) To: kvm, linux-kernel, x86 Cc: pbonzini, sean.j.christopherson, gregkh, tglx, tony.luck, dave.hansen, kyung.min.park, ricardo.neri-calderon, vkuznets, wanpengli, jmattson, joro, mingo, bp, hpa, jpoimboe, ak, ravi.v.shankar, Cathy Zhang Expose the SERIALIZE and TSX Suspend Load Address Tracking features in KVM CPUID, so when running on processors which support them, KVM could pass this information to guests and they can make use of these features accordingly. SERIALIZE is a faster serializing instruction which does not modify registers, arithmetic flags or memory, will not cause VM exit. It's availability is indicated by CPUID.(EAX=7,ECX=0):ECX[bit 14]. TSX suspend load tracking instruction aims to give a way to choose which memory accesses do not need to be tracked in the TSX read set. It's availability is indicated as CPUID.(EAX=7,ECX=0):EDX[bit 16]. Those instructions are currently documented in the the latest "extensions" manual (ISE). It will appear in the "main" manual (SDM) in the future. Signed-off-by: Cathy Zhang <cathy.zhang@intel.com> Reviewed-by: Tony Luck <tony.luck@intel.com> --- Changes since v2: * Merge two patches into a single one. (Luck, Tony) * Add overview introduction for features. (Sean Christopherson) * Refactor commit message to explain why expose feature bits. (Luck, Tony) --- arch/x86/kvm/cpuid.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 8a294f9..dcf48cc 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -341,7 +341,8 @@ void kvm_set_cpu_caps(void) kvm_cpu_cap_mask(CPUID_7_EDX, F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) | F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) | - F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) + F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) | + F(SERIALIZE) | F(TSXLDTRK) ); /* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */ -- 1.8.3.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v3 2/2] x86/kvm: Expose new features for supported cpuid 2020-08-09 7:47 ` [PATCH v3 2/2] x86/kvm: Expose new features for supported cpuid Cathy Zhang @ 2020-08-09 17:14 ` Paolo Bonzini 2020-08-10 23:50 ` Zhang, Cathy 0 siblings, 1 reply; 8+ messages in thread From: Paolo Bonzini @ 2020-08-09 17:14 UTC (permalink / raw) To: Cathy Zhang, kvm, linux-kernel, x86 Cc: sean.j.christopherson, gregkh, tglx, tony.luck, dave.hansen, kyung.min.park, ricardo.neri-calderon, vkuznets, wanpengli, jmattson, joro, mingo, bp, hpa, jpoimboe, ak, ravi.v.shankar On 09/08/20 09:47, Cathy Zhang wrote: > Expose the SERIALIZE and TSX Suspend Load Address Tracking > features in KVM CPUID, so when running on processors which > support them, KVM could pass this information to guests and > they can make use of these features accordingly. > > SERIALIZE is a faster serializing instruction which does not modify > registers, arithmetic flags or memory, will not cause VM exit. It's > availability is indicated by CPUID.(EAX=7,ECX=0):ECX[bit 14]. > > TSX suspend load tracking instruction aims to give a way to choose > which memory accesses do not need to be tracked in the TSX read set. > It's availability is indicated as CPUID.(EAX=7,ECX=0):EDX[bit 16]. > > Those instructions are currently documented in the the latest "extensions" > manual (ISE). It will appear in the "main" manual (SDM) in the future. > > Signed-off-by: Cathy Zhang <cathy.zhang@intel.com> > Reviewed-by: Tony Luck <tony.luck@intel.com> > --- > Changes since v2: > * Merge two patches into a single one. (Luck, Tony) > * Add overview introduction for features. (Sean Christopherson) > * Refactor commit message to explain why expose feature bits. (Luck, Tony) > --- > arch/x86/kvm/cpuid.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c > index 8a294f9..dcf48cc 100644 > --- a/arch/x86/kvm/cpuid.c > +++ b/arch/x86/kvm/cpuid.c > @@ -341,7 +341,8 @@ void kvm_set_cpu_caps(void) > kvm_cpu_cap_mask(CPUID_7_EDX, > F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) | > F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) | > - F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) > + F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) | > + F(SERIALIZE) | F(TSXLDTRK) > ); > > /* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */ > TSXLDTRK is not going to be in 5.9 as far as I can see, so I split back again the patches (this is why I prefer them to be split, sorry Tony :)) and committed the SERIALIZE part. Paolo ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v3 2/2] x86/kvm: Expose new features for supported cpuid 2020-08-09 17:14 ` Paolo Bonzini @ 2020-08-10 23:50 ` Zhang, Cathy 2020-08-10 23:59 ` Luck, Tony 0 siblings, 1 reply; 8+ messages in thread From: Zhang, Cathy @ 2020-08-10 23:50 UTC (permalink / raw) To: Paolo Bonzini, kvm, linux-kernel, x86 Cc: sean.j.christopherson, gregkh, tglx, tony.luck, dave.hansen, kyung.min.park, ricardo.neri-calderon, vkuznets, wanpengli, jmattson, joro, mingo, bp, hpa, jpoimboe, ak, ravi.v.shankar On 8/10/2020 1:14 AM, Paolo Bonzini wrote: > On 09/08/20 09:47, Cathy Zhang wrote: >> Expose the SERIALIZE and TSX Suspend Load Address Tracking >> features in KVM CPUID, so when running on processors which >> support them, KVM could pass this information to guests and >> they can make use of these features accordingly. >> >> SERIALIZE is a faster serializing instruction which does not modify >> registers, arithmetic flags or memory, will not cause VM exit. It's >> availability is indicated by CPUID.(EAX=7,ECX=0):ECX[bit 14]. >> >> TSX suspend load tracking instruction aims to give a way to choose >> which memory accesses do not need to be tracked in the TSX read set. >> It's availability is indicated as CPUID.(EAX=7,ECX=0):EDX[bit 16]. >> >> Those instructions are currently documented in the the latest "extensions" >> manual (ISE). It will appear in the "main" manual (SDM) in the future. >> >> Signed-off-by: Cathy Zhang <cathy.zhang@intel.com> >> Reviewed-by: Tony Luck <tony.luck@intel.com> >> --- >> Changes since v2: >> * Merge two patches into a single one. (Luck, Tony) >> * Add overview introduction for features. (Sean Christopherson) >> * Refactor commit message to explain why expose feature bits. (Luck, Tony) >> --- >> arch/x86/kvm/cpuid.c | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c >> index 8a294f9..dcf48cc 100644 >> --- a/arch/x86/kvm/cpuid.c >> +++ b/arch/x86/kvm/cpuid.c >> @@ -341,7 +341,8 @@ void kvm_set_cpu_caps(void) >> kvm_cpu_cap_mask(CPUID_7_EDX, >> F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) | >> F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) | >> - F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) >> + F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) | >> + F(SERIALIZE) | F(TSXLDTRK) >> ); >> >> /* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */ >> > TSXLDTRK is not going to be in 5.9 as far as I can see, so I split back > again the patches (this is why I prefer them to be split, sorry Tony :)) > and committed the SERIALIZE part. > > Paolo Hello Paolo, As you suggest, I will split the kvm patch into two parts, SERIALIZE and TSXLDTRK, and this series will include three patches then, 2 kvm patches and 1 kernel patch. SERIALIZE could get merged into 5.9, but TSXLDTRK should wait for the next release. I just want to double confirm with you, please help correct me if I'm wrong. ^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [PATCH v3 2/2] x86/kvm: Expose new features for supported cpuid 2020-08-10 23:50 ` Zhang, Cathy @ 2020-08-10 23:59 ` Luck, Tony 2020-08-11 0:18 ` Zhang, Cathy 2020-08-11 8:32 ` Paolo Bonzini 0 siblings, 2 replies; 8+ messages in thread From: Luck, Tony @ 2020-08-10 23:59 UTC (permalink / raw) To: Zhang, Cathy, Paolo Bonzini, kvm, linux-kernel, x86 Cc: Christopherson, Sean J, gregkh, tglx, Hansen, Dave, Park, Kyung Min, ricardo.neri-calderon, vkuznets, wanpengli, jmattson, joro, mingo, bp, hpa, jpoimboe, ak, Shankar, Ravi V > As you suggest, I will split the kvm patch into two parts, SERIALIZE and > TSXLDTRK, and this series will include three patches then, 2 kvm patches > and 1 kernel patch. SERIALIZE could get merged into 5.9, but TSXLDTRK > should wait for the next release. I just want to double confirm with > you, please help correct me if I'm wrong. Paolo is saying that he has applied the SERIALIZE part to his KVM tree. https://git.kernel.org/pub/scm/virt/kvm/kvm.git/commit/?h=queue&id=43bd9ef42b3b862c97f1f4e86bf3ace890bef924 Next step for you is a two part series. Part 1: Add TSXLDTRK to cpufeatures.h Part 2: Add TSXLDTRK to arch/x86/kvm/cpuid.c (on top of the version that Paolo committed with SERIALIZE) Paolo: The 5.9 merge window is still open this week. Will you send the KVM serialize patch to Linus before this merge window closes? Or do you have it queued for v5.10? -Tony ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v3 2/2] x86/kvm: Expose new features for supported cpuid 2020-08-10 23:59 ` Luck, Tony @ 2020-08-11 0:18 ` Zhang, Cathy 2020-08-11 8:32 ` Paolo Bonzini 1 sibling, 0 replies; 8+ messages in thread From: Zhang, Cathy @ 2020-08-11 0:18 UTC (permalink / raw) To: Luck, Tony, Paolo Bonzini, kvm, linux-kernel, x86 Cc: Christopherson, Sean J, gregkh, tglx, Hansen, Dave, Park, Kyung Min, ricardo.neri-calderon, vkuznets, wanpengli, jmattson, joro, mingo, bp, hpa, jpoimboe, ak, Shankar, Ravi V On 8/11/2020 7:59 AM, Luck, Tony wrote: >> As you suggest, I will split the kvm patch into two parts, SERIALIZE and >> TSXLDTRK, and this series will include three patches then, 2 kvm patches >> and 1 kernel patch. SERIALIZE could get merged into 5.9, but TSXLDTRK >> should wait for the next release. I just want to double confirm with >> you, please help correct me if I'm wrong. > Paolo is saying that he has applied the SERIALIZE part to his KVM tree. > > https://git.kernel.org/pub/scm/virt/kvm/kvm.git/commit/?h=queue&id=43bd9ef42b3b862c97f1f4e86bf3ace890bef924 > > Next step for you is a two part series. > > Part 1: Add TSXLDTRK to cpufeatures.h > Part 2: Add TSXLDTRK to arch/x86/kvm/cpuid.c (on top of the version that Paolo committed with SERIALIZE) > > Paolo: The 5.9 merge window is still open this week. Will you send the KVM serialize patch to Linus > before this merge window closes? Or do you have it queued for v5.10? > > -Tony Got it! Thanks for the explanation, Tony! ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v3 2/2] x86/kvm: Expose new features for supported cpuid 2020-08-10 23:59 ` Luck, Tony 2020-08-11 0:18 ` Zhang, Cathy @ 2020-08-11 8:32 ` Paolo Bonzini 1 sibling, 0 replies; 8+ messages in thread From: Paolo Bonzini @ 2020-08-11 8:32 UTC (permalink / raw) To: Luck, Tony, Zhang, Cathy, kvm, linux-kernel, x86 Cc: Christopherson, Sean J, gregkh, tglx, Hansen, Dave, Park, Kyung Min, ricardo.neri-calderon, vkuznets, wanpengli, jmattson, joro, mingo, bp, hpa, jpoimboe, ak, Shankar, Ravi V On 11/08/20 01:59, Luck, Tony wrote: > > Part 1: Add TSXLDTRK to cpufeatures.h Part 2: Add TSXLDTRK to > arch/x86/kvm/cpuid.c (on top of the version that Paolo committed with > SERIALIZE) > > Paolo: The 5.9 merge window is still open this week. Will you send > the KVM serialize patch to Linus before this merge window closes? Or > do you have it queued for v5.10? Yes, I am sending it today together with the bulk of ARM and PPC changes. I just wanted to soak the branch in linux-next for a day or two, just in case I screwed up the ARM and PPC pull requests. Paolo ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2020-08-11 8:32 UTC | newest] Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-08-09 7:47 [PATCH v3 0/2] Expose new features for Intel processor Cathy Zhang 2020-08-09 7:47 ` [PATCH v3 1/2] x86/cpufeatures: Enumerate TSX suspend load address tracking instructions Cathy Zhang 2020-08-09 7:47 ` [PATCH v3 2/2] x86/kvm: Expose new features for supported cpuid Cathy Zhang 2020-08-09 17:14 ` Paolo Bonzini 2020-08-10 23:50 ` Zhang, Cathy 2020-08-10 23:59 ` Luck, Tony 2020-08-11 0:18 ` Zhang, Cathy 2020-08-11 8:32 ` Paolo Bonzini
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