* [PATCH 1/1] arm64: dts: qcom: sm6125: Add dispcc node
@ 2022-10-01 18:53 Martin Botka
2022-10-01 20:11 ` Konrad Dybcio
0 siblings, 1 reply; 2+ messages in thread
From: Martin Botka @ 2022-10-01 18:53 UTC (permalink / raw)
To: martin.botka1
Cc: ~postmarketos/upstreaming, Konrad Dybcio,
AngeloGioacchino Del Regno, Marijn Suijten, Jami Kettunen,
Paul Bouchara, Martin Botka, Andy Gross, Bjorn Andersson,
Rob Herring, Krzysztof Kozlowski, linux-arm-msm, devicetree,
linux-kernel
Add the dispcc node for the newly added DISPCC
driver for Qualcomm Technology Inc's SM6125 SoC.
Signed-off-by: Martin Botka <martin.botka@somainline.org>
---
arch/arm64/boot/dts/qcom/sm6125.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
index 62f216bfca4f..ffbcee009279 100644
--- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
@@ -3,6 +3,7 @@
* Copyright (c) 2021, Martin Botka <martin.botka@somainline.org>
*/
+#include <dt-bindings/clock/qcom,dispcc-sm6125.h>
#include <dt-bindings/clock/qcom,gcc-sm6125.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/gpio/gpio.h>
@@ -367,6 +368,17 @@ soc {
ranges = <0x00 0x00 0x00 0xffffffff>;
compatible = "simple-bus";
+ dispcc: clock-controller@5f00000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "qcom,dispcc-sm6125";
+ reg = <0x5f00000 0x20000>;
+ clocks = <&gcc GCC_DISP_AHB_CLK>;
+ clock-names = "cfg_ahb_clk";
+ #clock-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
tcsr_mutex: hwlock@340000 {
compatible = "qcom,tcsr-mutex";
reg = <0x00340000 0x20000>;
--
2.37.3
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH 1/1] arm64: dts: qcom: sm6125: Add dispcc node
2022-10-01 18:53 [PATCH 1/1] arm64: dts: qcom: sm6125: Add dispcc node Martin Botka
@ 2022-10-01 20:11 ` Konrad Dybcio
0 siblings, 0 replies; 2+ messages in thread
From: Konrad Dybcio @ 2022-10-01 20:11 UTC (permalink / raw)
To: Martin Botka, martin.botka1
Cc: ~postmarketos/upstreaming, AngeloGioacchino Del Regno,
Marijn Suijten, Jami Kettunen, Paul Bouchara, Andy Gross,
Bjorn Andersson, Rob Herring, Krzysztof Kozlowski, linux-arm-msm,
devicetree, linux-kernel
On 1.10.2022 20:53, Martin Botka wrote:
> Add the dispcc node for the newly added DISPCC
> driver for Qualcomm Technology Inc's SM6125 SoC.
>
> Signed-off-by: Martin Botka <martin.botka@somainline.org>
> ---
> arch/arm64/boot/dts/qcom/sm6125.dtsi | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> index 62f216bfca4f..ffbcee009279 100644
> --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> @@ -3,6 +3,7 @@
> * Copyright (c) 2021, Martin Botka <martin.botka@somainline.org>
> */
>
> +#include <dt-bindings/clock/qcom,dispcc-sm6125.h>
> #include <dt-bindings/clock/qcom,gcc-sm6125.h>
> #include <dt-bindings/clock/qcom,rpmcc.h>
> #include <dt-bindings/gpio/gpio.h>
> @@ -367,6 +368,17 @@ soc {
> ranges = <0x00 0x00 0x00 0xffffffff>;
> compatible = "simple-bus";
>
> + dispcc: clock-controller@5f00000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "qcom,dispcc-sm6125";
> + reg = <0x5f00000 0x20000>;
Please pad the address to 8 hex digits and sort the properties properly.
> + clocks = <&gcc GCC_DISP_AHB_CLK>;
> + clock-names = "cfg_ahb_clk";
This driver does not expect this clock. It does however expect:
bi_tcxo
dp_phy_pll_link_clk
dp_phy_pll_vco_div_clk
dsi0_phy_pll_out_byteclk
dsi0_phy_pll_out_dsiclk
dsi1_phy_pll_out_dsiclk
gcc_disp_gpll0_div_clk_src
Konrad
> + #clock-cells = <1>;
> + #power-domain-cells = <1>;
> + };
> +
> tcsr_mutex: hwlock@340000 {
> compatible = "qcom,tcsr-mutex";
> reg = <0x00340000 0x20000>;
^ permalink raw reply [flat|nested] 2+ messages in thread
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