From: Paolo Bonzini <pbonzini@redhat.com>
To: Mohammed Gamal <mgamal@redhat.com>, kvm@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, vkuznets@redhat.com,
sean.j.christopherson@intel.com, wanpengli@tencent.com,
jmattson@google.com, joro@8bytes.org
Subject: Re: [PATCH v3 3/9] KVM: x86: mmu: Add guest physical address check in translate_gpa()
Date: Fri, 10 Jul 2020 19:41:25 +0200 [thread overview]
Message-ID: <2cb33bf8-f4f9-6a5b-ca72-d2dbcafc436d@redhat.com> (raw)
In-Reply-To: <20200710154811.418214-4-mgamal@redhat.com>
On 10/07/20 17:48, Mohammed Gamal wrote:
> In case of running a guest with 4-level page tables on a 5-level page
> table host, it might happen that a guest might have a physical address
> with reserved bits set, but the host won't see that and trap it.
>
> Hence, we need to check page faults' physical addresses against the guest's
> maximum physical memory and if it's exceeded, we need to add
> the PFERR_RSVD_MASK bits to the PF's error code.
>
> Also make sure the error code isn't overwritten by the page table walker.
>
New commit message:
KVM: x86: mmu: Add guest physical address check in translate_gpa()
Intel processors of various generations have supported 36, 39, 46 or 52
bits for physical addresses. Until IceLake introduced MAXPHYADDR==52,
running on a machine with higher MAXPHYADDR than the guest more or less
worked, because software that relied on reserved address bits (like KVM)
generally used bit 51 as a marker and therefore the page faults where
generated anyway.
Unfortunately this is not true anymore if the host MAXPHYADDR is 52,
and this can cause problems when migrating from a MAXPHYADDR<52
machine to one with MAXPHYADDR==52. Typically, the latter are machines
that support 5-level page tables, so they can be identified easily from
the LA57 CPUID bit.
When that happens, the guest might have a physical address with reserved
bits set, but the host won't see that and trap it. Hence, we need
to check page faults' physical addresses against the guest's maximum
physical memory and if it's exceeded, we need to add the PFERR_RSVD_MASK
bits to the page fault error code.
This patch does this for the MMU's page walks. The next patches will
ensure that the correct exception and error code is produced whenever
no host-reserved bits are set in page table entries.
Paolo
next prev parent reply other threads:[~2020-07-10 17:41 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-10 15:48 [PATCH v3 0/9] KVM: Support guest MAXPHYADDR < host MAXPHYADDR Mohammed Gamal
2020-07-10 15:48 ` [PATCH v3 1/9] KVM: x86: Add helper functions for illegal GPA checking and page fault injection Mohammed Gamal
2020-07-10 15:48 ` [PATCH v3 2/9] KVM: x86: mmu: Move translate_gpa() to mmu.c Mohammed Gamal
2020-07-10 15:48 ` [PATCH v3 3/9] KVM: x86: mmu: Add guest physical address check in translate_gpa() Mohammed Gamal
2020-07-10 17:41 ` Paolo Bonzini [this message]
2020-07-10 15:48 ` [PATCH v3 4/9] KVM: x86: rename update_bp_intercept to update_exception_bitmap Mohammed Gamal
2020-07-10 16:15 ` Jim Mattson
2020-07-10 15:48 ` [PATCH v3 5/9] KVM: x86: update exception bitmap on CPUID changes Mohammed Gamal
2020-07-10 16:25 ` Jim Mattson
2020-07-10 15:48 ` [PATCH v3 6/9] KVM: VMX: introduce vmx_need_pf_intercept Mohammed Gamal
2020-07-10 15:48 ` [PATCH v3 7/9] KVM: VMX: Add guest physical address check in EPT violation and misconfig Mohammed Gamal
2020-07-13 18:32 ` Sean Christopherson
2020-07-15 23:00 ` Sean Christopherson
2020-08-17 17:22 ` Sean Christopherson
2020-08-17 18:01 ` Paolo Bonzini
2020-10-09 16:17 ` Jim Mattson
2020-10-14 23:44 ` Jim Mattson
2020-10-23 3:14 ` Sean Christopherson
2020-10-23 9:22 ` Paolo Bonzini
2020-10-23 16:59 ` Jim Mattson
2020-10-23 17:16 ` Paolo Bonzini
2020-10-23 17:23 ` Jim Mattson
2020-10-23 17:43 ` Paolo Bonzini
2021-01-15 19:35 ` Jim Mattson
2021-01-20 21:16 ` Jim Mattson
2021-01-27 20:57 ` Jim Mattson
2021-06-21 18:31 ` Jim Mattson
2020-07-10 15:48 ` [PATCH v3 8/9] KVM: VMX: optimize #PF injection when MAXPHYADDR does not match Mohammed Gamal
2020-07-10 15:48 ` [PATCH v3 9/9] KVM: x86: SVM: VMX: Make GUEST_MAXPHYADDR < HOST_MAXPHYADDR support configurable Mohammed Gamal
2020-07-10 17:40 ` Paolo Bonzini
2020-07-10 16:30 ` [PATCH v3 0/9] KVM: Support guest MAXPHYADDR < host MAXPHYADDR Jim Mattson
2020-07-10 17:06 ` Paolo Bonzini
2020-07-10 17:13 ` Jim Mattson
2020-07-10 17:16 ` Paolo Bonzini
2020-07-10 17:26 ` Sean Christopherson
2020-07-10 17:26 ` Jim Mattson
2020-07-10 17:40 ` Paolo Bonzini
2020-07-10 17:49 ` Paolo Bonzini
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=2cb33bf8-f4f9-6a5b-ca72-d2dbcafc436d@redhat.com \
--to=pbonzini@redhat.com \
--cc=jmattson@google.com \
--cc=joro@8bytes.org \
--cc=kvm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mgamal@redhat.com \
--cc=sean.j.christopherson@intel.com \
--cc=vkuznets@redhat.com \
--cc=wanpengli@tencent.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).