[PATCH 0/2] clk: meson: drop clk-audio-divider

[PATCH 0/2] clk: meson: drop clk-audio-divider

[Jerome Brunet]

As explained in the commit descriptions, clk-audio-divider was a poor
solution to make sure PLL rates would be high enough while using CCF
rate propagation to determine audio clock rates.

Stopping rate propagation before the PLLs is actually simpler and provides
better results. It also allow to get rid of clk-audio-divider.

Off tree sound cards using these clocks should add the following to the
sound card DT to properly setup the PLLs:

	assigned-clocks = <&clkc CLKID_MPLL2>,
	                  <&clkc CLKID_MPLL0>,
	                  <&clkc CLKID_MPLL1>;
	assigned-clock-parents = <0>, <0>, <0>;
	assigned-clock-rates = <294912000>,
	                       <270950400>,
	                       <393216000>;

* MPLL2: 294912000Hz: 192Khz * 32 * 24 * 2
  used 24, 48, 96, 192Khz

* MPLL0: 270950400Hz: 176.4Khz * 32 * 24 * 2
  used for 5.512, 10.025, 20.05, 44.1, 88.2 and 176,4Khz

* MPLL1: 393216000Hz: 64Khz * 32 * 24 * 8
  used for 8, 16, 32 and 64Khz

Jerome Brunet (2):
  clk: meson: stop rate propagation for audio clocks
  clk: meson: remove unused clk-audio-divider driver

 drivers/clk/meson/Makefile            |   2 +-
 drivers/clk/meson/clk-audio-divider.c | 110 ----------------------------------
 drivers/clk/meson/clkc.h              |   7 ---
 drivers/clk/meson/gxbb.c              |  16 +++--
 4 files changed, 8 insertions(+), 127 deletions(-)
 delete mode 100644 drivers/clk/meson/clk-audio-divider.c

-- 
2.14.3

[PATCH 1/2] clk: meson: stop rate propagation for audio clocks

[Jerome Brunet]

It is actually a lot easier to setup the PLL with carefully chosen rates
than relying on CCF clock propagation for this audio use case.
This way, we can make sure we will always be able to provide the common
audio clock rates, while having the PLL in the optimal operating range.

For this, we stop the rate propagation at the mux picking the
PLL and let it round to the closest matching PLL.

Doing so, we can use the generic divider for the i2s clock.
clk-audio-divider is no longer required. It was a (poor) attempt
to use CCF rate propagation while making sure the PLL rate would
be high enough to work with audio use cases.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/clk/meson/gxbb.c | 16 +++++++---------
 1 file changed, 7 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 297ebc391475..894a6adaa17a 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -970,28 +970,26 @@ static struct clk_regmap gxbb_cts_amclk_sel = {
 		.mask = 0x3,
 		.shift = 9,
 		.table = (u32[]){ 1, 2, 3 },
+		.flags = CLK_MUX_ROUND_CLOSEST,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "cts_amclk_sel",
 		.ops = &clk_regmap_mux_ops,
 		.parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" },
 		.num_parents = 3,
-		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 
 static struct clk_regmap gxbb_cts_amclk_div = {
-	.data = &(struct meson_clk_audio_div_data){
-		.div = {
-			.reg_off = HHI_AUD_CLK_CNTL,
-			.shift   = 0,
-			.width   = 8,
-		},
+	.data = &(struct clk_regmap_div_data) {
+		.offset = HHI_AUD_CLK_CNTL,
+		.shift = 0,
+		.width = 8,
 		.flags = CLK_DIVIDER_ROUND_CLOSEST,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "cts_amclk_div",
-		.ops = &meson_clk_audio_divider_ops,
+		.ops = &clk_regmap_divider_ops,
 		.parent_names = (const char *[]){ "cts_amclk_sel" },
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
@@ -1018,13 +1016,13 @@ static struct clk_regmap gxbb_cts_mclk_i958_sel = {
 		.mask = 0x3,
 		.shift = 25,
 		.table = (u32[]){ 1, 2, 3 },
+		.flags = CLK_MUX_ROUND_CLOSEST,
 	},
 	.hw.init = &(struct clk_init_data) {
 		.name = "cts_mclk_i958_sel",
 		.ops = &clk_regmap_mux_ops,
 		.parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" },
 		.num_parents = 3,
-		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 
-- 
2.14.3

Re: [PATCH 1/2] clk: meson: stop rate propagation for audio clocks

[Neil Armstrong]

On 20/06/2018 12:06, Jerome Brunet wrote:
> It is actually a lot easier to setup the PLL with carefully chosen rates
> than relying on CCF clock propagation for this audio use case.
> This way, we can make sure we will always be able to provide the common
> audio clock rates, while having the PLL in the optimal operating range.
> 
> For this, we stop the rate propagation at the mux picking the
> PLL and let it round to the closest matching PLL.
> 
> Doing so, we can use the generic divider for the i2s clock.
> clk-audio-divider is no longer required. It was a (poor) attempt
> to use CCF rate propagation while making sure the PLL rate would
> be high enough to work with audio use cases.
> 
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> ---
>  drivers/clk/meson/gxbb.c | 16 +++++++---------
>  1 file changed, 7 insertions(+), 9 deletions(-)
> 
[...]
Acked-by: Neil Armstrong <narmstrong@baylibre.com>

[PATCH 2/2] clk: meson: remove unused clk-audio-divider driver

[Jerome Brunet]

clk-audio-divider is no longer used, we can remove it.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/clk/meson/Makefile            |   2 +-
 drivers/clk/meson/clk-audio-divider.c | 110 ----------------------------------
 drivers/clk/meson/clkc.h              |   7 ---
 3 files changed, 1 insertion(+), 118 deletions(-)
 delete mode 100644 drivers/clk/meson/clk-audio-divider.c

diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index d0d13aeb369a..e40fea96069b 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -2,7 +2,7 @@
 # Makefile for Meson specific clk
 #
 
-obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-audio-divider.o
+obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o
 obj-$(CONFIG_COMMON_CLK_MESON_AO) += meson-aoclk.o
 obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
 obj-$(CONFIG_COMMON_CLK_GXBB)	 += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
diff --git a/drivers/clk/meson/clk-audio-divider.c b/drivers/clk/meson/clk-audio-divider.c
deleted file mode 100644
index e4cf96ba704e..000000000000
--- a/drivers/clk/meson/clk-audio-divider.c
+++ /dev/null
@@ -1,110 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2017 AmLogic, Inc.
- * Author: Jerome Brunet <jbrunet@baylibre.com>
- */
-
-/*
- * i2s master clock divider: The algorithm of the generic clk-divider used with
- * a very precise clock parent such as the mpll tends to select a low divider
- * factor. This gives poor results with this particular divider, especially with
- * high frequencies (> 100 MHz)
- *
- * This driver try to select the maximum possible divider with the rate the
- * upstream clock can provide.
- */
-
-#include <linux/clk-provider.h>
-#include "clkc.h"
-
-static inline struct meson_clk_audio_div_data *
-meson_clk_audio_div_data(struct clk_regmap *clk)
-{
-	return (struct meson_clk_audio_div_data *)clk->data;
-}
-
-static int _div_round(unsigned long parent_rate, unsigned long rate,
-		      unsigned long flags)
-{
-	if (flags & CLK_DIVIDER_ROUND_CLOSEST)
-		return DIV_ROUND_CLOSEST_ULL((u64)parent_rate, rate);
-
-	return DIV_ROUND_UP_ULL((u64)parent_rate, rate);
-}
-
-static int _get_val(unsigned long parent_rate, unsigned long rate)
-{
-	return DIV_ROUND_UP_ULL((u64)parent_rate, rate) - 1;
-}
-
-static int _valid_divider(unsigned int width, int divider)
-{
-	int max_divider = 1 << width;
-
-	return clamp(divider, 1, max_divider);
-}
-
-static unsigned long audio_divider_recalc_rate(struct clk_hw *hw,
-					       unsigned long parent_rate)
-{
-	struct clk_regmap *clk = to_clk_regmap(hw);
-	struct meson_clk_audio_div_data *adiv = meson_clk_audio_div_data(clk);
-	unsigned long divider;
-
-	divider = meson_parm_read(clk->map, &adiv->div) + 1;
-
-	return DIV_ROUND_UP_ULL((u64)parent_rate, divider);
-}
-
-static long audio_divider_round_rate(struct clk_hw *hw,
-				     unsigned long rate,
-				     unsigned long *parent_rate)
-{
-	struct clk_regmap *clk = to_clk_regmap(hw);
-	struct meson_clk_audio_div_data *adiv = meson_clk_audio_div_data(clk);
-	unsigned long max_prate;
-	int divider;
-
-	if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
-		divider = _div_round(*parent_rate, rate, adiv->flags);
-		divider = _valid_divider(adiv->div.width, divider);
-		return DIV_ROUND_UP_ULL((u64)*parent_rate, divider);
-	}
-
-	/* Get the maximum parent rate */
-	max_prate = clk_hw_round_rate(clk_hw_get_parent(hw), ULONG_MAX);
-
-	/* Get the corresponding rounded down divider */
-	divider = max_prate / rate;
-	divider = _valid_divider(adiv->div.width, divider);
-
-	/* Get actual rate of the parent */
-	*parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
-					 divider * rate);
-
-	return DIV_ROUND_UP_ULL((u64)*parent_rate, divider);
-}
-
-static int audio_divider_set_rate(struct clk_hw *hw,
-				  unsigned long rate,
-				  unsigned long parent_rate)
-{
-	struct clk_regmap *clk = to_clk_regmap(hw);
-	struct meson_clk_audio_div_data *adiv = meson_clk_audio_div_data(clk);
-	int val = _get_val(parent_rate, rate);
-
-	meson_parm_write(clk->map, &adiv->div, val);
-
-	return 0;
-}
-
-const struct clk_ops meson_clk_audio_divider_ro_ops = {
-	.recalc_rate	= audio_divider_recalc_rate,
-	.round_rate	= audio_divider_round_rate,
-};
-
-const struct clk_ops meson_clk_audio_divider_ops = {
-	.recalc_rate	= audio_divider_recalc_rate,
-	.round_rate	= audio_divider_round_rate,
-	.set_rate	= audio_divider_set_rate,
-};
diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
index 2fb084330ee9..48db02424f02 100644
--- a/drivers/clk/meson/clkc.h
+++ b/drivers/clk/meson/clkc.h
@@ -91,11 +91,6 @@ struct meson_clk_mpll_data {
 
 #define CLK_MESON_MPLL_ROUND_CLOSEST	BIT(0)
 
-struct meson_clk_audio_div_data {
-	struct parm div;
-	u8 flags;
-};
-
 #define MESON_GATE(_name, _reg, _bit)					\
 struct clk_regmap _name = {						\
 	.data = &(struct clk_regmap_gate_data){				\
@@ -117,7 +112,5 @@ extern const struct clk_ops meson_clk_pll_ops;
 extern const struct clk_ops meson_clk_cpu_ops;
 extern const struct clk_ops meson_clk_mpll_ro_ops;
 extern const struct clk_ops meson_clk_mpll_ops;
-extern const struct clk_ops meson_clk_audio_divider_ro_ops;
-extern const struct clk_ops meson_clk_audio_divider_ops;
 
 #endif /* __CLKC_H */
-- 
2.14.3

Re: [PATCH 2/2] clk: meson: remove unused clk-audio-divider driver

[Neil Armstrong]

On 20/06/2018 12:06, Jerome Brunet wrote:
> clk-audio-divider is no longer used, we can remove it.
> 
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> ---
>  drivers/clk/meson/Makefile            |   2 +-
>  drivers/clk/meson/clk-audio-divider.c | 110 ----------------------------------
>  drivers/clk/meson/clkc.h              |   7 ---
>  3 files changed, 1 insertion(+), 118 deletions(-)
>  delete mode 100644 drivers/clk/meson/clk-audio-divider.c
> 
[...]
Acked-by: Neil Armstrong <narmstrong@baylibre.com>

Re: [PATCH 0/2] clk: meson: drop clk-audio-divider

[Jerome Brunet]

On Wed, 2018-06-20 at 12:06 +0200, Jerome Brunet wrote:
> As explained in the commit descriptions, clk-audio-divider was a poor
> solution to make sure PLL rates would be high enough while using CCF
> rate propagation to determine audio clock rates.
> 
> Stopping rate propagation before the PLLs is actually simpler and provides
> better results. It also allow to get rid of clk-audio-divider.
> 
> Off tree sound cards using these clocks should add the following to the
> sound card DT to properly setup the PLLs:
> 
> 	assigned-clocks = <&clkc CLKID_MPLL2>,
> 	                  <&clkc CLKID_MPLL0>,
> 	                  <&clkc CLKID_MPLL1>;
> 	assigned-clock-parents = <0>, <0>, <0>;
> 	assigned-clock-rates = <294912000>,
> 	                       <270950400>,
> 	                       <393216000>;
> 
> * MPLL2: 294912000Hz: 192Khz * 32 * 24 * 2
>   used 24, 48, 96, 192Khz
> 
> * MPLL0: 270950400Hz: 176.4Khz * 32 * 24 * 2
>   used for 5.512, 10.025, 20.05, 44.1, 88.2 and 176,4Khz
> 
> * MPLL1: 393216000Hz: 64Khz * 32 * 24 * 8
>   used for 8, 16, 32 and 64Khz
> 
> Jerome Brunet (2):
>   clk: meson: stop rate propagation for audio clocks
>   clk: meson: remove unused clk-audio-divider driver
> 
>  drivers/clk/meson/Makefile            |   2 +-
>  drivers/clk/meson/clk-audio-divider.c | 110 ----------------------------------
>  drivers/clk/meson/clkc.h              |   7 ---
>  drivers/clk/meson/gxbb.c              |  16 +++--
>  4 files changed, 8 insertions(+), 127 deletions(-)
>  delete mode 100644 drivers/clk/meson/clk-audio-divider.c
> 

Rebased and applied with Neil's ack.