* [PATCH v1 1/2] clk: tegra: divider: Fix missing check for enable-bit on rate's recalculation @ 2019-07-15 17:35 Dmitry Osipenko 2019-07-15 17:35 ` [PATCH v1 2/2] clk: tegra: divider: Support enable-bit for Super clocks Dmitry Osipenko 2019-07-17 20:08 ` [PATCH v1 1/2] clk: tegra: divider: Fix missing check for enable-bit on rate's recalculation Stephen Boyd 0 siblings, 2 replies; 6+ messages in thread From: Dmitry Osipenko @ 2019-07-15 17:35 UTC (permalink / raw) To: Michael Turquette, Thierry Reding, Jonathan Hunter, Peter De Schrijver, Prashant Gaikwad, Stephen Boyd Cc: linux-clk, linux-tegra, linux-kernel Unset "enable" bit means that divider is in bypass mode, hence it doesn't have any effect in that case. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> --- drivers/clk/tegra/clk-divider.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c index e76731fb7d69..f33c19045386 100644 --- a/drivers/clk/tegra/clk-divider.c +++ b/drivers/clk/tegra/clk-divider.c @@ -40,8 +40,13 @@ static unsigned long clk_frac_div_recalc_rate(struct clk_hw *hw, int div, mul; u64 rate = parent_rate; - reg = readl_relaxed(divider->reg) >> divider->shift; - div = reg & div_mask(divider); + reg = readl_relaxed(divider->reg); + + if ((divider->flags & TEGRA_DIVIDER_UART) && + !(reg & PERIPH_CLK_UART_DIV_ENB)) + return rate; + + div = (reg >> divider->shift) & div_mask(divider); mul = get_mul(divider); div += mul; -- 2.22.0 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v1 2/2] clk: tegra: divider: Support enable-bit for Super clocks 2019-07-15 17:35 [PATCH v1 1/2] clk: tegra: divider: Fix missing check for enable-bit on rate's recalculation Dmitry Osipenko @ 2019-07-15 17:35 ` Dmitry Osipenko 2019-07-17 20:08 ` [PATCH v1 1/2] clk: tegra: divider: Fix missing check for enable-bit on rate's recalculation Stephen Boyd 1 sibling, 0 replies; 6+ messages in thread From: Dmitry Osipenko @ 2019-07-15 17:35 UTC (permalink / raw) To: Michael Turquette, Thierry Reding, Jonathan Hunter, Peter De Schrijver, Prashant Gaikwad, Stephen Boyd Cc: linux-clk, linux-tegra, linux-kernel All "super" clock dividers have enable bit. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> --- drivers/clk/tegra/clk-divider.c | 12 ++++++++++++ drivers/clk/tegra/clk-super.c | 1 + drivers/clk/tegra/clk.h | 4 ++++ 3 files changed, 17 insertions(+) diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c index f33c19045386..a980b9bddecd 100644 --- a/drivers/clk/tegra/clk-divider.c +++ b/drivers/clk/tegra/clk-divider.c @@ -17,6 +17,7 @@ #define get_max_div(d) div_mask(d) #define PERIPH_CLK_UART_DIV_ENB BIT(24) +#define SUPER_CLK_DIV_ENB BIT(31) static int get_div(struct tegra_clk_frac_div *divider, unsigned long rate, unsigned long parent_rate) @@ -46,6 +47,10 @@ static unsigned long clk_frac_div_recalc_rate(struct clk_hw *hw, !(reg & PERIPH_CLK_UART_DIV_ENB)) return rate; + if ((divider->flags & TEGRA_DIVIDER_SUPER) && + !(reg & SUPER_CLK_DIV_ENB)) + return rate; + div = (reg >> divider->shift) & div_mask(divider); mul = get_mul(divider); @@ -96,6 +101,13 @@ static int clk_frac_div_set_rate(struct clk_hw *hw, unsigned long rate, val &= ~(div_mask(divider) << divider->shift); val |= div << divider->shift; + if (divider->flags & TEGRA_DIVIDER_SUPER) { + if (div) + val |= SUPER_CLK_DIV_ENB; + else + val &= ~SUPER_CLK_DIV_ENB; + } + if (divider->flags & TEGRA_DIVIDER_UART) { if (div) val |= PERIPH_CLK_UART_DIV_ENB; diff --git a/drivers/clk/tegra/clk-super.c b/drivers/clk/tegra/clk-super.c index 39ef31b46df5..4d8e36b04f03 100644 --- a/drivers/clk/tegra/clk-super.c +++ b/drivers/clk/tegra/clk-super.c @@ -220,6 +220,7 @@ struct clk *tegra_clk_register_super_clk(const char *name, super->frac_div.width = 8; super->frac_div.frac_width = 1; super->frac_div.lock = lock; + super->frac_div.flags = TEGRA_DIVIDER_SUPER; super->div_ops = &tegra_clk_frac_div_ops; /* Data in .init is copied by clk_register(), so stack variable OK */ diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 905bf1096558..a4fbf55930aa 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -53,6 +53,9 @@ struct clk *tegra_clk_register_sync_source(const char *name, * TEGRA_DIVIDER_UART - UART module divider has additional enable bit which is * set when divider value is not 0. This flags indicates that the divider * is for UART module. + * TEGRA_DIVIDER_SUPER - Super clock divider has additional enable bit which + * is set when divider value is not 0. This flags indicates that the + * divider is for super clock. */ struct tegra_clk_frac_div { struct clk_hw hw; @@ -70,6 +73,7 @@ struct tegra_clk_frac_div { #define TEGRA_DIVIDER_FIXED BIT(1) #define TEGRA_DIVIDER_INT BIT(2) #define TEGRA_DIVIDER_UART BIT(3) +#define TEGRA_DIVIDER_SUPER BIT(4) extern const struct clk_ops tegra_clk_frac_div_ops; struct clk *tegra_clk_register_divider(const char *name, -- 2.22.0 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v1 1/2] clk: tegra: divider: Fix missing check for enable-bit on rate's recalculation 2019-07-15 17:35 [PATCH v1 1/2] clk: tegra: divider: Fix missing check for enable-bit on rate's recalculation Dmitry Osipenko 2019-07-15 17:35 ` [PATCH v1 2/2] clk: tegra: divider: Support enable-bit for Super clocks Dmitry Osipenko @ 2019-07-17 20:08 ` Stephen Boyd 2019-07-17 21:33 ` Dmitry Osipenko 1 sibling, 1 reply; 6+ messages in thread From: Stephen Boyd @ 2019-07-17 20:08 UTC (permalink / raw) To: Dmitry Osipenko, Jonathan Hunter, Michael Turquette, Peter De Schrijver, Prashant Gaikwad, Thierry Reding Cc: linux-clk, linux-tegra, linux-kernel Quoting Dmitry Osipenko (2019-07-15 10:35:26) > Unset "enable" bit means that divider is in bypass mode, hence it doesn't > have any effect in that case. > > Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Any Fixes tags for these patches? ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v1 1/2] clk: tegra: divider: Fix missing check for enable-bit on rate's recalculation 2019-07-17 20:08 ` [PATCH v1 1/2] clk: tegra: divider: Fix missing check for enable-bit on rate's recalculation Stephen Boyd @ 2019-07-17 21:33 ` Dmitry Osipenko 2019-07-22 21:55 ` Stephen Boyd 0 siblings, 1 reply; 6+ messages in thread From: Dmitry Osipenko @ 2019-07-17 21:33 UTC (permalink / raw) To: Stephen Boyd, Jonathan Hunter, Michael Turquette, Peter De Schrijver, Prashant Gaikwad, Thierry Reding Cc: linux-clk, linux-tegra, linux-kernel 17.07.2019 23:08, Stephen Boyd пишет: > Quoting Dmitry Osipenko (2019-07-15 10:35:26) >> Unset "enable" bit means that divider is in bypass mode, hence it doesn't >> have any effect in that case. >> >> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> > > Any Fixes tags for these patches? I'm not aware of any actual bugs that this change fixes. Probably better to just s/Fix/Add/ in the commit's title? ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v1 1/2] clk: tegra: divider: Fix missing check for enable-bit on rate's recalculation 2019-07-17 21:33 ` Dmitry Osipenko @ 2019-07-22 21:55 ` Stephen Boyd 2019-07-23 0:13 ` Dmitry Osipenko 0 siblings, 1 reply; 6+ messages in thread From: Stephen Boyd @ 2019-07-22 21:55 UTC (permalink / raw) To: Dmitry Osipenko, Jonathan Hunter, Michael Turquette, Peter De Schrijver, Prashant Gaikwad, Thierry Reding Cc: linux-clk, linux-tegra, linux-kernel Quoting Dmitry Osipenko (2019-07-17 14:33:36) > 17.07.2019 23:08, Stephen Boyd пишет: > > Quoting Dmitry Osipenko (2019-07-15 10:35:26) > >> Unset "enable" bit means that divider is in bypass mode, hence it doesn't > >> have any effect in that case. > >> > >> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> > > > > Any Fixes tags for these patches? > > I'm not aware of any actual bugs that this change fixes. Probably better > to just s/Fix/Add/ in the commit's title? Sounds fine to me. ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v1 1/2] clk: tegra: divider: Fix missing check for enable-bit on rate's recalculation 2019-07-22 21:55 ` Stephen Boyd @ 2019-07-23 0:13 ` Dmitry Osipenko 0 siblings, 0 replies; 6+ messages in thread From: Dmitry Osipenko @ 2019-07-23 0:13 UTC (permalink / raw) To: Stephen Boyd, Jonathan Hunter, Michael Turquette, Peter De Schrijver, Prashant Gaikwad, Thierry Reding Cc: linux-clk, linux-tegra, linux-kernel 23.07.2019 0:55, Stephen Boyd пишет: > Quoting Dmitry Osipenko (2019-07-17 14:33:36) >> 17.07.2019 23:08, Stephen Boyd пишет: >>> Quoting Dmitry Osipenko (2019-07-15 10:35:26) >>>> Unset "enable" bit means that divider is in bypass mode, hence it doesn't >>>> have any effect in that case. >>>> >>>> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> >>> >>> Any Fixes tags for these patches? >> >> I'm not aware of any actual bugs that this change fixes. Probably better >> to just s/Fix/Add/ in the commit's title? > > Sounds fine to me. > Okay, I'll re-spin these patches. ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2019-07-23 0:13 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-07-15 17:35 [PATCH v1 1/2] clk: tegra: divider: Fix missing check for enable-bit on rate's recalculation Dmitry Osipenko 2019-07-15 17:35 ` [PATCH v1 2/2] clk: tegra: divider: Support enable-bit for Super clocks Dmitry Osipenko 2019-07-17 20:08 ` [PATCH v1 1/2] clk: tegra: divider: Fix missing check for enable-bit on rate's recalculation Stephen Boyd 2019-07-17 21:33 ` Dmitry Osipenko 2019-07-22 21:55 ` Stephen Boyd 2019-07-23 0:13 ` Dmitry Osipenko
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