* [PATCH 0/7] pinctrl: Fixes for AST2600 support
@ 2019-10-08 4:41 Andrew Jeffery
2019-10-08 4:41 ` [PATCH 1/7] dt-bindings: pinctrl: aspeed-g6: Rework SD3 function and groups Andrew Jeffery
` (8 more replies)
0 siblings, 9 replies; 14+ messages in thread
From: Andrew Jeffery @ 2019-10-08 4:41 UTC (permalink / raw)
To: linux-gpio
Cc: linus.walleij, robh+dt, mark.rutland, joel, linux-aspeed,
devicetree, linux-arm-kernel, linux-kernel, johnny_huang,
ryanchen.aspeed
Hello,
This series resolves several issues found in testing by Johnny Huang from
ASPEED, who also contributed the patches to fix them. We'll have more patches
from him in the near future (which I'm pretty happy about).
The major issue resolved is the way I grouped the eMMC pins. What I had was
ugly and I want to get rid of it before the binding is solidified with the 5.4
release.
The remaining fixes are minor issues that stem from lack of documentation or
understanding on my part, and at least one brain-fart.
Please review!
Andrew
Andrew Jeffery (4):
dt-bindings: pinctrl: aspeed-g6: Rework SD3 function and groups
pinctrl: aspeed-g6: Sort pins for sanity
pinctrl: aspeed-g6: Fix I2C14 SDA description
pinctrl: aspeed-g6: Make SIG_DESC_CLEAR() behave intuitively
Johnny Huang (3):
pinctrl: aspeed-g6: Fix I3C3/I3C4 pinmux configuration
pinctrl: aspeed-g6: Fix UART13 group pinmux
pinctrl: aspeed-g6: Rename SD3 to EMMC and rework pin groups
.../pinctrl/aspeed,ast2600-pinctrl.yaml | 86 ++++++------
drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 124 ++++++++----------
drivers/pinctrl/aspeed/pinmux-aspeed.h | 3 +-
3 files changed, 98 insertions(+), 115 deletions(-)
--
2.20.1
^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH 1/7] dt-bindings: pinctrl: aspeed-g6: Rework SD3 function and groups 2019-10-08 4:41 [PATCH 0/7] pinctrl: Fixes for AST2600 support Andrew Jeffery @ 2019-10-08 4:41 ` Andrew Jeffery 2019-10-15 22:24 ` Rob Herring 2019-10-08 4:41 ` [PATCH 2/7] pinctrl: aspeed-g6: Sort pins for sanity Andrew Jeffery ` (7 subsequent siblings) 8 siblings, 1 reply; 14+ messages in thread From: Andrew Jeffery @ 2019-10-08 4:41 UTC (permalink / raw) To: linux-gpio Cc: linus.walleij, robh+dt, mark.rutland, joel, linux-aspeed, devicetree, linux-arm-kernel, linux-kernel, johnny_huang, ryanchen.aspeed Rename SD3 functions and groups to EMMC to better reflect their intended use before the binding escapes too far into the wild. Also clean up the SD3 pin groups to eliminate some silliness that slipped through the cracks (SD3DAT[4-7]) by unifying them into three new groups: EMMCG1, EMMCG4 and EMMCG8 for 1, 4 and 8-bit data buses respectively. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> --- Unfortunately reflowing the list creates a lot of noise in this change. As mentioned the SD3DAT[4-7] groups are renamed, as is the SD3 function. There should be no functional changes beyond that. .../pinctrl/aspeed,ast2600-pinctrl.yaml | 86 +++++++++---------- 1 file changed, 42 insertions(+), 44 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml index f83d888176cc..064b7dfc4252 100644 --- a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml @@ -33,13 +33,13 @@ patternProperties: allOf: - $ref: "/schemas/types.yaml#/definitions/string" - enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, - ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, ESPI, - ESPIALT, FSI1, FSI2, FWSPIABR, FWSPID, FWSPIWP, GPIT0, GPIT1, - GPIT2, GPIT3, GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1, GPIU2, - GPIU3, GPIU4, GPIU5, GPIU6, GPIU7, I2C1, I2C10, I2C11, I2C12, - I2C13, I2C14, I2C15, I2C16, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7, - I2C8, I2C9, I3C3, I3C4, I3C5, I3C6, JTAGM, LHPD, LHSIRQ, LPC, - LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ, MACLINK1, MACLINK2, + ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMC, + ESPI, ESPIALT, FSI1, FSI2, FWSPIABR, FWSPID, FWSPIWP, GPIT0, + GPIT1, GPIT2, GPIT3, GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1, + GPIU2, GPIU3, GPIU4, GPIU5, GPIU6, GPIU7, I2C1, I2C10, I2C11, + I2C12, I2C13, I2C14, I2C15, I2C16, I2C2, I2C3, I2C4, I2C5, I2C6, + I2C7, I2C8, I2C9, I3C3, I3C4, I3C5, I3C6, JTAGM, LHPD, LHSIRQ, + LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ, MACLINK1, MACLINK2, MACLINK3, MACLINK4, MDIO1, MDIO2, MDIO3, MDIO4, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4, NRTS1, @@ -48,47 +48,45 @@ patternProperties: PWM8, PWM9, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3, RMII4, RXD1, RXD2, RXD3, RXD4, SALT1, SALT10, SALT11, SALT12, SALT13, SALT14, SALT15, SALT16, SALT2, SALT3, SALT4, SALT5, - SALT6, SALT7, SALT8, SALT9, SD1, SD2, SD3, SD3DAT4, SD3DAT5, - SD3DAT6, SD3DAT7, SGPM1, SGPS1, SIOONCTRL, SIOPBI, SIOPBO, - SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1ABR, SPI1CS1, - SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11, - TACH12, TACH13, TACH14, TACH15, TACH2, TACH3, TACH4, TACH5, - TACH6, TACH7, TACH8, TACH9, THRU0, THRU1, THRU2, THRU3, TXD1, - TXD2, TXD3, TXD4, UART10, UART11, UART12, UART13, UART6, UART7, - UART8, UART9, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3, - WDTRST4, ] + SALT6, SALT7, SALT8, SALT9, SD1, SD2, SGPM1, SGPS1, SIOONCTRL, + SIOPBI, SIOPBO, SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, + SPI1ABR, SPI1CS1, SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1, + TACH10, TACH11, TACH12, TACH13, TACH14, TACH15, TACH2, TACH3, + TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0, THRU1, THRU2, + THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12, UART13, + UART6, UART7, UART8, UART9, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, + WDTRST3, WDTRST4, ] groups: allOf: - $ref: "/schemas/types.yaml#/definitions/string" - enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, - ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, ESPI, - ESPIALT, FSI1, FSI2, FWSPIABR, FWSPID, FWQSPID, FWSPIWP, GPIT0, - GPIT1, GPIT2, GPIT3, GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1, - GPIU2, GPIU3, GPIU4, GPIU5, GPIU6, GPIU7, HVI3C3, HVI3C4, I2C1, - I2C10, I2C11, I2C12, I2C13, I2C14, I2C15, I2C16, I2C2, I2C3, - I2C4, I2C5, I2C6, I2C7, I2C8, I2C9, I3C3, I3C4, I3C5, I3C6, - JTAGM, LHPD, LHSIRQ, LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ, - MACLINK1, MACLINK2, MACLINK3, MACLINK4, MDIO1, MDIO2, MDIO3, - MDIO4, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4, - NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, - NRI2, NRI3, NRI4, NRTS1, NRTS2, NRTS3, NRTS4, OSCCLK, PEWAKE, - PWM0, PWM1, PWM10G0, PWM10G1, PWM11G0, PWM11G1, PWM12G0, PWM12G1, - PWM13G0, PWM13G1, PWM14G0, PWM14G1, PWM15G0, PWM15G1, PWM2, PWM3, - PWM4, PWM5, PWM6, PWM7, PWM8G0, PWM8G1, PWM9G0, PWM9G1, QSPI1, - QSPI2, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3, - RMII4, RXD1, RXD2, RXD3, RXD4, SALT1, SALT10G0, SALT10G1, - SALT11G0, SALT11G1, SALT12G0, SALT12G1, SALT13G0, SALT13G1, - SALT14G0, SALT14G1, SALT15G0, SALT15G1, SALT16G0, SALT16G1, - SALT2, SALT3, SALT4, SALT5, SALT6, SALT7, SALT8, SALT9G0, - SALT9G1, SD1, SD2, SD3, SD3DAT4, SD3DAT5, SD3DAT6, SD3DAT7, - SGPM1, SGPS1, SIOONCTRL, SIOPBI, SIOPBO, SIOPWREQ, SIOPWRGD, - SIOS3, SIOS5, SIOSCI, SPI1, SPI1ABR, SPI1CS1, SPI1WP, SPI2, - SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11, TACH12, TACH13, - TACH14, TACH15, TACH2, TACH3, TACH4, TACH5, TACH6, TACH7, TACH8, - TACH9, THRU0, THRU1, THRU2, THRU3, TXD1, TXD2, TXD3, TXD4, - UART10, UART11, UART12G0, UART12G1, UART13G0, UART13G1, UART6, - UART7, UART8, UART9, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3, - WDTRST4, ] + ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMCG1, + EMMCG4, EMMCG8, ESPI, ESPIALT, FSI1, FSI2, FWSPIABR, FWSPID, + FWQSPID, FWSPIWP, GPIT0, GPIT1, GPIT2, GPIT3, GPIT4, GPIT5, + GPIT6, GPIT7, GPIU0, GPIU1, GPIU2, GPIU3, GPIU4, GPIU5, GPIU6, + GPIU7, HVI3C3, HVI3C4, I2C1, I2C10, I2C11, I2C12, I2C13, I2C14, + I2C15, I2C16, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7, I2C8, I2C9, + I3C3, I3C4, I3C5, I3C6, JTAGM, LHPD, LHSIRQ, LPC, LPCHC, LPCPD, + LPCPME, LPCSMI, LSIRQ, MACLINK1, MACLINK2, MACLINK3, MACLINK4, + MDIO1, MDIO2, MDIO3, MDIO4, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, + NDCD2, NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, + NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4, NRTS1, NRTS2, NRTS3, NRTS4, + OSCCLK, PEWAKE, PWM0, PWM1, PWM10G0, PWM10G1, PWM11G0, PWM11G1, + PWM12G0, PWM12G1, PWM13G0, PWM13G1, PWM14G0, PWM14G1, PWM15G0, + PWM15G1, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, PWM8G0, PWM8G1, + PWM9G0, PWM9G1, QSPI1, QSPI2, RGMII1, RGMII2, RGMII3, RGMII4, + RMII1, RMII2, RMII3, RMII4, RXD1, RXD2, RXD3, RXD4, SALT1, + SALT10G0, SALT10G1, SALT11G0, SALT11G1, SALT12G0, SALT12G1, + SALT13G0, SALT13G1, SALT14G0, SALT14G1, SALT15G0, SALT15G1, + SALT16G0, SALT16G1, SALT2, SALT3, SALT4, SALT5, SALT6, SALT7, + SALT8, SALT9G0, SALT9G1, SD1, SD2, SD3, SGPM1, SGPS1, SIOONCTRL, + SIOPBI, SIOPBO, SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, + SPI1ABR, SPI1CS1, SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1, + TACH10, TACH11, TACH12, TACH13, TACH14, TACH15, TACH2, TACH3, + TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0, THRU1, THRU2, + THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12G0, + UART12G1, UART13G0, UART13G1, UART6, UART7, UART8, UART9, VB, + VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3, WDTRST4, ] required: - compatible -- 2.20.1 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH 1/7] dt-bindings: pinctrl: aspeed-g6: Rework SD3 function and groups 2019-10-08 4:41 ` [PATCH 1/7] dt-bindings: pinctrl: aspeed-g6: Rework SD3 function and groups Andrew Jeffery @ 2019-10-15 22:24 ` Rob Herring 0 siblings, 0 replies; 14+ messages in thread From: Rob Herring @ 2019-10-15 22:24 UTC (permalink / raw) To: Andrew Jeffery Cc: linux-gpio, linus.walleij, robh+dt, mark.rutland, joel, linux-aspeed, devicetree, linux-arm-kernel, linux-kernel, johnny_huang, ryanchen.aspeed On Tue, 8 Oct 2019 15:11:47 +1030, Andrew Jeffery wrote: > Rename SD3 functions and groups to EMMC to better reflect their intended > use before the binding escapes too far into the wild. Also clean up the > SD3 pin groups to eliminate some silliness that slipped through the > cracks (SD3DAT[4-7]) by unifying them into three new groups: EMMCG1, > EMMCG4 and EMMCG8 for 1, 4 and 8-bit data buses respectively. > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > --- > Unfortunately reflowing the list creates a lot of noise in this change. As > mentioned the SD3DAT[4-7] groups are renamed, as is the SD3 function. There > should be no functional changes beyond that. > > .../pinctrl/aspeed,ast2600-pinctrl.yaml | 86 +++++++++---------- > 1 file changed, 42 insertions(+), 44 deletions(-) > Reviewed-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 2/7] pinctrl: aspeed-g6: Sort pins for sanity 2019-10-08 4:41 [PATCH 0/7] pinctrl: Fixes for AST2600 support Andrew Jeffery 2019-10-08 4:41 ` [PATCH 1/7] dt-bindings: pinctrl: aspeed-g6: Rework SD3 function and groups Andrew Jeffery @ 2019-10-08 4:41 ` Andrew Jeffery 2019-10-08 4:41 ` [PATCH 3/7] pinctrl: aspeed-g6: Fix I2C14 SDA description Andrew Jeffery ` (6 subsequent siblings) 8 siblings, 0 replies; 14+ messages in thread From: Andrew Jeffery @ 2019-10-08 4:41 UTC (permalink / raw) To: linux-gpio Cc: linus.walleij, robh+dt, mark.rutland, joel, linux-aspeed, devicetree, linux-arm-kernel, linux-kernel, johnny_huang, ryanchen.aspeed Some pins crept in that weren't ordered in the list. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> --- drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c index 648ddb7f038a..ff208b7c75a8 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c @@ -1574,6 +1574,8 @@ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = { ASPEED_PINCTRL_PIN(A3), ASPEED_PINCTRL_PIN(AA11), ASPEED_PINCTRL_PIN(AA12), + ASPEED_PINCTRL_PIN(AA16), + ASPEED_PINCTRL_PIN(AA17), ASPEED_PINCTRL_PIN(AA23), ASPEED_PINCTRL_PIN(AA24), ASPEED_PINCTRL_PIN(AA25), @@ -1585,6 +1587,8 @@ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = { ASPEED_PINCTRL_PIN(AB11), ASPEED_PINCTRL_PIN(AB12), ASPEED_PINCTRL_PIN(AB15), + ASPEED_PINCTRL_PIN(AB16), + ASPEED_PINCTRL_PIN(AB17), ASPEED_PINCTRL_PIN(AB18), ASPEED_PINCTRL_PIN(AB19), ASPEED_PINCTRL_PIN(AB22), @@ -1602,6 +1606,7 @@ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = { ASPEED_PINCTRL_PIN(AC11), ASPEED_PINCTRL_PIN(AC12), ASPEED_PINCTRL_PIN(AC15), + ASPEED_PINCTRL_PIN(AC16), ASPEED_PINCTRL_PIN(AC17), ASPEED_PINCTRL_PIN(AC18), ASPEED_PINCTRL_PIN(AC19), @@ -1619,6 +1624,7 @@ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = { ASPEED_PINCTRL_PIN(AD12), ASPEED_PINCTRL_PIN(AD14), ASPEED_PINCTRL_PIN(AD15), + ASPEED_PINCTRL_PIN(AD16), ASPEED_PINCTRL_PIN(AD19), ASPEED_PINCTRL_PIN(AD20), ASPEED_PINCTRL_PIN(AD22), @@ -1634,8 +1640,11 @@ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = { ASPEED_PINCTRL_PIN(AE12), ASPEED_PINCTRL_PIN(AE14), ASPEED_PINCTRL_PIN(AE15), + ASPEED_PINCTRL_PIN(AE16), ASPEED_PINCTRL_PIN(AE18), ASPEED_PINCTRL_PIN(AE19), + ASPEED_PINCTRL_PIN(AE25), + ASPEED_PINCTRL_PIN(AE26), ASPEED_PINCTRL_PIN(AE7), ASPEED_PINCTRL_PIN(AE8), ASPEED_PINCTRL_PIN(AF10), @@ -1643,6 +1652,8 @@ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = { ASPEED_PINCTRL_PIN(AF12), ASPEED_PINCTRL_PIN(AF14), ASPEED_PINCTRL_PIN(AF15), + ASPEED_PINCTRL_PIN(AF24), + ASPEED_PINCTRL_PIN(AF25), ASPEED_PINCTRL_PIN(AF7), ASPEED_PINCTRL_PIN(AF8), ASPEED_PINCTRL_PIN(AF9), @@ -1792,17 +1803,6 @@ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = { ASPEED_PINCTRL_PIN(Y3), ASPEED_PINCTRL_PIN(Y4), ASPEED_PINCTRL_PIN(Y5), - ASPEED_PINCTRL_PIN(AB16), - ASPEED_PINCTRL_PIN(AA17), - ASPEED_PINCTRL_PIN(AB17), - ASPEED_PINCTRL_PIN(AE16), - ASPEED_PINCTRL_PIN(AC16), - ASPEED_PINCTRL_PIN(AA16), - ASPEED_PINCTRL_PIN(AD16), - ASPEED_PINCTRL_PIN(AF25), - ASPEED_PINCTRL_PIN(AE26), - ASPEED_PINCTRL_PIN(AE25), - ASPEED_PINCTRL_PIN(AF24), }; static const struct aspeed_pin_group aspeed_g6_groups[] = { -- 2.20.1 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 3/7] pinctrl: aspeed-g6: Fix I2C14 SDA description 2019-10-08 4:41 [PATCH 0/7] pinctrl: Fixes for AST2600 support Andrew Jeffery 2019-10-08 4:41 ` [PATCH 1/7] dt-bindings: pinctrl: aspeed-g6: Rework SD3 function and groups Andrew Jeffery 2019-10-08 4:41 ` [PATCH 2/7] pinctrl: aspeed-g6: Sort pins for sanity Andrew Jeffery @ 2019-10-08 4:41 ` Andrew Jeffery 2019-10-08 4:41 ` [PATCH 4/7] pinctrl: aspeed-g6: Fix I3C3/I3C4 pinmux configuration Andrew Jeffery ` (5 subsequent siblings) 8 siblings, 0 replies; 14+ messages in thread From: Andrew Jeffery @ 2019-10-08 4:41 UTC (permalink / raw) To: linux-gpio Cc: linus.walleij, robh+dt, mark.rutland, joel, linux-aspeed, devicetree, linux-arm-kernel, linux-kernel, johnny_huang, ryanchen.aspeed The I2C function the pin participated in was incorrectly named SDA14 which lead to a failure to mux: [ 6.884344] No function I2C14 found on pin 7 (7). Found signal(s) MACLINK4, SDA14, GPIOA7 for function(s) MACLINK4, SDA14, GPIOA7 Fixes: 58dc52ad00a0 ("pinctrl: aspeed: Add AST2600 pinmux support") Signed-off-by: Andrew Jeffery <andrew@aj.id.au> --- drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c index ff208b7c75a8..9079655cc818 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c @@ -87,7 +87,7 @@ FUNC_GROUP_DECL(MACLINK3, L23); #define K25 7 SIG_EXPR_LIST_DECL_SESG(K25, MACLINK4, MACLINK4, SIG_DESC_SET(SCU410, 7)); -SIG_EXPR_LIST_DECL_SESG(K25, SDA14, SDA14, SIG_DESC_SET(SCU4B0, 7)); +SIG_EXPR_LIST_DECL_SESG(K25, SDA14, I2C14, SIG_DESC_SET(SCU4B0, 7)); PIN_DECL_2(K25, GPIOA7, MACLINK4, SDA14); FUNC_GROUP_DECL(MACLINK4, K25); -- 2.20.1 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 4/7] pinctrl: aspeed-g6: Fix I3C3/I3C4 pinmux configuration 2019-10-08 4:41 [PATCH 0/7] pinctrl: Fixes for AST2600 support Andrew Jeffery ` (2 preceding siblings ...) 2019-10-08 4:41 ` [PATCH 3/7] pinctrl: aspeed-g6: Fix I2C14 SDA description Andrew Jeffery @ 2019-10-08 4:41 ` Andrew Jeffery 2019-10-08 4:41 ` [PATCH 5/7] pinctrl: aspeed-g6: Make SIG_DESC_CLEAR() behave intuitively Andrew Jeffery ` (4 subsequent siblings) 8 siblings, 0 replies; 14+ messages in thread From: Andrew Jeffery @ 2019-10-08 4:41 UTC (permalink / raw) To: linux-gpio Cc: Johnny Huang, linus.walleij, robh+dt, mark.rutland, joel, linux-aspeed, devicetree, linux-arm-kernel, linux-kernel, ryanchen.aspeed From: Johnny Huang <johnny_huang@aspeedtech.com> The documentation to configure I3C3/FSI1 and I3C4/FSI2 was initially unclear. Fixes: 58dc52ad00a0 ("pinctrl: aspeed: Add AST2600 pinmux support") Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> [AJ: Tweak commit message, resolve rebase conflicts] Signed-off-by: Andrew Jeffery <andrew@aj.id.au> --- drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 24 ++++++++-------------- 1 file changed, 8 insertions(+), 16 deletions(-) diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c index 9079655cc818..68b066594461 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c @@ -1513,18 +1513,14 @@ FUNC_GROUP_DECL(VB, Y1, Y2, Y3, Y4); * following 4 pins */ #define AF25 244 -SIG_EXPR_LIST_DECL_SEMG(AF25, I3C3SCL, I3C3, I3C3, SIG_DESC_SET(SCU438, 20), - SIG_DESC_SET(SCU4D8, 20)); -SIG_EXPR_LIST_DECL_SESG(AF25, FSI1CLK, FSI1, SIG_DESC_CLEAR(SCU438, 20), - SIG_DESC_SET(SCU4D8, 20)); +SIG_EXPR_LIST_DECL_SEMG(AF25, I3C3SCL, I3C3, I3C3, SIG_DESC_SET(SCU438, 20)); +SIG_EXPR_LIST_DECL_SESG(AF25, FSI1CLK, FSI1, SIG_DESC_SET(SCU4D8, 20)); PIN_DECL_(AF25, SIG_EXPR_LIST_PTR(AF25, I3C3SCL), SIG_EXPR_LIST_PTR(AF25, FSI1CLK)); #define AE26 245 -SIG_EXPR_LIST_DECL_SEMG(AE26, I3C3SDA, I3C3, I3C3, SIG_DESC_SET(SCU438, 21), - SIG_DESC_SET(SCU4D8, 21)); -SIG_EXPR_LIST_DECL_SESG(AE26, FSI1DATA, FSI1, SIG_DESC_CLEAR(SCU438, 21), - SIG_DESC_SET(SCU4D8, 21)); +SIG_EXPR_LIST_DECL_SEMG(AE26, I3C3SDA, I3C3, I3C3, SIG_DESC_SET(SCU438, 21)); +SIG_EXPR_LIST_DECL_SESG(AE26, FSI1DATA, FSI1, SIG_DESC_SET(SCU4D8, 21)); PIN_DECL_(AE26, SIG_EXPR_LIST_PTR(AE26, I3C3SDA), SIG_EXPR_LIST_PTR(AE26, FSI1DATA)); @@ -1533,18 +1529,14 @@ FUNC_DECL_2(I3C3, HVI3C3, I3C3); FUNC_GROUP_DECL(FSI1, AF25, AE26); #define AE25 246 -SIG_EXPR_LIST_DECL_SEMG(AE25, I3C4SCL, I3C4, I3C4, SIG_DESC_SET(SCU438, 22), - SIG_DESC_SET(SCU4D8, 22)); -SIG_EXPR_LIST_DECL_SESG(AE25, FSI2CLK, FSI2, SIG_DESC_CLEAR(SCU438, 22), - SIG_DESC_SET(SCU4D8, 22)); +SIG_EXPR_LIST_DECL_SEMG(AE25, I3C4SCL, I3C4, I3C4, SIG_DESC_SET(SCU438, 22)); +SIG_EXPR_LIST_DECL_SESG(AE25, FSI2CLK, FSI2, SIG_DESC_SET(SCU4D8, 22)); PIN_DECL_(AE25, SIG_EXPR_LIST_PTR(AE25, I3C4SCL), SIG_EXPR_LIST_PTR(AE25, FSI2CLK)); #define AF24 247 -SIG_EXPR_LIST_DECL_SEMG(AF24, I3C4SDA, I3C4, I3C4, SIG_DESC_SET(SCU438, 23), - SIG_DESC_SET(SCU4D8, 23)); -SIG_EXPR_LIST_DECL_SESG(AF24, FSI2DATA, FSI2, SIG_DESC_CLEAR(SCU438, 23), - SIG_DESC_SET(SCU4D8, 23)); +SIG_EXPR_LIST_DECL_SEMG(AF24, I3C4SDA, I3C4, I3C4, SIG_DESC_SET(SCU438, 23)); +SIG_EXPR_LIST_DECL_SESG(AF24, FSI2DATA, FSI2, SIG_DESC_SET(SCU4D8, 23)); PIN_DECL_(AF24, SIG_EXPR_LIST_PTR(AF24, I3C4SDA), SIG_EXPR_LIST_PTR(AF24, FSI2DATA)); -- 2.20.1 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 5/7] pinctrl: aspeed-g6: Make SIG_DESC_CLEAR() behave intuitively 2019-10-08 4:41 [PATCH 0/7] pinctrl: Fixes for AST2600 support Andrew Jeffery ` (3 preceding siblings ...) 2019-10-08 4:41 ` [PATCH 4/7] pinctrl: aspeed-g6: Fix I3C3/I3C4 pinmux configuration Andrew Jeffery @ 2019-10-08 4:41 ` Andrew Jeffery 2019-10-08 4:41 ` [PATCH 6/7] pinctrl: aspeed-g6: Fix UART13 group pinmux Andrew Jeffery ` (3 subsequent siblings) 8 siblings, 0 replies; 14+ messages in thread From: Andrew Jeffery @ 2019-10-08 4:41 UTC (permalink / raw) To: linux-gpio Cc: linus.walleij, robh+dt, mark.rutland, joel, linux-aspeed, devicetree, linux-arm-kernel, linux-kernel, johnny_huang, ryanchen.aspeed Signal descriptors can represent multi-bit bitfields and so have explicit "enable" and "disable" states. However many descriptor instances only describe a single bit, and so the SIG_DESC_SET() macro is provides an abstraction for the single-bit cases: Its expansion configures the "enable" state to set the bit and "disable" to clear. SIG_DESC_CLEAR() was introduced to provide a similar single-bit abstraction for for descriptors to clear the bit of interest. However its behaviour was defined as the literal inverse of SIG_DESC_SET() - the impact is the bit of interest is set in the disable path. This behaviour isn't intuitive and doesn't align with how we want to use the macro in practice, so make it clear the bit for both the enable and disable paths. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> --- drivers/pinctrl/aspeed/pinmux-aspeed.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/aspeed/pinmux-aspeed.h b/drivers/pinctrl/aspeed/pinmux-aspeed.h index a2c0d52e4f7b..d5202241f411 100644 --- a/drivers/pinctrl/aspeed/pinmux-aspeed.h +++ b/drivers/pinctrl/aspeed/pinmux-aspeed.h @@ -508,7 +508,7 @@ struct aspeed_pin_desc { * @idx: The bit index in the register */ #define SIG_DESC_SET(reg, idx) SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, 1) -#define SIG_DESC_CLEAR(reg, idx) SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, 0) +#define SIG_DESC_CLEAR(reg, idx) { ASPEED_IP_SCU, reg, BIT_MASK(idx), 0, 0 } #define SIG_DESC_LIST_SYM(sig, group) sig_descs_ ## sig ## _ ## group #define SIG_DESC_LIST_DECL(sig, group, ...) \ -- 2.20.1 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 6/7] pinctrl: aspeed-g6: Fix UART13 group pinmux 2019-10-08 4:41 [PATCH 0/7] pinctrl: Fixes for AST2600 support Andrew Jeffery ` (4 preceding siblings ...) 2019-10-08 4:41 ` [PATCH 5/7] pinctrl: aspeed-g6: Make SIG_DESC_CLEAR() behave intuitively Andrew Jeffery @ 2019-10-08 4:41 ` Andrew Jeffery 2019-10-08 4:41 ` [PATCH 7/7] pinctrl: aspeed-g6: Rename SD3 to EMMC and rework pin groups Andrew Jeffery ` (2 subsequent siblings) 8 siblings, 0 replies; 14+ messages in thread From: Andrew Jeffery @ 2019-10-08 4:41 UTC (permalink / raw) To: linux-gpio Cc: Johnny Huang, linus.walleij, robh+dt, mark.rutland, joel, linux-aspeed, devicetree, linux-arm-kernel, linux-kernel, ryanchen.aspeed From: Johnny Huang <johnny_huang@aspeedtech.com> When UART13G1 is set the pinmux configuration in SCU4B8 for UART13G0 should be cleared. Fixes: 58dc52ad00a0 ("pinctrl: aspeed: Add AST2600 pinmux support") Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> [AJ: Tweak commit message] Signed-off-by: Andrew Jeffery <andrew@aj.id.au> --- drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c index 68b066594461..dc17cf3d3549 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c @@ -1262,13 +1262,13 @@ GROUP_DECL(SPI1, AB11, AC11, AA11); #define AD11 206 SIG_EXPR_LIST_DECL_SEMG(AD11, SPI1DQ2, QSPI1, SPI1, SIG_DESC_SET(SCU438, 14)); SIG_EXPR_LIST_DECL_SEMG(AD11, TXD13, UART13G1, UART13, - SIG_DESC_SET(SCU438, 14)); + SIG_DESC_CLEAR(SCU4B8, 2), SIG_DESC_SET(SCU4D8, 14)); PIN_DECL_2(AD11, GPIOZ6, SPI1DQ2, TXD13); #define AF10 207 SIG_EXPR_LIST_DECL_SEMG(AF10, SPI1DQ3, QSPI1, SPI1, SIG_DESC_SET(SCU438, 15)); SIG_EXPR_LIST_DECL_SEMG(AF10, RXD13, UART13G1, UART13, - SIG_DESC_SET(SCU438, 15)); + SIG_DESC_CLEAR(SCU4B8, 3), SIG_DESC_SET(SCU4D8, 15)); PIN_DECL_2(AF10, GPIOZ7, SPI1DQ3, RXD13); GROUP_DECL(QSPI1, AB11, AC11, AA11, AD11, AF10); -- 2.20.1 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 7/7] pinctrl: aspeed-g6: Rename SD3 to EMMC and rework pin groups 2019-10-08 4:41 [PATCH 0/7] pinctrl: Fixes for AST2600 support Andrew Jeffery ` (5 preceding siblings ...) 2019-10-08 4:41 ` [PATCH 6/7] pinctrl: aspeed-g6: Fix UART13 group pinmux Andrew Jeffery @ 2019-10-08 4:41 ` Andrew Jeffery 2019-10-08 4:54 ` [PATCH 0/7] pinctrl: Fixes for AST2600 support Joel Stanley 2019-10-16 11:19 ` Linus Walleij 8 siblings, 0 replies; 14+ messages in thread From: Andrew Jeffery @ 2019-10-08 4:41 UTC (permalink / raw) To: linux-gpio Cc: Johnny Huang, linus.walleij, robh+dt, mark.rutland, joel, linux-aspeed, devicetree, linux-arm-kernel, linux-kernel, ryanchen.aspeed From: Johnny Huang <johnny_huang@aspeedtech.com> AST2600 EMMC support 3 types DAT bus sizes (1, 4 and 8-bit), corresponding to 3 groups: EMMCG1, EMMCG4 and EMMCG8 Fixes: 58dc52ad00a0 ("pinctrl: aspeed: Add AST2600 pinmux support") Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> --- drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 72 ++++++++++------------ drivers/pinctrl/aspeed/pinmux-aspeed.h | 1 + 2 files changed, 33 insertions(+), 40 deletions(-) diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c index dc17cf3d3549..c6800d220920 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c @@ -1440,74 +1440,72 @@ FUNC_GROUP_DECL(RGMII2, D4, C2, C1, D3, E4, F5, D2, E3, D1, F4, E2, E1); FUNC_GROUP_DECL(RMII2, D4, C2, C1, D3, D2, D1, F4, E2, E1); #define AB4 232 -SIG_EXPR_LIST_DECL_SESG(AB4, SD3CLK, SD3, SIG_DESC_SET(SCU400, 24)); -PIN_DECL_1(AB4, GPIO18D0, SD3CLK); +SIG_EXPR_LIST_DECL_SEMG(AB4, EMMCCLK, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 24)); +PIN_DECL_1(AB4, GPIO18D0, EMMCCLK); #define AA4 233 -SIG_EXPR_LIST_DECL_SESG(AA4, SD3CMD, SD3, SIG_DESC_SET(SCU400, 25)); -PIN_DECL_1(AA4, GPIO18D1, SD3CMD); +SIG_EXPR_LIST_DECL_SEMG(AA4, EMMCCMD, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 25)); +PIN_DECL_1(AA4, GPIO18D1, EMMCCMD); #define AC4 234 -SIG_EXPR_LIST_DECL_SESG(AC4, SD3DAT0, SD3, SIG_DESC_SET(SCU400, 26)); -PIN_DECL_1(AC4, GPIO18D2, SD3DAT0); +SIG_EXPR_LIST_DECL_SEMG(AC4, EMMCDAT0, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 26)); +PIN_DECL_1(AC4, GPIO18D2, EMMCDAT0); #define AA5 235 -SIG_EXPR_LIST_DECL_SESG(AA5, SD3DAT1, SD3, SIG_DESC_SET(SCU400, 27)); -PIN_DECL_1(AA5, GPIO18D3, SD3DAT1); +SIG_EXPR_LIST_DECL_SEMG(AA5, EMMCDAT1, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 27)); +PIN_DECL_1(AA5, GPIO18D3, EMMCDAT1); #define Y5 236 -SIG_EXPR_LIST_DECL_SESG(Y5, SD3DAT2, SD3, SIG_DESC_SET(SCU400, 28)); -PIN_DECL_1(Y5, GPIO18D4, SD3DAT2); +SIG_EXPR_LIST_DECL_SEMG(Y5, EMMCDAT2, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 28)); +PIN_DECL_1(Y5, GPIO18D4, EMMCDAT2); #define AB5 237 -SIG_EXPR_LIST_DECL_SESG(AB5, SD3DAT3, SD3, SIG_DESC_SET(SCU400, 29)); -PIN_DECL_1(AB5, GPIO18D5, SD3DAT3); +SIG_EXPR_LIST_DECL_SEMG(AB5, EMMCDAT3, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 29)); +PIN_DECL_1(AB5, GPIO18D5, EMMCDAT3); #define AB6 238 -SIG_EXPR_LIST_DECL_SESG(AB6, SD3CD, SD3, SIG_DESC_SET(SCU400, 30)); -PIN_DECL_1(AB6, GPIO18D6, SD3CD); +SIG_EXPR_LIST_DECL_SEMG(AB6, EMMCCD, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 30)); +PIN_DECL_1(AB6, GPIO18D6, EMMCCD); #define AC5 239 -SIG_EXPR_LIST_DECL_SESG(AC5, SD3WP, SD3, SIG_DESC_SET(SCU400, 31)); -PIN_DECL_1(AC5, GPIO18D7, SD3WP); +SIG_EXPR_LIST_DECL_SEMG(AC5, EMMCWP, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 31)); +PIN_DECL_1(AC5, GPIO18D7, EMMCWP); -FUNC_GROUP_DECL(SD3, AB4, AA4, AC4, AA5, Y5, AB5, AB6, AC5); +GROUP_DECL(EMMCG1, AB4, AA4, AC4, AB6, AC5); +GROUP_DECL(EMMCG4, AB4, AA4, AC4, AA5, Y5, AB5, AB6, AC5); #define Y1 240 SIG_EXPR_LIST_DECL_SEMG(Y1, FWSPIDCS, FWSPID, FWSPID, SIG_DESC_SET(SCU500, 3)); SIG_EXPR_LIST_DECL_SESG(Y1, VBCS, VB, SIG_DESC_SET(SCU500, 5)); -SIG_EXPR_LIST_DECL_SESG(Y1, SD3DAT4, SD3DAT4, SIG_DESC_SET(SCU404, 0)); -PIN_DECL_3(Y1, GPIO18E0, FWSPIDCS, VBCS, SD3DAT4); -FUNC_GROUP_DECL(SD3DAT4, Y1); +SIG_EXPR_LIST_DECL_SEMG(Y1, EMMCDAT4, EMMCG8, EMMC, SIG_DESC_SET(SCU404, 0)); +PIN_DECL_3(Y1, GPIO18E0, FWSPIDCS, VBCS, EMMCDAT4); #define Y2 241 SIG_EXPR_LIST_DECL_SEMG(Y2, FWSPIDCK, FWSPID, FWSPID, SIG_DESC_SET(SCU500, 3)); SIG_EXPR_LIST_DECL_SESG(Y2, VBCK, VB, SIG_DESC_SET(SCU500, 5)); -SIG_EXPR_LIST_DECL_SESG(Y2, SD3DAT5, SD3DAT5, SIG_DESC_SET(SCU404, 1)); -PIN_DECL_3(Y2, GPIO18E1, FWSPIDCK, VBCK, SD3DAT5); -FUNC_GROUP_DECL(SD3DAT5, Y2); +SIG_EXPR_LIST_DECL_SEMG(Y2, EMMCDAT5, EMMCG8, EMMC, SIG_DESC_SET(SCU404, 1)); +PIN_DECL_3(Y2, GPIO18E1, FWSPIDCK, VBCK, EMMCDAT5); #define Y3 242 SIG_EXPR_LIST_DECL_SEMG(Y3, FWSPIDMOSI, FWSPID, FWSPID, SIG_DESC_SET(SCU500, 3)); SIG_EXPR_LIST_DECL_SESG(Y3, VBMOSI, VB, SIG_DESC_SET(SCU500, 5)); -SIG_EXPR_LIST_DECL_SESG(Y3, SD3DAT6, SD3DAT6, SIG_DESC_SET(SCU404, 2)); -PIN_DECL_3(Y3, GPIO18E2, FWSPIDMOSI, VBMOSI, SD3DAT6); -FUNC_GROUP_DECL(SD3DAT6, Y3); +SIG_EXPR_LIST_DECL_SEMG(Y3, EMMCDAT6, EMMCG8, EMMC, SIG_DESC_SET(SCU404, 2)); +PIN_DECL_3(Y3, GPIO18E2, FWSPIDMOSI, VBMOSI, EMMCDAT6); #define Y4 243 SIG_EXPR_LIST_DECL_SEMG(Y4, FWSPIDMISO, FWSPID, FWSPID, SIG_DESC_SET(SCU500, 3)); SIG_EXPR_LIST_DECL_SESG(Y4, VBMISO, VB, SIG_DESC_SET(SCU500, 5)); -SIG_EXPR_LIST_DECL_SESG(Y4, SD3DAT7, SD3DAT7, SIG_DESC_SET(SCU404, 3)); -PIN_DECL_3(Y4, GPIO18E3, FWSPIDMISO, VBMISO, SD3DAT7); -FUNC_GROUP_DECL(SD3DAT7, Y4); +SIG_EXPR_LIST_DECL_SEMG(Y4, EMMCDAT7, EMMCG8, EMMC, SIG_DESC_SET(SCU404, 3)); +PIN_DECL_3(Y4, GPIO18E3, FWSPIDMISO, VBMISO, EMMCDAT7); GROUP_DECL(FWSPID, Y1, Y2, Y3, Y4); GROUP_DECL(FWQSPID, Y1, Y2, Y3, Y4, AE12, AF12); +GROUP_DECL(EMMCG8, AB4, AA4, AC4, AA5, Y5, AB5, AB6, AC5, Y1, Y2, Y3, Y4); FUNC_DECL_2(FWSPID, FWSPID, FWQSPID); FUNC_GROUP_DECL(VB, Y1, Y2, Y3, Y4); - +FUNC_DECL_3(EMMC, EMMCG1, EMMCG4, EMMCG8); /* * FIXME: Confirm bits and priorities are the right way around for the * following 4 pins @@ -1968,11 +1966,9 @@ static const struct aspeed_pin_group aspeed_g6_groups[] = { ASPEED_PINCTRL_GROUP(SALT9G1), ASPEED_PINCTRL_GROUP(SD1), ASPEED_PINCTRL_GROUP(SD2), - ASPEED_PINCTRL_GROUP(SD3), - ASPEED_PINCTRL_GROUP(SD3DAT4), - ASPEED_PINCTRL_GROUP(SD3DAT5), - ASPEED_PINCTRL_GROUP(SD3DAT6), - ASPEED_PINCTRL_GROUP(SD3DAT7), + ASPEED_PINCTRL_GROUP(EMMCG1), + ASPEED_PINCTRL_GROUP(EMMCG4), + ASPEED_PINCTRL_GROUP(EMMCG8), ASPEED_PINCTRL_GROUP(SGPM1), ASPEED_PINCTRL_GROUP(SGPS1), ASPEED_PINCTRL_GROUP(SIOONCTRL), @@ -2051,6 +2047,7 @@ static const struct aspeed_pin_function aspeed_g6_functions[] = { ASPEED_PINCTRL_FUNC(ADC8), ASPEED_PINCTRL_FUNC(ADC9), ASPEED_PINCTRL_FUNC(BMCINT), + ASPEED_PINCTRL_FUNC(EMMC), ASPEED_PINCTRL_FUNC(ESPI), ASPEED_PINCTRL_FUNC(ESPIALT), ASPEED_PINCTRL_FUNC(FSI1), @@ -2183,11 +2180,6 @@ static const struct aspeed_pin_function aspeed_g6_functions[] = { ASPEED_PINCTRL_FUNC(SALT9), ASPEED_PINCTRL_FUNC(SD1), ASPEED_PINCTRL_FUNC(SD2), - ASPEED_PINCTRL_FUNC(SD3), - ASPEED_PINCTRL_FUNC(SD3DAT4), - ASPEED_PINCTRL_FUNC(SD3DAT5), - ASPEED_PINCTRL_FUNC(SD3DAT6), - ASPEED_PINCTRL_FUNC(SD3DAT7), ASPEED_PINCTRL_FUNC(SGPM1), ASPEED_PINCTRL_FUNC(SGPS1), ASPEED_PINCTRL_FUNC(SIOONCTRL), diff --git a/drivers/pinctrl/aspeed/pinmux-aspeed.h b/drivers/pinctrl/aspeed/pinmux-aspeed.h index d5202241f411..140c5ce9fbc1 100644 --- a/drivers/pinctrl/aspeed/pinmux-aspeed.h +++ b/drivers/pinctrl/aspeed/pinmux-aspeed.h @@ -738,6 +738,7 @@ struct aspeed_pin_desc { static const char *FUNC_SYM(func)[] = { __VA_ARGS__ } #define FUNC_DECL_2(func, one, two) FUNC_DECL_(func, #one, #two) +#define FUNC_DECL_3(func, one, two, three) FUNC_DECL_(func, #one, #two, #three) #define FUNC_GROUP_DECL(func, ...) \ GROUP_DECL(func, __VA_ARGS__); \ -- 2.20.1 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH 0/7] pinctrl: Fixes for AST2600 support 2019-10-08 4:41 [PATCH 0/7] pinctrl: Fixes for AST2600 support Andrew Jeffery ` (6 preceding siblings ...) 2019-10-08 4:41 ` [PATCH 7/7] pinctrl: aspeed-g6: Rename SD3 to EMMC and rework pin groups Andrew Jeffery @ 2019-10-08 4:54 ` Joel Stanley 2019-10-16 11:19 ` Linus Walleij 8 siblings, 0 replies; 14+ messages in thread From: Joel Stanley @ 2019-10-08 4:54 UTC (permalink / raw) To: Andrew Jeffery Cc: open list:GPIO SUBSYSTEM, Linus Walleij, Rob Herring, Mark Rutland, linux-aspeed, devicetree, Linux ARM, Linux Kernel Mailing List, johnny_huang, Ryan Chen On Tue, 8 Oct 2019 at 04:41, Andrew Jeffery <andrew@aj.id.au> wrote: > > Hello, > > This series resolves several issues found in testing by Johnny Huang from > ASPEED, who also contributed the patches to fix them. We'll have more patches > from him in the near future (which I'm pretty happy about). For the series: Reviewed-by: Joel Stanley <joel@jms.id.au> These patches have been in the OpenBMC tree for a while and look good. Cheers, Joel > > The major issue resolved is the way I grouped the eMMC pins. What I had was > ugly and I want to get rid of it before the binding is solidified with the 5.4 > release. > > The remaining fixes are minor issues that stem from lack of documentation or > understanding on my part, and at least one brain-fart. > > Please review! > > Andrew > > Andrew Jeffery (4): > dt-bindings: pinctrl: aspeed-g6: Rework SD3 function and groups > pinctrl: aspeed-g6: Sort pins for sanity > pinctrl: aspeed-g6: Fix I2C14 SDA description > pinctrl: aspeed-g6: Make SIG_DESC_CLEAR() behave intuitively > > Johnny Huang (3): > pinctrl: aspeed-g6: Fix I3C3/I3C4 pinmux configuration > pinctrl: aspeed-g6: Fix UART13 group pinmux > pinctrl: aspeed-g6: Rename SD3 to EMMC and rework pin groups > > .../pinctrl/aspeed,ast2600-pinctrl.yaml | 86 ++++++------ > drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 124 ++++++++---------- > drivers/pinctrl/aspeed/pinmux-aspeed.h | 3 +- > 3 files changed, 98 insertions(+), 115 deletions(-) > > -- > 2.20.1 > ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 0/7] pinctrl: Fixes for AST2600 support 2019-10-08 4:41 [PATCH 0/7] pinctrl: Fixes for AST2600 support Andrew Jeffery ` (7 preceding siblings ...) 2019-10-08 4:54 ` [PATCH 0/7] pinctrl: Fixes for AST2600 support Joel Stanley @ 2019-10-16 11:19 ` Linus Walleij 2019-10-16 11:41 ` Andrew Jeffery 8 siblings, 1 reply; 14+ messages in thread From: Linus Walleij @ 2019-10-16 11:19 UTC (permalink / raw) To: Andrew Jeffery Cc: open list:GPIO SUBSYSTEM, Rob Herring, Mark Rutland, Joel Stanley, linux-aspeed, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Linux ARM, linux-kernel, johnny_huang, ryanchen.aspeed On Tue, Oct 8, 2019 at 6:41 AM Andrew Jeffery <andrew@aj.id.au> wrote: > This series resolves several issues found in testing by Johnny Huang from > ASPEED, who also contributed the patches to fix them. We'll have more patches > from him in the near future (which I'm pretty happy about). > > The major issue resolved is the way I grouped the eMMC pins. What I had was > ugly and I want to get rid of it before the binding is solidified with the 5.4 > release. Should some of these go in with fixes? All of them? Or just some? I applied them to devel right now (for v5.5). > The remaining fixes are minor issues that stem from lack of documentation or > understanding on my part, and at least one brain-fart. Do they need to go in to v5.4 or not? I need a shortlist of anything that should go into v5.4 if anything. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 0/7] pinctrl: Fixes for AST2600 support 2019-10-16 11:19 ` Linus Walleij @ 2019-10-16 11:41 ` Andrew Jeffery 2019-10-16 14:00 ` Linus Walleij 0 siblings, 1 reply; 14+ messages in thread From: Andrew Jeffery @ 2019-10-16 11:41 UTC (permalink / raw) To: Linus Walleij Cc: open list:GPIO SUBSYSTEM, Rob Herring, Mark Rutland, Joel Stanley, linux-aspeed, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Linux ARM, linux-kernel, Johnny Huang, Ryan Chen On Wed, 16 Oct 2019, at 21:49, Linus Walleij wrote: > On Tue, Oct 8, 2019 at 6:41 AM Andrew Jeffery <andrew@aj.id.au> wrote: > > > This series resolves several issues found in testing by Johnny Huang from > > ASPEED, who also contributed the patches to fix them. We'll have more patches > > from him in the near future (which I'm pretty happy about). > > > > The major issue resolved is the way I grouped the eMMC pins. What I had was > > ugly and I want to get rid of it before the binding is solidified with the 5.4 > > release. > > Should some of these go in with fixes? All of them? Or just some? > I applied them to devel right now (for v5.5). I was hoping to get them into the 5.4 fixes branch: I consider them all fixes - the rework of the eMMC pin groups and functions is a fix for the binding. The rest are fixes for the driver itself. My preference is that they get into a release sooner rather than later. It's there something that makes you think they shouldn't be merged as fixes for 5.4? > > > The remaining fixes are minor issues that stem from lack of documentation or > > understanding on my part, and at least one brain-fart. > > Do they need to go in to v5.4 or not? > > I need a shortlist of anything that should go into v5.4 if anything. IMO all of them should go into 5.4, as above. It's there something I can do in the future to communicate this better? Explicit shortlist in the cover letter? Fixes tags on the relevant patches? Keen to make things easier/more obvious if I can. Cheers, Andrew ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 0/7] pinctrl: Fixes for AST2600 support 2019-10-16 11:41 ` Andrew Jeffery @ 2019-10-16 14:00 ` Linus Walleij 2019-10-16 23:26 ` Andrew Jeffery 0 siblings, 1 reply; 14+ messages in thread From: Linus Walleij @ 2019-10-16 14:00 UTC (permalink / raw) To: Andrew Jeffery Cc: open list:GPIO SUBSYSTEM, Rob Herring, Mark Rutland, Joel Stanley, linux-aspeed, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Linux ARM, linux-kernel, Johnny Huang, Ryan Chen On Wed, Oct 16, 2019 at 1:42 PM Andrew Jeffery <andrew@aj.id.au> wrote: > I was hoping to get them into the 5.4 fixes branch: I consider them all fixes OK I moved them all to fixes. > > I need a shortlist of anything that should go into v5.4 if anything. > > IMO all of them should go into 5.4, as above. OK > It's there something I can do in the future to communicate this better? Nah it is a complicated process, things need to be done manually at times, overly obsessing with process is counterproductive. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 0/7] pinctrl: Fixes for AST2600 support 2019-10-16 14:00 ` Linus Walleij @ 2019-10-16 23:26 ` Andrew Jeffery 0 siblings, 0 replies; 14+ messages in thread From: Andrew Jeffery @ 2019-10-16 23:26 UTC (permalink / raw) To: Linus Walleij Cc: open list:GPIO SUBSYSTEM, Rob Herring, Mark Rutland, Joel Stanley, linux-aspeed, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Linux ARM, linux-kernel, Johnny Huang, Ryan Chen On Thu, 17 Oct 2019, at 00:30, Linus Walleij wrote: > On Wed, Oct 16, 2019 at 1:42 PM Andrew Jeffery <andrew@aj.id.au> wrote: > > > I was hoping to get them into the 5.4 fixes branch: I consider them all fixes > > OK I moved them all to fixes. Thanks. > > > > I need a shortlist of anything that should go into v5.4 if anything. > > > > IMO all of them should go into 5.4, as above. > > OK > > > It's there something I can do in the future to communicate this better? > > Nah it is a complicated process, things need to be done manually > at times, overly obsessing with process is counterproductive. No worries, happy to carry on as is. Andrew ^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2019-10-16 23:25 UTC | newest] Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-10-08 4:41 [PATCH 0/7] pinctrl: Fixes for AST2600 support Andrew Jeffery 2019-10-08 4:41 ` [PATCH 1/7] dt-bindings: pinctrl: aspeed-g6: Rework SD3 function and groups Andrew Jeffery 2019-10-15 22:24 ` Rob Herring 2019-10-08 4:41 ` [PATCH 2/7] pinctrl: aspeed-g6: Sort pins for sanity Andrew Jeffery 2019-10-08 4:41 ` [PATCH 3/7] pinctrl: aspeed-g6: Fix I2C14 SDA description Andrew Jeffery 2019-10-08 4:41 ` [PATCH 4/7] pinctrl: aspeed-g6: Fix I3C3/I3C4 pinmux configuration Andrew Jeffery 2019-10-08 4:41 ` [PATCH 5/7] pinctrl: aspeed-g6: Make SIG_DESC_CLEAR() behave intuitively Andrew Jeffery 2019-10-08 4:41 ` [PATCH 6/7] pinctrl: aspeed-g6: Fix UART13 group pinmux Andrew Jeffery 2019-10-08 4:41 ` [PATCH 7/7] pinctrl: aspeed-g6: Rename SD3 to EMMC and rework pin groups Andrew Jeffery 2019-10-08 4:54 ` [PATCH 0/7] pinctrl: Fixes for AST2600 support Joel Stanley 2019-10-16 11:19 ` Linus Walleij 2019-10-16 11:41 ` Andrew Jeffery 2019-10-16 14:00 ` Linus Walleij 2019-10-16 23:26 ` Andrew Jeffery
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