[PATCH v3 00/11] Add the internal phy support

[PATCH v3 00/11] Add the internal phy support

[David Wu]

The rk3228 and rk3328 support internal phy inside, let's enable
it to work. And the internal phy need to do some special setting, so
register the rockchip internal phy driver.

David Wu (11):
  net: phy: Add rockchip phy driver support
  multi_v7_defconfig: Make rockchip phy built-in
  arm64: defconfig: Enable CONFIG_ROCKCHIP_PHY
  net: stmmac: dwmac-rk: Remove unwanted code for rk3328_set_to_rmii()
  net: stmmac: dwmac-rk: Add internal phy support
  net: stmmac: dwmac-rk: Add internal phy support for rk3228
  net: stmmac: dwmac-rk: Add internal phy supprot for rk3328
  ARM: dts: rk322x: Add support internal phy for gmac
  ARM: dts: rk3228-evb: Enable the internal phy for gmac
  ARM64: dts: rockchip: Add gmac2phy node support for rk3328
  ARM64: dts: rockchip: Enable gmac2phy for rk3328-evb

 .../devicetree/bindings/net/rockchip-dwmac.txt     |   6 +-
 arch/arm/boot/dts/rk3228-evb.dts                   |  20 ++
 arch/arm/boot/dts/rk322x.dtsi                      |   8 +-
 arch/arm/configs/multi_v7_defconfig                |   1 +
 arch/arm64/boot/dts/rockchip/rk3328-evb.dts        |  17 ++
 arch/arm64/boot/dts/rockchip/rk3328.dtsi           |  25 +++
 arch/arm64/configs/defconfig                       |   1 +
 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c     | 122 ++++++++++-
 drivers/net/phy/Kconfig                            |   5 +
 drivers/net/phy/Makefile                           |   1 +
 drivers/net/phy/rockchip.c                         | 229 +++++++++++++++++++++
 11 files changed, 424 insertions(+), 11 deletions(-)
 create mode 100644 drivers/net/phy/rockchip.c

-- 
1.9.1

[PATCH v3 01/11] net: phy: Add rockchip phy driver support

[David Wu]

Support internal ethernet phy currently.

Signed-off-by: David Wu <david.wu@rock-chips.com>
---
 drivers/net/phy/Kconfig    |   5 +
 drivers/net/phy/Makefile   |   1 +
 drivers/net/phy/rockchip.c | 229 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 235 insertions(+)
 create mode 100644 drivers/net/phy/rockchip.c

diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 2dda720..22cc702 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -334,6 +334,11 @@ config REALTEK_PHY
 	---help---
 	  Supports the Realtek 821x PHY.
 
+config ROCKCHIP_PHY
+        tristate "Driver for Rockchip Ethernet PHYs"
+        ---help---
+          Currently supports the internal Ethernet PHY.
+
 config SMSC_PHY
 	tristate "SMSC PHYs"
 	---help---
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 8e9b9f3..350520e 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -66,6 +66,7 @@ obj-$(CONFIG_MICROSEMI_PHY)	+= mscc.o
 obj-$(CONFIG_NATIONAL_PHY)	+= national.o
 obj-$(CONFIG_QSEMI_PHY)		+= qsemi.o
 obj-$(CONFIG_REALTEK_PHY)	+= realtek.o
+obj-$(CONFIG_ROCKCHIP_PHY)	+= rockchip.o
 obj-$(CONFIG_SMSC_PHY)		+= smsc.o
 obj-$(CONFIG_STE10XP)		+= ste10Xp.o
 obj-$(CONFIG_TERANETICS_PHY)	+= teranetics.o
diff --git a/drivers/net/phy/rockchip.c b/drivers/net/phy/rockchip.c
new file mode 100644
index 0000000..c1f07d6
--- /dev/null
+++ b/drivers/net/phy/rockchip.c
@@ -0,0 +1,229 @@
+/**
+ * drivers/net/phy/rockchip.c
+ *
+ * Driver for ROCKCHIP Ethernet PHYs
+ *
+ * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * David Wu <david.wu@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mii.h>
+#include <linux/ethtool.h>
+#include <linux/phy.h>
+#include <linux/netdevice.h>
+
+#define MII_INTERNAL_CTRL_STATUS	17
+#define SMI_ADDR_TSTCNTL		20
+#define SMI_ADDR_TSTREAD1		21
+#define SMI_ADDR_TSTREAD2		22
+#define SMI_ADDR_TSTWRITE		23
+#define MII_SPECIAL_CONTROL_STATUS	31
+
+#define MII_AUTO_MDIX_EN		BIT(7)
+#define MII_MDIX_EN			BIT(6)
+
+#define MII_SPEED_10			BIT(2)
+#define MII_SPEED_100			BIT(3)
+
+#define TSTCNTL_RD			(BIT(15) | BIT(10))
+#define TSTCNTL_WR			(BIT(14) | BIT(10))
+
+#define WR_ADDR_A7CFG			0x18
+
+static int rockchip_init_tstmode(struct phy_device *phydev)
+{
+	int ret;
+
+	/* Enable access to Analog and DSP register banks */
+	ret = phy_write(phydev, SMI_ADDR_TSTCNTL, 0x0400);
+	if (ret)
+		return ret;
+
+	ret = phy_write(phydev, SMI_ADDR_TSTCNTL, 0x0000);
+	if (ret)
+		return ret;
+
+	return phy_write(phydev, SMI_ADDR_TSTCNTL, 0x0400);
+}
+
+static int rockchip_close_tstmode(struct phy_device *phydev)
+{
+	/* Back to basic register bank */
+	return phy_write(phydev, SMI_ADDR_TSTCNTL, 0x0000);
+}
+
+static int rockchip_internal_phy_analog_init(struct phy_device *phydev)
+{
+	int ret;
+
+	ret = rockchip_init_tstmode(phydev);
+	if (ret)
+		return ret;
+
+	/*
+	 * Adjust tx amplitude to make sginal better,
+	 * the default value is 0x8.
+	 */
+	ret = phy_write(phydev, SMI_ADDR_TSTWRITE, 0xB);
+	if (ret)
+		return ret;
+	ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTCNTL_WR | WR_ADDR_A7CFG);
+	if (ret)
+		return ret;
+
+	return rockchip_close_tstmode(phydev);
+}
+
+static int rockchip_internal_phy_config_init(struct phy_device *phydev)
+{
+	int val, ret;
+
+	/*
+	 * The auto MIDX has linked problem on some board,
+	 * workround to disable auto MDIX.
+	 */
+	val = phy_read(phydev, MII_INTERNAL_CTRL_STATUS);
+	if (val < 0)
+		return val;
+	val &= ~MII_AUTO_MDIX_EN;
+	ret = phy_write(phydev, MII_INTERNAL_CTRL_STATUS, val);
+	if (ret)
+		return ret;
+
+	return rockchip_internal_phy_analog_init(phydev);
+}
+
+static void rockchip_link_change_notify(struct phy_device *phydev)
+{
+	int speed = SPEED_10;
+
+	if (phydev->autoneg == AUTONEG_ENABLE) {
+		int reg = phy_read(phydev, MII_SPECIAL_CONTROL_STATUS);
+
+		if (reg < 0) {
+			phydev_err(phydev, "phy_read err: %d.\n", reg);
+			return;
+		}
+
+		if (reg & MII_SPEED_100)
+			speed = SPEED_100;
+		else if (reg & MII_SPEED_10)
+			speed = SPEED_10;
+	} else {
+		int bmcr = phy_read(phydev, MII_BMCR);
+
+		if (bmcr < 0) {
+			phydev_err(phydev, "phy_read err: %d.\n", bmcr);
+			return;
+		}
+
+		if (bmcr & BMCR_SPEED100)
+			speed = SPEED_100;
+		else
+			speed = SPEED_10;
+	}
+
+	/*
+	 * If mode switch happens from 10BT to 100BT, all DSP/AFE
+	 * registers are set to default values. So any AFE/DSP
+	 * registers have to be re-initialized in this case.
+	 */
+	if ((phydev->speed == SPEED_10) && (speed == SPEED_100)) {
+		int ret = rockchip_internal_phy_analog_init(phydev);
+		if (ret)
+			phydev_err(phydev, "rockchip_internal_phy_analog_init err: %d.\n",
+				   ret);
+	}
+}
+
+static int rockchip_set_polarity(struct phy_device *phydev, int polarity)
+{
+	int reg, err, val;
+
+	/* get the current settings */
+	reg = phy_read(phydev, MII_INTERNAL_CTRL_STATUS);
+	if (reg < 0)
+		return reg;
+
+	reg &= ~MII_AUTO_MDIX_EN;
+	val = reg;
+	switch (polarity) {
+	case ETH_TP_MDI:
+		val &= ~MII_MDIX_EN;
+		break;
+	case ETH_TP_MDI_X:
+		val |= MII_MDIX_EN;
+		break;
+	case ETH_TP_MDI_AUTO:
+	case ETH_TP_MDI_INVALID:
+	default:
+		return 0;
+	}
+
+	if (val != reg) {
+		/* Set the new polarity value in the register */
+		err = phy_write(phydev, MII_INTERNAL_CTRL_STATUS, val);
+		if (err)
+			return err;
+	}
+
+	return 0;
+}
+
+static int rockchip_config_aneg(struct phy_device *phydev)
+{
+	int err;
+
+	err = rockchip_set_polarity(phydev, phydev->mdix);
+	if (err < 0)
+		return err;
+
+	return genphy_config_aneg(phydev);
+}
+
+static int rockchip_phy_resume(struct phy_device *phydev)
+{
+	genphy_resume(phydev);
+
+	return rockchip_internal_phy_config_init(phydev);
+}
+
+static struct phy_driver rockchip_phy_driver[] = {
+{
+	.phy_id			= 0x1234d400,
+	.phy_id_mask		= 0xfffffff0,
+	.name			= "Rockchip internal EPHY",
+	.features		= (PHY_BASIC_FEATURES | SUPPORTED_Pause
+				   | SUPPORTED_Asym_Pause),
+	.flags			= PHY_IS_INTERNAL,
+	.link_change_notify	= rockchip_link_change_notify,
+	.soft_reset		= genphy_soft_reset,
+	.config_init		= rockchip_internal_phy_config_init,
+	.config_aneg		= rockchip_config_aneg,
+	.read_status		= genphy_read_status,
+	.suspend		= genphy_suspend,
+	.resume			= rockchip_phy_resume,
+},
+};
+
+module_phy_driver(rockchip_phy_driver);
+
+static struct mdio_device_id __maybe_unused rockchip_phy_tbl[] = {
+	{ 0x1234d400, 0xfffffff0 },
+	{ }
+};
+
+MODULE_DEVICE_TABLE(mdio, rockchip_phy_tbl);
+
+MODULE_AUTHOR("David Wu <david.wu@rock-chips.com>");
+MODULE_DESCRIPTION("Rockchip Ethernet PHY driver");
+MODULE_LICENSE("GPL v2");
-- 
1.9.1

[PATCH v3 02/11] multi_v7_defconfig: Make rockchip phy built-in

[David Wu]

Enable the rockchip phy for multi_v7_defconfig builds.

Signed-off-by: David Wu <david.wu@rock-chips.com>
---
 arch/arm/configs/multi_v7_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 4d19c1b..94d7e71 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -270,6 +270,7 @@ CONFIG_ICPLUS_PHY=y
 CONFIG_REALTEK_PHY=y
 CONFIG_MICREL_PHY=y
 CONFIG_FIXED_PHY=y
+CONFIG_ROCKCHIP_PHY=y
 CONFIG_USB_PEGASUS=y
 CONFIG_USB_RTL8152=m
 CONFIG_USB_USBNET=y
-- 
1.9.1

[PATCH v3 03/11] arm64: defconfig: Enable CONFIG_ROCKCHIP_PHY

[David Wu]

Make the rockchip phy driver built into the kernel.

Signed-off-by: David Wu <david.wu@rock-chips.com>
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 6c7d147..925bd478 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -203,6 +203,7 @@ CONFIG_MARVELL_PHY=m
 CONFIG_MESON_GXL_PHY=m
 CONFIG_MICREL_PHY=y
 CONFIG_REALTEK_PHY=m
+CONFIG_ROCKCHIP_PHY=y
 CONFIG_USB_PEGASUS=m
 CONFIG_USB_RTL8150=m
 CONFIG_USB_RTL8152=m
-- 
1.9.1

[PATCH v3 04/11] net: stmmac: dwmac-rk: Remove unwanted code for rk3328_set_to_rmii()

[David Wu]

This is wrong setting for rk3328_set_to_rmii(), so remove it.

Signed-off-by: David Wu <david.wu@rock-chips.com>
---
 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index f0df519..a8e8fd5 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -365,9 +365,6 @@ static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
 	regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
 		     RK3328_GMAC_PHY_INTF_SEL_RMII |
 		     RK3328_GMAC_RMII_MODE);
-
-	/* set MAC to RMII mode */
-	regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, GRF_BIT(11));
 }
 
 static void rk3328_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
-- 
1.9.1

Re: [PATCH v3 01/11] net: phy: Add rockchip phy driver support

[Corentin Labbe]

Hello I have some minor comment below

> +
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/mii.h>
> +#include <linux/ethtool.h>
> +#include <linux/phy.h>
> +#include <linux/netdevice.h>

in alphabetic order please

[...]
> +static int rockchip_init_tstmode(struct phy_device *phydev)
> +{
> +	int ret;
> +
> +	/* Enable access to Analog and DSP register banks */
> +	ret = phy_write(phydev, SMI_ADDR_TSTCNTL, 0x0400);
> +	if (ret)
> +		return ret;
> +
> +	ret = phy_write(phydev, SMI_ADDR_TSTCNTL, 0x0000);
> +	if (ret)
> +		return ret;
> +
> +	return phy_write(phydev, SMI_ADDR_TSTCNTL, 0x0400);
> +}
> +
> +static int rockchip_close_tstmode(struct phy_device *phydev)
> +{
> +	/* Back to basic register bank */
> +	return phy_write(phydev, SMI_ADDR_TSTCNTL, 0x0000);

The reuse of 0x0000 and 0x0400 seems to promote a define use

[...]
> +static struct phy_driver rockchip_phy_driver[] = {
> +{
> +	.phy_id			= 0x1234d400,
> +	.phy_id_mask		= 0xfffffff0,
> +	.name			= "Rockchip internal EPHY",
> +	.features		= (PHY_BASIC_FEATURES | SUPPORTED_Pause
> +				   | SUPPORTED_Asym_Pause),
> +	.flags			= PHY_IS_INTERNAL,
> +	.link_change_notify	= rockchip_link_change_notify,
> +	.soft_reset		= genphy_soft_reset,
> +	.config_init		= rockchip_internal_phy_config_init,
> +	.config_aneg		= rockchip_config_aneg,
> +	.read_status		= genphy_read_status,
> +	.suspend		= genphy_suspend,
> +	.resume			= rockchip_phy_resume,
> +},
> +};
> +
> +module_phy_driver(rockchip_phy_driver);
> +
> +static struct mdio_device_id __maybe_unused rockchip_phy_tbl[] = {
> +	{ 0x1234d400, 0xfffffff0 },

Same comment for phy_id, use a define

Regards
Corentin Labbe

[PATCH v3 05/11] net: stmmac: dwmac-rk: Add internal phy support

[David Wu]

To make internal phy work, need to configure the phy_clock,
phy cru_reset and related registers.

Signed-off-by: David Wu <david.wu@rock-chips.com>
---
 .../devicetree/bindings/net/rockchip-dwmac.txt     |  6 +-
 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c     | 81 ++++++++++++++++++++++
 2 files changed, 86 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
index 8f42755..ec39b31 100644
--- a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
+++ b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
@@ -25,7 +25,8 @@ Required properties:
  - clock-names: One name for each entry in the clocks property.
  - phy-mode: See ethernet.txt file in the same directory.
  - pinctrl-names: Names corresponding to the numbered pinctrl states.
- - pinctrl-0: pin-control mode. can be <&rgmii_pins> or <&rmii_pins>.
+ - pinctrl-0: pin-control mode. can be <&rgmii_pins>, <&rmii_pins> or led pins
+   for internal phy mode.
  - clock_in_out: For RGMII, it must be "input", means main clock(125MHz)
    is not sourced from SoC's PLL, but input from PHY; For RMII, "input" means
    PHY provides the reference clock(50MHz), "output" means GMAC provides the
@@ -40,6 +41,9 @@ Optional properties:
  - tx_delay: Delay value for TXD timing. Range value is 0~0x7F, 0x30 as default.
  - rx_delay: Delay value for RXD timing. Range value is 0~0x7F, 0x10 as default.
  - phy-supply: phandle to a regulator if the PHY needs one
+ - clocks: <&cru MAC_PHY>: Clock selector for internal macphy
+ - phy-is-internal: A boolean property allows us to know that MAC will connect to
+   internal phy.
 
 Example:
 
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index a8e8fd5..7b80ab9 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -41,6 +41,7 @@ struct rk_gmac_ops {
 	void (*set_to_rmii)(struct rk_priv_data *bsp_priv);
 	void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed);
 	void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed);
+	void (*internal_phy_powerup)(struct rk_priv_data *bsp_priv);
 };
 
 struct rk_priv_data {
@@ -52,6 +53,7 @@ struct rk_priv_data {
 
 	bool clk_enabled;
 	bool clock_input;
+	bool internal_phy;
 
 	struct clk *clk_mac;
 	struct clk *gmac_clkin;
@@ -61,6 +63,9 @@ struct rk_priv_data {
 	struct clk *clk_mac_refout;
 	struct clk *aclk_mac;
 	struct clk *pclk_mac;
+	struct clk *clk_macphy;
+
+	struct reset_control *macphy_reset;
 
 	int tx_delay;
 	int rx_delay;
@@ -750,6 +755,50 @@ static void rk3399_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 	.set_rmii_speed = rk3399_set_rmii_speed,
 };
 
+#define RK_GRF_MACPHY_CON0		0xb00
+#define RK_GRF_MACPHY_CON1		0xb04
+#define RK_GRF_MACPHY_CON2		0xb08
+#define RK_GRF_MACPHY_CON3		0xb0c
+
+#define RK_MACPHY_ENABLE		GRF_BIT(0)
+#define RK_MACPHY_DISABLE		GRF_CLR_BIT(0)
+#define RK_MACPHY_CFG_CLK_50M		GRF_BIT(14)
+#define RK_GMAC2PHY_RMII_MODE		(GRF_BIT(6) | GRF_CLR_BIT(7))
+#define RK_GRF_CON2_MACPHY_ID		HIWORD_UPDATE(0x1234, 0xffff, 0)
+#define RK_GRF_CON3_MACPHY_ID		HIWORD_UPDATE(0x35, 0x3f, 0)
+
+static void rk_gmac_internal_phy_powerup(struct rk_priv_data *priv)
+{
+	if (priv->ops->internal_phy_powerup)
+		priv->ops->internal_phy_powerup(priv);
+
+	regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);
+	regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);
+
+	regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);
+	regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);
+
+	if (priv->macphy_reset) {
+		/* macphy needs to be disabled before trying to reset it */
+		regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
+		if (priv->macphy_reset)
+			reset_control_assert(priv->macphy_reset);
+		usleep_range(10, 20);
+		if (priv->macphy_reset)
+			reset_control_deassert(priv->macphy_reset);
+		usleep_range(10, 20);
+		regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);
+		msleep(30);
+	}
+}
+
+static void rk_gmac_internal_phy_powerdown(struct rk_priv_data *priv)
+{
+	regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
+	if (priv->macphy_reset)
+		reset_control_assert(priv->macphy_reset);
+}
+
 static int gmac_clk_init(struct rk_priv_data *bsp_priv)
 {
 	struct device *dev = &bsp_priv->pdev->dev;
@@ -803,6 +852,14 @@ static int gmac_clk_init(struct rk_priv_data *bsp_priv)
 			clk_set_rate(bsp_priv->clk_mac, 50000000);
 	}
 
+	if (bsp_priv->internal_phy) {
+		bsp_priv->clk_macphy = devm_clk_get(dev, "clk_macphy");
+		if (IS_ERR(bsp_priv->clk_macphy))
+			dev_err(dev, "cannot get %s clock\n", "clk_macphy");
+		else
+			clk_set_rate(bsp_priv->clk_macphy, 50000000);
+	}
+
 	return 0;
 }
 
@@ -826,6 +883,9 @@ static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)
 						bsp_priv->clk_mac_refout);
 			}
 
+			if (!IS_ERR(bsp_priv->clk_macphy))
+				clk_prepare_enable(bsp_priv->clk_macphy);
+
 			if (!IS_ERR(bsp_priv->aclk_mac))
 				clk_prepare_enable(bsp_priv->aclk_mac);
 
@@ -858,6 +918,9 @@ static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)
 						bsp_priv->clk_mac_refout);
 			}
 
+			if (!IS_ERR(bsp_priv->clk_macphy))
+				clk_disable_unprepare(bsp_priv->clk_macphy);
+
 			if (!IS_ERR(bsp_priv->aclk_mac))
 				clk_disable_unprepare(bsp_priv->aclk_mac);
 
@@ -940,6 +1003,18 @@ static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev,
 			bsp_priv->clock_input = false;
 	}
 
+	bsp_priv->internal_phy = device_property_read_bool(dev,
+							   "phy-is-internal");
+	if (bsp_priv->internal_phy) {
+		bsp_priv->macphy_reset = devm_reset_control_get(dev, "mac-phy");
+		if (IS_ERR(bsp_priv->macphy_reset)) {
+			dev_info(dev, "no macphy_reset control found\n");
+			bsp_priv->macphy_reset = NULL;
+		}
+	}
+	dev_info(dev, "internal PHY? (%s).\n",
+		 bsp_priv->internal_phy ? "yes" : "no");
+
 	ret = of_property_read_u32(dev->of_node, "tx_delay", &value);
 	if (ret) {
 		bsp_priv->tx_delay = 0x30;
@@ -1014,6 +1089,9 @@ static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
 	pm_runtime_enable(dev);
 	pm_runtime_get_sync(dev);
 
+	if (bsp_priv->internal_phy)
+		rk_gmac_internal_phy_powerup(bsp_priv);
+
 	return 0;
 }
 
@@ -1021,6 +1099,9 @@ static void rk_gmac_powerdown(struct rk_priv_data *gmac)
 {
 	struct device *dev = &gmac->pdev->dev;
 
+	if (gmac->internal_phy)
+		rk_gmac_internal_phy_powerdown(gmac);
+
 	pm_runtime_put_sync(dev);
 	pm_runtime_disable(dev);
 
-- 
1.9.1

[PATCH v3 06/11] net: stmmac: dwmac-rk: Add internal phy support for rk3228

[David Wu]

There is only one mac controller in rk3228, which could connect to
external phy or internal phy, use the grf_com_mux bit15 to route
external/internal phy.

Signed-off-by: David Wu <david.wu@rock-chips.com>
---
 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 7b80ab9..74cf0bb 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -86,6 +86,8 @@ struct rk_priv_data {
 #define RK3228_GRF_MAC_CON0	0x0900
 #define RK3228_GRF_MAC_CON1	0x0904
 
+#define RK3228_GRF_CON_MUX	0x50
+
 /* RK3228_GRF_MAC_CON0 */
 #define RK3228_GMAC_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 7)
 #define RK3228_GMAC_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 0)
@@ -111,6 +113,9 @@ struct rk_priv_data {
 #define RK3228_GMAC_RXCLK_DLY_ENABLE	GRF_BIT(1)
 #define RK3228_GMAC_RXCLK_DLY_DISABLE	GRF_CLR_BIT(1)
 
+/* RK3228_GRF_COM_MUX */
+#define RK3228_GRF_CON_MUX_GMAC_INTERNAL_PHY	GRF_BIT(15)
+
 static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv,
 				int tx_delay, int rx_delay)
 {
@@ -191,11 +196,18 @@ static void rk3228_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 		dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 }
 
+static void rk3228_internal_phy_powerup(struct rk_priv_data *priv)
+{
+	regmap_write(priv->grf, RK3228_GRF_CON_MUX,
+		     RK3228_GRF_CON_MUX_GMAC_INTERNAL_PHY);
+}
+
 static const struct rk_gmac_ops rk3228_ops = {
 	.set_to_rgmii = rk3228_set_to_rgmii,
 	.set_to_rmii = rk3228_set_to_rmii,
 	.set_rgmii_speed = rk3228_set_rgmii_speed,
 	.set_rmii_speed = rk3228_set_rmii_speed,
+	.internal_phy_powerup =  rk3228_internal_phy_powerup,
 };
 
 #define RK3288_GRF_SOC_CON1	0x0248
-- 
1.9.1

[PATCH v3 07/11] net: stmmac: dwmac-rk: Add internal phy supprot for rk3328

[David Wu]

There are two mac controllers in the rk3328, the one connects
to external phy, and the other one connects to internal phy.
Like the mac of external phy, the internal phy's mac also needs to
configure the related mac registers at GRF.

Signed-off-by: David Wu <david.wu@rock-chips.com>
---
 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 26 +++++++++++++++++++++++---
 1 file changed, 23 insertions(+), 3 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 74cf0bb..83471f3 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -323,6 +323,8 @@ static void rk3288_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 
 #define RK3328_GRF_MAC_CON0	0x0900
 #define RK3328_GRF_MAC_CON1	0x0904
+#define RK3328_GRF_MAC_CON2	0x0908
+#define RK3328_GRF_MACPHY_CON1	0xb04
 
 /* RK3328_GRF_MAC_CON0 */
 #define RK3328_GMAC_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 7)
@@ -349,6 +351,9 @@ static void rk3288_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 #define RK3328_GMAC_RXCLK_DLY_ENABLE	GRF_BIT(1)
 #define RK3328_GMAC_RXCLK_DLY_DISABLE	GRF_CLR_BIT(0)
 
+/* RK3328_GRF_MACPHY_CON1 */
+#define RK3328_MACPHY_RMII_MODE		GRF_BIT(9)
+
 static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv,
 				int tx_delay, int rx_delay)
 {
@@ -373,13 +378,17 @@ static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv,
 static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
 {
 	struct device *dev = &bsp_priv->pdev->dev;
+	unsigned int reg;
 
 	if (IS_ERR(bsp_priv->grf)) {
 		dev_err(dev, "Missing rockchip,grf property\n");
 		return;
 	}
 
-	regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
+	reg = bsp_priv->internal_phy ? RK3328_GRF_MAC_CON2 :
+		  RK3328_GRF_MAC_CON1;
+
+	regmap_write(bsp_priv->grf, reg,
 		     RK3328_GMAC_PHY_INTF_SEL_RMII |
 		     RK3328_GMAC_RMII_MODE);
 }
@@ -409,29 +418,40 @@ static void rk3328_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 static void rk3328_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 {
 	struct device *dev = &bsp_priv->pdev->dev;
+	unsigned int reg;
 
 	if (IS_ERR(bsp_priv->grf)) {
 		dev_err(dev, "Missing rockchip,grf property\n");
 		return;
 	}
 
+	reg = bsp_priv->internal_phy ? RK3328_GRF_MAC_CON2 :
+		  RK3328_GRF_MAC_CON1;
+
 	if (speed == 10)
-		regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
+		regmap_write(bsp_priv->grf, reg,
 			     RK3328_GMAC_RMII_CLK_2_5M |
 			     RK3328_GMAC_SPEED_10M);
 	else if (speed == 100)
-		regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
+		regmap_write(bsp_priv->grf, reg,
 			     RK3328_GMAC_RMII_CLK_25M |
 			     RK3328_GMAC_SPEED_100M);
 	else
 		dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 }
 
+static void rk3328_internal_phy_powerup(struct rk_priv_data *priv)
+{
+	regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1,
+		     RK3328_MACPHY_RMII_MODE);
+}
+
 static const struct rk_gmac_ops rk3328_ops = {
 	.set_to_rgmii = rk3328_set_to_rgmii,
 	.set_to_rmii = rk3328_set_to_rmii,
 	.set_rgmii_speed = rk3328_set_rgmii_speed,
 	.set_rmii_speed = rk3328_set_rmii_speed,
+	.internal_phy_powerup =  rk3328_internal_phy_powerup,
 };
 
 #define RK3366_GRF_SOC_CON6	0x0418
-- 
1.9.1

[PATCH v3 08/11] ARM: dts: rk322x: Add support internal phy for gmac

[David Wu]

This patch adds internal mac phy clock and internal mac phy reset
for rk gmac using.

Signed-off-by: David Wu <david.wu@rock-chips.com>
---
 arch/arm/boot/dts/rk322x.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index f3e4ffd..3778f7d 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -611,13 +611,13 @@
 		clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 			<&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
 			<&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
-			<&cru PCLK_GMAC>;
+			<&cru PCLK_GMAC>, <&cru SCLK_MAC_PHY>;
 		clock-names = "stmmaceth", "mac_clk_rx",
 			"mac_clk_tx", "clk_mac_ref",
 			"clk_mac_refout", "aclk_mac",
-			"pclk_mac";
-		resets = <&cru SRST_GMAC>;
-		reset-names = "stmmaceth";
+			"pclk_mac", "clk_macphy";
+		resets = <&cru SRST_GMAC>, <&cru SRST_MACPHY>;
+		reset-names = "stmmaceth", "mac-phy";
 		rockchip,grf = <&grf>;
 		status = "disabled";
 	};
-- 
1.9.1

[PATCH v3 09/11] ARM: dts: rk3228-evb: Enable the internal phy for gmac

[David Wu]

This patch enables the internal phy for rk3228 evb board
by default.
To use the external 1000M phy on evb board, need to make
some switch of evb board to be on.

Signed-off-by: David Wu <david.wu@rock-chips.com>
---
 arch/arm/boot/dts/rk3228-evb.dts | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm/boot/dts/rk3228-evb.dts b/arch/arm/boot/dts/rk3228-evb.dts
index 5883433..48b3adb 100644
--- a/arch/arm/boot/dts/rk3228-evb.dts
+++ b/arch/arm/boot/dts/rk3228-evb.dts
@@ -50,6 +50,16 @@
 		device_type = "memory";
 		reg = <0x60000000 0x40000000>;
 	};
+
+	vcc_phy: vcc-phy-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		regulator-name = "vcc_phy";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
 };
 
 &emmc {
@@ -60,6 +70,16 @@
 	status = "okay";
 };
 
+&gmac {
+	assigned-clocks = <&cru SCLK_MAC_SRC>;
+	assigned-clock-rates = <50000000>;
+	clock_in_out = "output";
+	phy-supply = <&vcc_phy>;
+	phy-mode = "rmii";
+	phy-is-internal;
+	status = "okay";
+};
+
 &tsadc {
 	status = "okay";
 
-- 
1.9.1

[PATCH v3 10/11] ARM64: dts: rockchip: Add gmac2phy node support for rk3328

[David Wu]

The gmac2phy controller of rk3328 is connected to internal phy
directly inside, add the node for the internal phy support.

Signed-off-by: David Wu <david.wu@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/rk3328.dtsi | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 0be96ce..51c8c66 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -63,6 +63,8 @@
 		i2c1 = &i2c1;
 		i2c2 = &i2c2;
 		i2c3 = &i2c3;
+		ethernet0 = &gmac2io;
+		ethernet1 = &gmac2phy;
 	};
 
 	cpus {
@@ -424,6 +426,29 @@
 		status = "disabled";
 	};
 
+	gmac2phy: eth@ff550000 {
+		compatible = "rockchip,rk3328-gmac";
+		reg = <0x0 0xff550000 0x0 0x10000>;
+		rockchip,grf = <&grf>;
+		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "macirq";
+		clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,
+			 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,
+			 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,
+			 <&cru SCLK_MAC2PHY_OUT>;
+		clock-names = "stmmaceth", "mac_clk_rx",
+			      "mac_clk_tx", "clk_mac_ref",
+			      "aclk_mac", "pclk_mac",
+			      "clk_macphy";
+		resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>;
+		reset-names = "stmmaceth", "mac-phy";
+		phy-mode = "rmii";
+		phy-is-internal;
+		pinctrl-names = "default";
+		pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
+		status = "disabled";
+	};
+
 	gic: interrupt-controller@ff811000 {
 		compatible = "arm,gic-400";
 		#interrupt-cells = <3>;
-- 
1.9.1

[PATCH v3 11/11] ARM64: dts: rockchip: Enable gmac2phy for rk3328-evb

[David Wu]

Enable the gmac2phy, make the gmac2phy work on
the rk3328-evb board.

Signed-off-by: David Wu <david.wu@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/rk3328-evb.dts | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3328-evb.dts b/arch/arm64/boot/dts/rockchip/rk3328-evb.dts
index cf27239..b9f36da 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-evb.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-evb.dts
@@ -50,6 +50,23 @@
 	chosen {
 		stdout-path = "serial2:1500000n8";
 	};
+
+	vcc_phy: vcc-phy-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_phy";
+		regulator-always-on;
+		regulator-boot-on;
+	};
+};
+
+&gmac2phy {
+	phy-supply = <&vcc_phy>;
+	clock_in_out = "output";
+	assigned-clocks = <&cru SCLK_MAC2PHY_SRC>;
+	assigned-clock-rate = <50000000>;
+	assigned-clocks = <&cru SCLK_MAC2PHY>;
+	assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
+	status = "okay";
 };
 
 &uart2 {
-- 
1.9.1

Re: [PATCH v3 10/11] ARM64: dts: rockchip: Add gmac2phy node support for rk3328

[Sergei Shtylyov]

Hello!

On 08/02/2017 09:24 AM, David Wu wrote:

> The gmac2phy controller of rk3328 is connected to internal phy
> directly inside, add the node for the internal phy support.
> 
> Signed-off-by: David Wu <david.wu@rock-chips.com>
> ---
>   arch/arm64/boot/dts/rockchip/rk3328.dtsi | 25 +++++++++++++++++++++++++
>   1 file changed, 25 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
> index 0be96ce..51c8c66 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
[...]
> @@ -424,6 +426,29 @@
>   		status = "disabled";
>   	};
>   
> +	gmac2phy: eth@ff550000 {

    The standardized name is ethernet@...

[...]

MBR, Sergei

Re: [PATCH v3 01/11] net: phy: Add rockchip phy driver support

[Andrew Lunn]

> +static struct phy_driver rockchip_phy_driver[] = {
> +{
> +	.phy_id			= 0x1234d400,
> +	.phy_id_mask		= 0xfffffff0,
> +	.name			= "Rockchip internal EPHY",
> +	.features		= (PHY_BASIC_FEATURES | SUPPORTED_Pause
> +				   | SUPPORTED_Asym_Pause),

Please take a look at Documentation/networking/phy.txt and
Fixes: 529ed1275263 ("net: phy: phy drivers should not set SUPPORTED_[Asym_]Pause")

Pause frames / flow control

 The PHY does not participate directly in flow control/pause frames except by
 making sure that the SUPPORTED_Pause and SUPPORTED_AsymPause bits are set in
 MII_ADVERTISE to indicate towards the link partner that the Ethernet MAC
 controller supports such a thing. Since flow control/pause frames generation
 involves the Ethernet MAC driver, it is recommended that this driver takes care
 of properly indicating advertisement and support for such features by setting
 the SUPPORTED_Pause and SUPPORTED_AsymPause bits accordingly. This can be done
 either before or after phy_connect() and/or as a result of implementing the
 ethtool::set_pauseparam feature.

	Andrew

Re: [PATCH v3 05/11] net: stmmac: dwmac-rk: Add internal phy support

[Florian Fainelli]

On 08/01/2017 11:21 PM, David Wu wrote:
> To make internal phy work, need to configure the phy_clock,
> phy cru_reset and related registers.
> 
> Signed-off-by: David Wu <david.wu@rock-chips.com>
> ---
>  .../devicetree/bindings/net/rockchip-dwmac.txt     |  6 +-
>  drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c     | 81 ++++++++++++++++++++++
>  2 files changed, 86 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
> index 8f42755..ec39b31 100644
> --- a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
> +++ b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
> @@ -25,7 +25,8 @@ Required properties:
>   - clock-names: One name for each entry in the clocks property.
>   - phy-mode: See ethernet.txt file in the same directory.
>   - pinctrl-names: Names corresponding to the numbered pinctrl states.
> - - pinctrl-0: pin-control mode. can be <&rgmii_pins> or <&rmii_pins>.
> + - pinctrl-0: pin-control mode. can be <&rgmii_pins>, <&rmii_pins> or led pins
> +   for internal phy mode.
>   - clock_in_out: For RGMII, it must be "input", means main clock(125MHz)
>     is not sourced from SoC's PLL, but input from PHY; For RMII, "input" means
>     PHY provides the reference clock(50MHz), "output" means GMAC provides the
> @@ -40,6 +41,9 @@ Optional properties:
>   - tx_delay: Delay value for TXD timing. Range value is 0~0x7F, 0x30 as default.
>   - rx_delay: Delay value for RXD timing. Range value is 0~0x7F, 0x10 as default.
>   - phy-supply: phandle to a regulator if the PHY needs one
> + - clocks: <&cru MAC_PHY>: Clock selector for internal macphy
> + - phy-is-internal: A boolean property allows us to know that MAC will connect to
> +   internal phy.

This is incorrect in two ways:

- this is a property of the PHY, so it should be documented as such in
Documentation/devicetree/bindings/net/phy.txt so other bindings can
re-use it

- if it was specific to your MAC you would expect a vendor prefix to
this property, which is not there

An alternative way to implement the external/internal logic selection
would be mandate that your Ethernet PHY node have a compatible string
like this:

phy@0 {
	compatible = "ethernet-phy-id1234.d400", "ethernet-phy-802.3-c22";
};

Then you don't need this phy-is-internal property, because you can
locate the PHY node by the phy-handle (see more about that in a reply to
patch 10) and you can determine ahead of time whether this PHY is
internal or not based on its compatible string.

Thank you

>  
>  Example:
>  
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
> index a8e8fd5..7b80ab9 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
> @@ -41,6 +41,7 @@ struct rk_gmac_ops {
>  	void (*set_to_rmii)(struct rk_priv_data *bsp_priv);
>  	void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed);
>  	void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed);
> +	void (*internal_phy_powerup)(struct rk_priv_data *bsp_priv);
>  };
>  
>  struct rk_priv_data {
> @@ -52,6 +53,7 @@ struct rk_priv_data {
>  
>  	bool clk_enabled;
>  	bool clock_input;
> +	bool internal_phy;
>  
>  	struct clk *clk_mac;
>  	struct clk *gmac_clkin;
> @@ -61,6 +63,9 @@ struct rk_priv_data {
>  	struct clk *clk_mac_refout;
>  	struct clk *aclk_mac;
>  	struct clk *pclk_mac;
> +	struct clk *clk_macphy;
> +
> +	struct reset_control *macphy_reset;
>  
>  	int tx_delay;
>  	int rx_delay;
> @@ -750,6 +755,50 @@ static void rk3399_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
>  	.set_rmii_speed = rk3399_set_rmii_speed,
>  };
>  
> +#define RK_GRF_MACPHY_CON0		0xb00
> +#define RK_GRF_MACPHY_CON1		0xb04
> +#define RK_GRF_MACPHY_CON2		0xb08
> +#define RK_GRF_MACPHY_CON3		0xb0c
> +
> +#define RK_MACPHY_ENABLE		GRF_BIT(0)
> +#define RK_MACPHY_DISABLE		GRF_CLR_BIT(0)
> +#define RK_MACPHY_CFG_CLK_50M		GRF_BIT(14)
> +#define RK_GMAC2PHY_RMII_MODE		(GRF_BIT(6) | GRF_CLR_BIT(7))
> +#define RK_GRF_CON2_MACPHY_ID		HIWORD_UPDATE(0x1234, 0xffff, 0)
> +#define RK_GRF_CON3_MACPHY_ID		HIWORD_UPDATE(0x35, 0x3f, 0)
> +
> +static void rk_gmac_internal_phy_powerup(struct rk_priv_data *priv)
> +{
> +	if (priv->ops->internal_phy_powerup)
> +		priv->ops->internal_phy_powerup(priv);
> +
> +	regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);
> +	regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);
> +
> +	regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);
> +	regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);
> +
> +	if (priv->macphy_reset) {
> +		/* macphy needs to be disabled before trying to reset it */
> +		regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
> +		if (priv->macphy_reset)
> +			reset_control_assert(priv->macphy_reset);
> +		usleep_range(10, 20);
> +		if (priv->macphy_reset)
> +			reset_control_deassert(priv->macphy_reset);
> +		usleep_range(10, 20);
> +		regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);
> +		msleep(30);
> +	}
> +}
> +
> +static void rk_gmac_internal_phy_powerdown(struct rk_priv_data *priv)
> +{
> +	regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
> +	if (priv->macphy_reset)
> +		reset_control_assert(priv->macphy_reset);
> +}
> +
>  static int gmac_clk_init(struct rk_priv_data *bsp_priv)
>  {
>  	struct device *dev = &bsp_priv->pdev->dev;
> @@ -803,6 +852,14 @@ static int gmac_clk_init(struct rk_priv_data *bsp_priv)
>  			clk_set_rate(bsp_priv->clk_mac, 50000000);
>  	}
>  
> +	if (bsp_priv->internal_phy) {
> +		bsp_priv->clk_macphy = devm_clk_get(dev, "clk_macphy");
> +		if (IS_ERR(bsp_priv->clk_macphy))
> +			dev_err(dev, "cannot get %s clock\n", "clk_macphy");
> +		else
> +			clk_set_rate(bsp_priv->clk_macphy, 50000000);
> +	}
> +
>  	return 0;
>  }
>  
> @@ -826,6 +883,9 @@ static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)
>  						bsp_priv->clk_mac_refout);
>  			}
>  
> +			if (!IS_ERR(bsp_priv->clk_macphy))
> +				clk_prepare_enable(bsp_priv->clk_macphy);
> +
>  			if (!IS_ERR(bsp_priv->aclk_mac))
>  				clk_prepare_enable(bsp_priv->aclk_mac);
>  
> @@ -858,6 +918,9 @@ static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)
>  						bsp_priv->clk_mac_refout);
>  			}
>  
> +			if (!IS_ERR(bsp_priv->clk_macphy))
> +				clk_disable_unprepare(bsp_priv->clk_macphy);
> +
>  			if (!IS_ERR(bsp_priv->aclk_mac))
>  				clk_disable_unprepare(bsp_priv->aclk_mac);
>  
> @@ -940,6 +1003,18 @@ static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev,
>  			bsp_priv->clock_input = false;
>  	}
>  
> +	bsp_priv->internal_phy = device_property_read_bool(dev,
> +							   "phy-is-internal");
> +	if (bsp_priv->internal_phy) {
> +		bsp_priv->macphy_reset = devm_reset_control_get(dev, "mac-phy");
> +		if (IS_ERR(bsp_priv->macphy_reset)) {
> +			dev_info(dev, "no macphy_reset control found\n");
> +			bsp_priv->macphy_reset = NULL;
> +		}
> +	}
> +	dev_info(dev, "internal PHY? (%s).\n",
> +		 bsp_priv->internal_phy ? "yes" : "no");
> +
>  	ret = of_property_read_u32(dev->of_node, "tx_delay", &value);
>  	if (ret) {
>  		bsp_priv->tx_delay = 0x30;
> @@ -1014,6 +1089,9 @@ static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
>  	pm_runtime_enable(dev);
>  	pm_runtime_get_sync(dev);
>  
> +	if (bsp_priv->internal_phy)
> +		rk_gmac_internal_phy_powerup(bsp_priv);
> +
>  	return 0;
>  }
>  
> @@ -1021,6 +1099,9 @@ static void rk_gmac_powerdown(struct rk_priv_data *gmac)
>  {
>  	struct device *dev = &gmac->pdev->dev;
>  
> +	if (gmac->internal_phy)
> +		rk_gmac_internal_phy_powerdown(gmac);
> +
>  	pm_runtime_put_sync(dev);
>  	pm_runtime_disable(dev);
>  
> 


-- 
Florian

Re: [PATCH v3 10/11] ARM64: dts: rockchip: Add gmac2phy node support for rk3328

[Florian Fainelli]

On 08/01/2017 11:24 PM, David Wu wrote:
> The gmac2phy controller of rk3328 is connected to internal phy
> directly inside, add the node for the internal phy support.
> 
> Signed-off-by: David Wu <david.wu@rock-chips.com>
> ---
>  arch/arm64/boot/dts/rockchip/rk3328.dtsi | 25 +++++++++++++++++++++++++
>  1 file changed, 25 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
> index 0be96ce..51c8c66 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
> @@ -63,6 +63,8 @@
>  		i2c1 = &i2c1;
>  		i2c2 = &i2c2;
>  		i2c3 = &i2c3;
> +		ethernet0 = &gmac2io;
> +		ethernet1 = &gmac2phy;
>  	};
>  
>  	cpus {
> @@ -424,6 +426,29 @@
>  		status = "disabled";
>  	};
>  
> +	gmac2phy: eth@ff550000 {
> +		compatible = "rockchip,rk3328-gmac";
> +		reg = <0x0 0xff550000 0x0 0x10000>;
> +		rockchip,grf = <&grf>;
> +		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-names = "macirq";
> +		clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,
> +			 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,
> +			 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,
> +			 <&cru SCLK_MAC2PHY_OUT>;
> +		clock-names = "stmmaceth", "mac_clk_rx",
> +			      "mac_clk_tx", "clk_mac_ref",
> +			      "aclk_mac", "pclk_mac",
> +			      "clk_macphy";
> +		resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>;
> +		reset-names = "stmmaceth", "mac-phy";
> +		phy-mode = "rmii";
> +		phy-is-internal;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
> +		status = "disabled";

But where is the the phy-handle property that points to this internal
PHY? Even if it is internal, it should be described properly with a mdio
bus sub-node and a standard Ethernet PHY node as specified by both
Documentation/devicetree/bindings/net/mdio.txt and
Documentation/devicetree/bindings/net/phy.txt

That means we should at least see something like this (on top of what
you added already)
		phy-handle = <&phy0>;

		mdio {
			compatible = "snps,dwmac-mdio";
			#address-cells = <1>;
			#size-cells = <0>;

			phy@0 {
				compatible = "ethernet-phy-id1234.d400", "ethernet-phy-802.3-c22";
				reg = <0>;
				phy-is-internal;
			};
		};

> +	};
> +
>  	gic: interrupt-controller@ff811000 {
>  		compatible = "arm,gic-400";
>  		#interrupt-cells = <3>;
> 


-- 
Florian

Re: [PATCH v3 05/11] net: stmmac: dwmac-rk: Add internal phy support

[Chen-Yu Tsai]

On Thu, Aug 3, 2017 at 1:38 AM, Florian Fainelli <f.fainelli@gmail.com> wrote:
> On 08/01/2017 11:21 PM, David Wu wrote:
>> To make internal phy work, need to configure the phy_clock,
>> phy cru_reset and related registers.
>>
>> Signed-off-by: David Wu <david.wu@rock-chips.com>
>> ---
>>  .../devicetree/bindings/net/rockchip-dwmac.txt     |  6 +-
>>  drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c     | 81 ++++++++++++++++++++++
>>  2 files changed, 86 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
>> index 8f42755..ec39b31 100644
>> --- a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
>> +++ b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
>> @@ -25,7 +25,8 @@ Required properties:
>>   - clock-names: One name for each entry in the clocks property.
>>   - phy-mode: See ethernet.txt file in the same directory.
>>   - pinctrl-names: Names corresponding to the numbered pinctrl states.
>> - - pinctrl-0: pin-control mode. can be <&rgmii_pins> or <&rmii_pins>.
>> + - pinctrl-0: pin-control mode. can be <&rgmii_pins>, <&rmii_pins> or led pins
>> +   for internal phy mode.
>>   - clock_in_out: For RGMII, it must be "input", means main clock(125MHz)
>>     is not sourced from SoC's PLL, but input from PHY; For RMII, "input" means
>>     PHY provides the reference clock(50MHz), "output" means GMAC provides the
>> @@ -40,6 +41,9 @@ Optional properties:
>>   - tx_delay: Delay value for TXD timing. Range value is 0~0x7F, 0x30 as default.
>>   - rx_delay: Delay value for RXD timing. Range value is 0~0x7F, 0x10 as default.
>>   - phy-supply: phandle to a regulator if the PHY needs one
>> + - clocks: <&cru MAC_PHY>: Clock selector for internal macphy
>> + - phy-is-internal: A boolean property allows us to know that MAC will connect to
>> +   internal phy.
>
> This is incorrect in two ways:
>
> - this is a property of the PHY, so it should be documented as such in
> Documentation/devicetree/bindings/net/phy.txt so other bindings can
> re-use it
>
> - if it was specific to your MAC you would expect a vendor prefix to
> this property, which is not there
>
> An alternative way to implement the external/internal logic selection
> would be mandate that your Ethernet PHY node have a compatible string
> like this:
>
> phy@0 {
>         compatible = "ethernet-phy-id1234.d400", "ethernet-phy-802.3-c22";
> };
>
> Then you don't need this phy-is-internal property, because you can
> locate the PHY node by the phy-handle (see more about that in a reply to
> patch 10) and you can determine ahead of time whether this PHY is
> internal or not based on its compatible string.

This doesn't really work for us (sunxi). The "internal" PHY of the H3
is also available in the X-Powers AC200 combo chip, which would be
external. Same ID. So if someone were to be stupid and put the two
together, you wouldn't know which one it actually is. Generically
it doesn't make sense to match against the ID either. The PHY is
only integrated or inlined into the SoC, meaning it could be moved
elsewhere or even be a discreet part.

The way I see it is more like a reversed pinmux. The system should
select either the internal set or external set of xMII pins to use.

A phy-is-internal property in the PHY node would work for us. We
already need a PHY node to describe its clocks and resets.

A side note to this solution is that, since the internal PHY is defined
at the .dtsi level, any external PHYs at the same address would need to
make sure to delete the property, which is kind of counterintuitive, but
it is how device tree works. One would want to put the internal PHY's
address, assuming it is configurable, on something that is rarely used.


Regards
ChenYu

Re: [PATCH v3 05/11] net: stmmac: dwmac-rk: Add internal phy support

[David.Wu]

Hi Florian & ChenYu

在 2017/8/3 1:38, Florian Fainelli 写道:
> This is incorrect in two ways:
> 
> - this is a property of the PHY, so it should be documented as such in
> Documentation/devicetree/bindings/net/phy.txt so other bindings can
> re-use it
> 
> - if it was specific to your MAC you would expect a vendor prefix to
> this property, which is not there
> 
> An alternative way to implement the external/internal logic selection
> would be mandate that your Ethernet PHY node have a compatible string
> like this:
> 
> phy@0 {
> 	compatible = "ethernet-phy-id1234.d400", "ethernet-phy-802.3-c22";
> };
> 
> Then you don't need this phy-is-internal property, because you can
> locate the PHY node by the phy-handle (see more about that in a reply to
> patch 10) and you can determine ahead of time whether this PHY is
> internal or not based on its compatible string.

We may implement a read_bool_property after parsed phy phandle at 
stmmac_platform.c, which would make MAC driver know it is a internal phy.

Re: [PATCH v3 01/11] net: phy: Add rockchip phy driver support

[David.Wu]

Hi Andrew,

在 2017/8/2 21:21, Andrew Lunn 写道:
>> +static struct phy_driver rockchip_phy_driver[] = {
>> +{
>> +	.phy_id			= 0x1234d400,
>> +	.phy_id_mask		= 0xfffffff0,
>> +	.name			= "Rockchip internal EPHY",
>> +	.features		= (PHY_BASIC_FEATURES | SUPPORTED_Pause
>> +				   | SUPPORTED_Asym_Pause),
> 
> Please take a look at Documentation/networking/phy.txt and
> Fixes: 529ed1275263 ("net: phy: phy drivers should not set SUPPORTED_[Asym_]Pause")
> 
> Pause frames / flow control
> 
>   The PHY does not participate directly in flow control/pause frames except by
>   making sure that the SUPPORTED_Pause and SUPPORTED_AsymPause bits are set in
>   MII_ADVERTISE to indicate towards the link partner that the Ethernet MAC
>   controller supports such a thing. Since flow control/pause frames generation
>   involves the Ethernet MAC driver, it is recommended that this driver takes care
>   of properly indicating advertisement and support for such features by setting
>   the SUPPORTED_Pause and SUPPORTED_AsymPause bits accordingly. This can be done
>   either before or after phy_connect() and/or as a result of implementing the
>   ethtool::set_pauseparam feature.
> 

Thanks for the reminder, I'll remove it.

> 	Andrew
> 
> 
> 

Re: [PATCH v3 05/11] net: stmmac: dwmac-rk: Add internal phy support

[Corentin Labbe]

On Thu, Aug 03, 2017 at 07:06:33PM +0800, Chen-Yu Tsai wrote:
> On Thu, Aug 3, 2017 at 1:38 AM, Florian Fainelli <f.fainelli@gmail.com> wrote:
> > On 08/01/2017 11:21 PM, David Wu wrote:
> >> To make internal phy work, need to configure the phy_clock,
> >> phy cru_reset and related registers.
> >>
> >> Signed-off-by: David Wu <david.wu@rock-chips.com>
> >> ---
> >>  .../devicetree/bindings/net/rockchip-dwmac.txt     |  6 +-
> >>  drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c     | 81 ++++++++++++++++++++++
> >>  2 files changed, 86 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
> >> index 8f42755..ec39b31 100644
> >> --- a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
> >> +++ b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
> >> @@ -25,7 +25,8 @@ Required properties:
> >>   - clock-names: One name for each entry in the clocks property.
> >>   - phy-mode: See ethernet.txt file in the same directory.
> >>   - pinctrl-names: Names corresponding to the numbered pinctrl states.
> >> - - pinctrl-0: pin-control mode. can be <&rgmii_pins> or <&rmii_pins>.
> >> + - pinctrl-0: pin-control mode. can be <&rgmii_pins>, <&rmii_pins> or led pins
> >> +   for internal phy mode.
> >>   - clock_in_out: For RGMII, it must be "input", means main clock(125MHz)
> >>     is not sourced from SoC's PLL, but input from PHY; For RMII, "input" means
> >>     PHY provides the reference clock(50MHz), "output" means GMAC provides the
> >> @@ -40,6 +41,9 @@ Optional properties:
> >>   - tx_delay: Delay value for TXD timing. Range value is 0~0x7F, 0x30 as default.
> >>   - rx_delay: Delay value for RXD timing. Range value is 0~0x7F, 0x10 as default.
> >>   - phy-supply: phandle to a regulator if the PHY needs one
> >> + - clocks: <&cru MAC_PHY>: Clock selector for internal macphy
> >> + - phy-is-internal: A boolean property allows us to know that MAC will connect to
> >> +   internal phy.
> >
> > This is incorrect in two ways:
> >
> > - this is a property of the PHY, so it should be documented as such in
> > Documentation/devicetree/bindings/net/phy.txt so other bindings can
> > re-use it
> >
> > - if it was specific to your MAC you would expect a vendor prefix to
> > this property, which is not there
> >
> > An alternative way to implement the external/internal logic selection
> > would be mandate that your Ethernet PHY node have a compatible string
> > like this:
> >
> > phy@0 {
> >         compatible = "ethernet-phy-id1234.d400", "ethernet-phy-802.3-c22";
> > };
> >
> > Then you don't need this phy-is-internal property, because you can
> > locate the PHY node by the phy-handle (see more about that in a reply to
> > patch 10) and you can determine ahead of time whether this PHY is
> > internal or not based on its compatible string.
> 
> This doesn't really work for us (sunxi). The "internal" PHY of the H3
> is also available in the X-Powers AC200 combo chip, which would be
> external. Same ID. So if someone were to be stupid and put the two
> together, you wouldn't know which one it actually is. Generically
> it doesn't make sense to match against the ID either. The PHY is
> only integrated or inlined into the SoC, meaning it could be moved
> elsewhere or even be a discreet part.
> 
> The way I see it is more like a reversed pinmux. The system should
> select either the internal set or external set of xMII pins to use.
> 
> A phy-is-internal property in the PHY node would work for us. We
> already need a PHY node to describe its clocks and resets.
> 
> A side note to this solution is that, since the internal PHY is defined
> at the .dtsi level, any external PHYs at the same address would need to
> make sure to delete the property, which is kind of counterintuitive, but
> it is how device tree works. One would want to put the internal PHY's
> address, assuming it is configurable, on something that is rarely used.
> 

Hello David, Florian, Andrew

Could someone ack this ? or nack if you think that the chance for having two PHY id both internal and external is too low.
Anyway, we need a choice.

Regards

Re: [PATCH v3 05/11] net: stmmac: dwmac-rk: Add internal phy support

[David.Wu]

Hello Corentin, Chen-Yu

在 2017/8/9 16:45, Corentin Labbe 写道:
> On Thu, Aug 03, 2017 at 07:06:33PM +0800, Chen-Yu Tsai wrote:
>> On Thu, Aug 3, 2017 at 1:38 AM, Florian Fainelli <f.fainelli@gmail.com> wrote:
>>> On 08/01/2017 11:21 PM, David Wu wrote:
>>>> To make internal phy work, need to configure the phy_clock,
>>>> phy cru_reset and related registers.
>>>>
>>>> Signed-off-by: David Wu <david.wu@rock-chips.com>
>>>> ---
>>>>   .../devicetree/bindings/net/rockchip-dwmac.txt     |  6 +-
>>>>   drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c     | 81 ++++++++++++++++++++++
>>>>   2 files changed, 86 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
>>>> index 8f42755..ec39b31 100644
>>>> --- a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
>>>> +++ b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
>>>> @@ -25,7 +25,8 @@ Required properties:
>>>>    - clock-names: One name for each entry in the clocks property.
>>>>    - phy-mode: See ethernet.txt file in the same directory.
>>>>    - pinctrl-names: Names corresponding to the numbered pinctrl states.
>>>> - - pinctrl-0: pin-control mode. can be <&rgmii_pins> or <&rmii_pins>.
>>>> + - pinctrl-0: pin-control mode. can be <&rgmii_pins>, <&rmii_pins> or led pins
>>>> +   for internal phy mode.
>>>>    - clock_in_out: For RGMII, it must be "input", means main clock(125MHz)
>>>>      is not sourced from SoC's PLL, but input from PHY; For RMII, "input" means
>>>>      PHY provides the reference clock(50MHz), "output" means GMAC provides the
>>>> @@ -40,6 +41,9 @@ Optional properties:
>>>>    - tx_delay: Delay value for TXD timing. Range value is 0~0x7F, 0x30 as default.
>>>>    - rx_delay: Delay value for RXD timing. Range value is 0~0x7F, 0x10 as default.
>>>>    - phy-supply: phandle to a regulator if the PHY needs one
>>>> + - clocks: <&cru MAC_PHY>: Clock selector for internal macphy
>>>> + - phy-is-internal: A boolean property allows us to know that MAC will connect to
>>>> +   internal phy.
>>>
>>> This is incorrect in two ways:
>>>
>>> - this is a property of the PHY, so it should be documented as such in
>>> Documentation/devicetree/bindings/net/phy.txt so other bindings can
>>> re-use it
>>>
>>> - if it was specific to your MAC you would expect a vendor prefix to
>>> this property, which is not there
>>>
>>> An alternative way to implement the external/internal logic selection
>>> would be mandate that your Ethernet PHY node have a compatible string
>>> like this:
>>>
>>> phy@0 {
>>>          compatible = "ethernet-phy-id1234.d400", "ethernet-phy-802.3-c22";
>>> };
>>>
>>> Then you don't need this phy-is-internal property, because you can
>>> locate the PHY node by the phy-handle (see more about that in a reply to
>>> patch 10) and you can determine ahead of time whether this PHY is
>>> internal or not based on its compatible string.
>>
>> This doesn't really work for us (sunxi). The "internal" PHY of the H3
>> is also available in the X-Powers AC200 combo chip, which would be
>> external. Same ID. So if someone were to be stupid and put the two
>> together, you wouldn't know which one it actually is. Generically
>> it doesn't make sense to match against the ID either. The PHY is
>> only integrated or inlined into the SoC, meaning it could be moved
>> elsewhere or even be a discreet part.
>>
>> The way I see it is more like a reversed pinmux. The system should
>> select either the internal set or external set of xMII pins to use.
>>
>> A phy-is-internal property in the PHY node would work for us. We
>> already need a PHY node to describe its clocks and resets.
>>
>> A side note to this solution is that, since the internal PHY is defined
>> at the .dtsi level, any external PHYs at the same address would need to
>> make sure to delete the property, which is kind of counterintuitive, but
>> it is how device tree works. One would want to put the internal PHY's
>> address, assuming it is configurable, on something that is rarely used.
>>
> 
> Hello David, Florian, Andrew
> 
> Could someone ack this ? or nack if you think that the chance for having two PHY id both internal and external is too low.
> Anyway, we need a choice.
> 

I think we should be specific to the situation, for us we have the 
possibility that the Mac only picks up internal PHY, so this can be 
fixed at the. DTSi level, also possible INTERNL PHY's Mac can also be 
used to connect external PHY, while cutting off the connection with the 
internal PHY, so we should define the internal PHY at the DTS level, so 
I think Florian's approach is acceptable.

> Regards
> 
> 
> 

Re: [PATCH v3 05/11] net: stmmac: dwmac-rk: Add internal phy support

[Florian Fainelli]

On August 9, 2017 1:45:41 AM PDT, Corentin Labbe <clabbe.montjoie@gmail.com> wrote:
>On Thu, Aug 03, 2017 at 07:06:33PM +0800, Chen-Yu Tsai wrote:
>> On Thu, Aug 3, 2017 at 1:38 AM, Florian Fainelli
><f.fainelli@gmail.com> wrote:
>> > On 08/01/2017 11:21 PM, David Wu wrote:
>> >> To make internal phy work, need to configure the phy_clock,
>> >> phy cru_reset and related registers.
>> >>
>> >> Signed-off-by: David Wu <david.wu@rock-chips.com>
>> >> ---
>> >>  .../devicetree/bindings/net/rockchip-dwmac.txt     |  6 +-
>> >>  drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c     | 81
>++++++++++++++++++++++
>> >>  2 files changed, 86 insertions(+), 1 deletion(-)
>> >>
>> >> diff --git
>a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
>b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
>> >> index 8f42755..ec39b31 100644
>> >> --- a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
>> >> +++ b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
>> >> @@ -25,7 +25,8 @@ Required properties:
>> >>   - clock-names: One name for each entry in the clocks property.
>> >>   - phy-mode: See ethernet.txt file in the same directory.
>> >>   - pinctrl-names: Names corresponding to the numbered pinctrl
>states.
>> >> - - pinctrl-0: pin-control mode. can be <&rgmii_pins> or
><&rmii_pins>.
>> >> + - pinctrl-0: pin-control mode. can be <&rgmii_pins>,
><&rmii_pins> or led pins
>> >> +   for internal phy mode.
>> >>   - clock_in_out: For RGMII, it must be "input", means main
>clock(125MHz)
>> >>     is not sourced from SoC's PLL, but input from PHY; For RMII,
>"input" means
>> >>     PHY provides the reference clock(50MHz), "output" means GMAC
>provides the
>> >> @@ -40,6 +41,9 @@ Optional properties:
>> >>   - tx_delay: Delay value for TXD timing. Range value is 0~0x7F,
>0x30 as default.
>> >>   - rx_delay: Delay value for RXD timing. Range value is 0~0x7F,
>0x10 as default.
>> >>   - phy-supply: phandle to a regulator if the PHY needs one
>> >> + - clocks: <&cru MAC_PHY>: Clock selector for internal macphy
>> >> + - phy-is-internal: A boolean property allows us to know that MAC
>will connect to
>> >> +   internal phy.
>> >
>> > This is incorrect in two ways:
>> >
>> > - this is a property of the PHY, so it should be documented as such
>in
>> > Documentation/devicetree/bindings/net/phy.txt so other bindings can
>> > re-use it
>> >
>> > - if it was specific to your MAC you would expect a vendor prefix
>to
>> > this property, which is not there
>> >
>> > An alternative way to implement the external/internal logic
>selection
>> > would be mandate that your Ethernet PHY node have a compatible
>string
>> > like this:
>> >
>> > phy@0 {
>> >         compatible = "ethernet-phy-id1234.d400",
>"ethernet-phy-802.3-c22";
>> > };
>> >
>> > Then you don't need this phy-is-internal property, because you can
>> > locate the PHY node by the phy-handle (see more about that in a
>reply to
>> > patch 10) and you can determine ahead of time whether this PHY is
>> > internal or not based on its compatible string.
>> 
>> This doesn't really work for us (sunxi). The "internal" PHY of the H3
>> is also available in the X-Powers AC200 combo chip, which would be
>> external. Same ID. So if someone were to be stupid and put the two
>> together, you wouldn't know which one it actually is. Generically
>> it doesn't make sense to match against the ID either. The PHY is
>> only integrated or inlined into the SoC, meaning it could be moved
>> elsewhere or even be a discreet part.

It actually makes a lot of sense to differentiate on the PHY ID because you are supposed to allocate an unique ID based on how the integration of the PHY is done. Not doing that is making a sloppy job at integrating HW blocks, but such is life and there is no shortage of creativity amongst HW engineers when they are not given feedback from SW people.

>> 
>> The way I see it is more like a reversed pinmux. The system should
>> select either the internal set or external set of xMII pins to use.
>> 
>> A phy-is-internal property in the PHY node would work for us. We
>> already need a PHY node to describe its clocks and resets.
>> 
>> A side note to this solution is that, since the internal PHY is
>defined
>> at the .dtsi level, any external PHYs at the same address would need
>to
>> make sure to delete the property, which is kind of counterintuitive,
>but
>> it is how device tree works. One would want to put the internal PHY's
>> address, assuming it is configurable, on something that is rarely
>used.
>> 
>
>Hello David, Florian, Andrew
>
>Could someone ack this ? or nack if you think that the chance for
>having two PHY id both internal and external is too low.
>Anyway, we need a choice.

Let's move forward with the 'phy-is-integrated' Boolean property ('phy-is-internal' is too close from the proprietary "internal" phy-mode IMHO). Andrew, does that also work for you?

-- 
Florian

Re: [PATCH v3 05/11] net: stmmac: dwmac-rk: Add internal phy support

[Chen-Yu Tsai]

Hi David,

On Wed, Aug 9, 2017 at 5:38 PM, David.Wu <david.wu@rock-chips.com> wrote:
> Hello Corentin, Chen-Yu
>
>
> 在 2017/8/9 16:45, Corentin Labbe 写道:
>>
>> On Thu, Aug 03, 2017 at 07:06:33PM +0800, Chen-Yu Tsai wrote:
>>>
>>> On Thu, Aug 3, 2017 at 1:38 AM, Florian Fainelli <f.fainelli@gmail.com>
>>> wrote:
>>>>
>>>> On 08/01/2017 11:21 PM, David Wu wrote:
>>>>>
>>>>> To make internal phy work, need to configure the phy_clock,
>>>>> phy cru_reset and related registers.
>>>>>
>>>>> Signed-off-by: David Wu <david.wu@rock-chips.com>
>>>>> ---
>>>>>   .../devicetree/bindings/net/rockchip-dwmac.txt     |  6 +-
>>>>>   drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c     | 81
>>>>> ++++++++++++++++++++++
>>>>>   2 files changed, 86 insertions(+), 1 deletion(-)
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
>>>>> b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
>>>>> index 8f42755..ec39b31 100644
>>>>> --- a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
>>>>> +++ b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
>>>>> @@ -25,7 +25,8 @@ Required properties:
>>>>>    - clock-names: One name for each entry in the clocks property.
>>>>>    - phy-mode: See ethernet.txt file in the same directory.
>>>>>    - pinctrl-names: Names corresponding to the numbered pinctrl states.
>>>>> - - pinctrl-0: pin-control mode. can be <&rgmii_pins> or <&rmii_pins>.
>>>>> + - pinctrl-0: pin-control mode. can be <&rgmii_pins>, <&rmii_pins> or
>>>>> led pins
>>>>> +   for internal phy mode.
>>>>>    - clock_in_out: For RGMII, it must be "input", means main
>>>>> clock(125MHz)
>>>>>      is not sourced from SoC's PLL, but input from PHY; For RMII,
>>>>> "input" means
>>>>>      PHY provides the reference clock(50MHz), "output" means GMAC
>>>>> provides the
>>>>> @@ -40,6 +41,9 @@ Optional properties:
>>>>>    - tx_delay: Delay value for TXD timing. Range value is 0~0x7F, 0x30
>>>>> as default.
>>>>>    - rx_delay: Delay value for RXD timing. Range value is 0~0x7F, 0x10
>>>>> as default.
>>>>>    - phy-supply: phandle to a regulator if the PHY needs one
>>>>> + - clocks: <&cru MAC_PHY>: Clock selector for internal macphy
>>>>> + - phy-is-internal: A boolean property allows us to know that MAC will
>>>>> connect to
>>>>> +   internal phy.
>>>>
>>>>
>>>> This is incorrect in two ways:
>>>>
>>>> - this is a property of the PHY, so it should be documented as such in
>>>> Documentation/devicetree/bindings/net/phy.txt so other bindings can
>>>> re-use it
>>>>
>>>> - if it was specific to your MAC you would expect a vendor prefix to
>>>> this property, which is not there
>>>>
>>>> An alternative way to implement the external/internal logic selection
>>>> would be mandate that your Ethernet PHY node have a compatible string
>>>> like this:
>>>>
>>>> phy@0 {
>>>>          compatible = "ethernet-phy-id1234.d400",
>>>> "ethernet-phy-802.3-c22";
>>>> };
>>>>
>>>> Then you don't need this phy-is-internal property, because you can
>>>> locate the PHY node by the phy-handle (see more about that in a reply to
>>>> patch 10) and you can determine ahead of time whether this PHY is
>>>> internal or not based on its compatible string.
>>>
>>>
>>> This doesn't really work for us (sunxi). The "internal" PHY of the H3
>>> is also available in the X-Powers AC200 combo chip, which would be
>>> external. Same ID. So if someone were to be stupid and put the two
>>> together, you wouldn't know which one it actually is. Generically
>>> it doesn't make sense to match against the ID either. The PHY is
>>> only integrated or inlined into the SoC, meaning it could be moved
>>> elsewhere or even be a discreet part.
>>>
>>> The way I see it is more like a reversed pinmux. The system should
>>> select either the internal set or external set of xMII pins to use.
>>>
>>> A phy-is-internal property in the PHY node would work for us. We
>>> already need a PHY node to describe its clocks and resets.
>>>
>>> A side note to this solution is that, since the internal PHY is defined
>>> at the .dtsi level, any external PHYs at the same address would need to
>>> make sure to delete the property, which is kind of counterintuitive, but
>>> it is how device tree works. One would want to put the internal PHY's
>>> address, assuming it is configurable, on something that is rarely used.
>>>
>>
>> Hello David, Florian, Andrew
>>
>> Could someone ack this ? or nack if you think that the chance for having
>> two PHY id both internal and external is too low.
>> Anyway, we need a choice.
>>
>
> I think we should be specific to the situation, for us we have the
> possibility that the Mac only picks up internal PHY, so this can be fixed at
> the. DTSi level, also possible INTERNL PHY's Mac can also be used to connect
> external PHY, while cutting off the connection with the internal PHY, so we
> should define the internal PHY at the DTS level, so I think Florian's
> approach is acceptable.

So it looks like you have the clock for the internal/integrated PHY at the
MAC level. I think this lets you define/add the PHY at the board level more
easily without a lot of duplication?

Sunxi has the clock and reset in the PHY node, which is defined in the dtsi
file. (This part is already done.)

ChenYu

Re: [PATCH v3 05/11] net: stmmac: dwmac-rk: Add internal phy support

[David.Wu]

Hi Chen-Yu,

在 2017/8/10 10:40, Chen-Yu Tsai 写道:
> Hi David,
> 
> On Wed, Aug 9, 2017 at 5:38 PM, David.Wu <david.wu@rock-chips.com> wrote:
>> Hello Corentin, Chen-Yu
>>
>>
>> 在 2017/8/9 16:45, Corentin Labbe 写道:
>>>
>>> On Thu, Aug 03, 2017 at 07:06:33PM +0800, Chen-Yu Tsai wrote:
>>>>
>>>> On Thu, Aug 3, 2017 at 1:38 AM, Florian Fainelli <f.fainelli@gmail.com>
>>>> wrote:
>>>>>
>>>>> On 08/01/2017 11:21 PM, David Wu wrote:
>>>>>>
>>>>>> To make internal phy work, need to configure the phy_clock,
>>>>>> phy cru_reset and related registers.
>>>>>>
>>>>>> Signed-off-by: David Wu <david.wu@rock-chips.com>
>>>>>> ---
>>>>>>    .../devicetree/bindings/net/rockchip-dwmac.txt     |  6 +-
>>>>>>    drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c     | 81
>>>>>> ++++++++++++++++++++++
>>>>>>    2 files changed, 86 insertions(+), 1 deletion(-)
>>>>>>
>>>>>> diff --git a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
>>>>>> b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
>>>>>> index 8f42755..ec39b31 100644
>>>>>> --- a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
>>>>>> +++ b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
>>>>>> @@ -25,7 +25,8 @@ Required properties:
>>>>>>     - clock-names: One name for each entry in the clocks property.
>>>>>>     - phy-mode: See ethernet.txt file in the same directory.
>>>>>>     - pinctrl-names: Names corresponding to the numbered pinctrl states.
>>>>>> - - pinctrl-0: pin-control mode. can be <&rgmii_pins> or <&rmii_pins>.
>>>>>> + - pinctrl-0: pin-control mode. can be <&rgmii_pins>, <&rmii_pins> or
>>>>>> led pins
>>>>>> +   for internal phy mode.
>>>>>>     - clock_in_out: For RGMII, it must be "input", means main
>>>>>> clock(125MHz)
>>>>>>       is not sourced from SoC's PLL, but input from PHY; For RMII,
>>>>>> "input" means
>>>>>>       PHY provides the reference clock(50MHz), "output" means GMAC
>>>>>> provides the
>>>>>> @@ -40,6 +41,9 @@ Optional properties:
>>>>>>     - tx_delay: Delay value for TXD timing. Range value is 0~0x7F, 0x30
>>>>>> as default.
>>>>>>     - rx_delay: Delay value for RXD timing. Range value is 0~0x7F, 0x10
>>>>>> as default.
>>>>>>     - phy-supply: phandle to a regulator if the PHY needs one
>>>>>> + - clocks: <&cru MAC_PHY>: Clock selector for internal macphy
>>>>>> + - phy-is-internal: A boolean property allows us to know that MAC will
>>>>>> connect to
>>>>>> +   internal phy.
>>>>>
>>>>>
>>>>> This is incorrect in two ways:
>>>>>
>>>>> - this is a property of the PHY, so it should be documented as such in
>>>>> Documentation/devicetree/bindings/net/phy.txt so other bindings can
>>>>> re-use it
>>>>>
>>>>> - if it was specific to your MAC you would expect a vendor prefix to
>>>>> this property, which is not there
>>>>>
>>>>> An alternative way to implement the external/internal logic selection
>>>>> would be mandate that your Ethernet PHY node have a compatible string
>>>>> like this:
>>>>>
>>>>> phy@0 {
>>>>>           compatible = "ethernet-phy-id1234.d400",
>>>>> "ethernet-phy-802.3-c22";
>>>>> };
>>>>>
>>>>> Then you don't need this phy-is-internal property, because you can
>>>>> locate the PHY node by the phy-handle (see more about that in a reply to
>>>>> patch 10) and you can determine ahead of time whether this PHY is
>>>>> internal or not based on its compatible string.
>>>>
>>>>
>>>> This doesn't really work for us (sunxi). The "internal" PHY of the H3
>>>> is also available in the X-Powers AC200 combo chip, which would be
>>>> external. Same ID. So if someone were to be stupid and put the two
>>>> together, you wouldn't know which one it actually is. Generically
>>>> it doesn't make sense to match against the ID either. The PHY is
>>>> only integrated or inlined into the SoC, meaning it could be moved
>>>> elsewhere or even be a discreet part.
>>>>
>>>> The way I see it is more like a reversed pinmux. The system should
>>>> select either the internal set or external set of xMII pins to use.
>>>>
>>>> A phy-is-internal property in the PHY node would work for us. We
>>>> already need a PHY node to describe its clocks and resets.
>>>>
>>>> A side note to this solution is that, since the internal PHY is defined
>>>> at the .dtsi level, any external PHYs at the same address would need to
>>>> make sure to delete the property, which is kind of counterintuitive, but
>>>> it is how device tree works. One would want to put the internal PHY's
>>>> address, assuming it is configurable, on something that is rarely used.
>>>>
>>>
>>> Hello David, Florian, Andrew
>>>
>>> Could someone ack this ? or nack if you think that the chance for having
>>> two PHY id both internal and external is too low.
>>> Anyway, we need a choice.
>>>
>>
>> I think we should be specific to the situation, for us we have the
>> possibility that the Mac only picks up internal PHY, so this can be fixed at
>> the. DTSi level, also possible INTERNL PHY's Mac can also be used to connect
>> external PHY, while cutting off the connection with the internal PHY, so we
>> should define the internal PHY at the DTS level, so I think Florian's
>> approach is acceptable.
> 
> So it looks like you have the clock for the internal/integrated PHY at the
> MAC level. I think this lets you define/add the PHY at the board level more
> easily without a lot of duplication?
> 
> Sunxi has the clock and reset in the PHY node, which is defined in the dtsi
> file. (This part is already done.)

Okay, that is better difined in the PHY node, i'll move them later.

> 
> ChenYu
> 
> 
>