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From: "Liang, Kan" <kan.liang@linux.intel.com>
To: Namhyung Kim <namhyung@kernel.org>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>,
	Ingo Molnar <mingo@kernel.org>,
	linux-kernel <linux-kernel@vger.kernel.org>,
	Peter Zijlstra <peterz@infradead.org>,
	Stephane Eranian <eranian@google.com>,
	Jiri Olsa <jolsa@redhat.com>, Andi Kleen <ak@linux.intel.com>,
	Yao Jin <yao.jin@linux.intel.com>,
	maddy@linux.vnet.ibm.com
Subject: Re: [PATCH 2/9] perf tools: Support the auxiliary event
Date: Fri, 5 Feb 2021 09:13:34 -0500	[thread overview]
Message-ID: <33221095-5ef6-bec8-136e-34dc14ae7adb@linux.intel.com> (raw)
In-Reply-To: <CAM9d7cjDYALhR-xd2n2vaL5cPBiMz8RukziQqsfqqYwqBc87yA@mail.gmail.com>



On 2/5/2021 5:52 AM, Namhyung Kim wrote:
> On Wed, Feb 3, 2021 at 5:14 AM <kan.liang@linux.intel.com> wrote:
>>
>> From: Kan Liang <kan.liang@linux.intel.com>
>>
>> On the Intel Sapphire Rapids server, an auxiliary event has to be
>> enabled simultaneously with the load latency event to retrieve complete
>> Memory Info.
>>
>> Add X86 specific perf_mem_events__name() to handle the auxiliary event.
>> - Users are only interested in the samples of the mem-loads event.
>>    Sample read the auxiliary event.
>> - The auxiliary event must be in front of the load latency event in a
>>    group. Assume the second event to sample if the auxiliary event is the
>>    leader.
>> - Add a weak is_mem_loads_aux_event() to check the auxiliary event for
>>    X86. For other ARCHs, it always return false.
>>
>> Parse the unique event name, mem-loads-aux, for the auxiliary event.
>>
>> Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
>> ---
>>   tools/perf/arch/x86/util/Build        |  1 +
>>   tools/perf/arch/x86/util/mem-events.c | 44 +++++++++++++++++++++++++++++++++++
>>   tools/perf/util/evsel.c               |  3 +++
>>   tools/perf/util/mem-events.c          |  5 ++++
>>   tools/perf/util/mem-events.h          |  2 ++
>>   tools/perf/util/parse-events.l        |  1 +
>>   tools/perf/util/record.c              |  5 +++-
>>   7 files changed, 60 insertions(+), 1 deletion(-)
>>   create mode 100644 tools/perf/arch/x86/util/mem-events.c
>>
>> diff --git a/tools/perf/arch/x86/util/Build b/tools/perf/arch/x86/util/Build
>> index 347c39b..d73f548 100644
>> --- a/tools/perf/arch/x86/util/Build
>> +++ b/tools/perf/arch/x86/util/Build
>> @@ -6,6 +6,7 @@ perf-y += perf_regs.o
>>   perf-y += topdown.o
>>   perf-y += machine.o
>>   perf-y += event.o
>> +perf-y += mem-events.o
>>
>>   perf-$(CONFIG_DWARF) += dwarf-regs.o
>>   perf-$(CONFIG_BPF_PROLOGUE) += dwarf-regs.o
>> diff --git a/tools/perf/arch/x86/util/mem-events.c b/tools/perf/arch/x86/util/mem-events.c
>> new file mode 100644
>> index 0000000..11b8469
>> --- /dev/null
>> +++ b/tools/perf/arch/x86/util/mem-events.c
>> @@ -0,0 +1,44 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +#include "util/pmu.h"
>> +#include "map_symbol.h"
>> +#include "mem-events.h"
>> +
>> +static char mem_loads_name[100];
>> +static bool mem_loads_name__init;
>> +
>> +#define MEM_LOADS_AUX          0x8203
>> +#define MEM_LOADS_AUX_NAME     "{cpu/mem-loads-aux/,cpu/mem-loads,ldlat=%u/pp}:S"
>> +
>> +bool is_mem_loads_aux_event(struct evsel *leader)
>> +{
>> +       if (!pmu_have_event("cpu", "mem-loads-aux"))
>> +               return false;
>> +
>> +       return leader->core.attr.config == MEM_LOADS_AUX;
>> +}
>> +
>> +char *perf_mem_events__name(int i)
>> +{
>> +       struct perf_mem_event *e = perf_mem_events__ptr(i);
>> +
>> +       if (!e)
>> +               return NULL;
>> +
>> +       if (i == PERF_MEM_EVENTS__LOAD) {
>> +               if (mem_loads_name__init)
>> +                       return mem_loads_name;
>> +
>> +               mem_loads_name__init = true;
>> +
>> +               if (pmu_have_event("cpu", "mem-loads-aux")) {
>> +                       scnprintf(mem_loads_name, sizeof(MEM_LOADS_AUX_NAME),
>> +                                 MEM_LOADS_AUX_NAME, perf_mem_events__loads_ldlat);
> 
> It changes "%u" to an actual latency value, right?
> What if the value takes 3 or more digits?
> I'm not sure scnprintf() will handle it properly.
>

Yes, you are right. We should use the sizeof(mem_loads_name) as below.
I will submit a patch to fix it.

diff --git a/tools/perf/arch/x86/util/mem-events.c 
b/tools/perf/arch/x86/util/mem-events.c
index 11b8469..588110f 100644
--- a/tools/perf/arch/x86/util/mem-events.c
+++ b/tools/perf/arch/x86/util/mem-events.c
@@ -31,7 +31,7 @@ char *perf_mem_events__name(int i)
  		mem_loads_name__init = true;

  		if (pmu_have_event("cpu", "mem-loads-aux")) {
-			scnprintf(mem_loads_name, sizeof(MEM_LOADS_AUX_NAME),
+			scnprintf(mem_loads_name, sizeof(mem_loads_name),
  				  MEM_LOADS_AUX_NAME, perf_mem_events__loads_ldlat);
  		} else {
  			scnprintf(mem_loads_name, sizeof(mem_loads_name),




Thanks,
Kan


  reply	other threads:[~2021-02-05 22:37 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-02 20:09 [PATCH 0/9] perf core PMU support for Sapphire Rapids (User tools) kan.liang
2021-02-02 20:09 ` [PATCH 1/9] tools headers uapi: Update tools's copy of linux/perf_event.h kan.liang
2021-02-02 20:09 ` [PATCH 2/9] perf tools: Support the auxiliary event kan.liang
2021-02-03 20:02   ` Arnaldo Carvalho de Melo
2021-02-03 21:20     ` Liang, Kan
2021-02-03 21:30       ` Arnaldo Carvalho de Melo
2021-02-05 10:52   ` Namhyung Kim
2021-02-05 14:13     ` Liang, Kan [this message]
2021-02-05 15:26       ` Arnaldo Carvalho de Melo
2021-02-05 15:45         ` Liang, Kan
2021-02-02 20:09 ` [PATCH 3/9] perf tools: Support data block and addr block kan.liang
2021-02-05 11:02   ` Namhyung Kim
2021-02-05 14:17     ` Liang, Kan
2021-02-02 20:09 ` [PATCH 4/9] perf c2c: " kan.liang
2021-02-03 20:21   ` Arnaldo Carvalho de Melo
2021-02-02 20:09 ` [PATCH 5/9] perf tools: Support PERF_SAMPLE_WEIGHT_STRUCT kan.liang
2021-02-03 20:31   ` Arnaldo Carvalho de Melo
2021-02-03 21:19     ` Liang, Kan
2021-02-03 21:29       ` Arnaldo Carvalho de Melo
2021-02-02 20:09 ` [PATCH 6/9] perf report: Support instruction latency kan.liang
2021-02-03 20:43   ` Arnaldo Carvalho de Melo
2021-02-04 13:11   ` Athira Rajeev
2021-02-04 15:19     ` Liang, Kan
2021-02-05 12:55       ` Athira Rajeev
2021-02-05 14:51         ` Liang, Kan
2021-02-07 16:45           ` Athira Rajeev
2021-02-05 11:08   ` Namhyung Kim
2021-02-05 14:38     ` Liang, Kan
2021-02-06  8:09       ` Namhyung Kim
2021-02-08 13:50         ` Liang, Kan
2021-02-02 20:09 ` [PATCH 7/9] perf test: Support PERF_SAMPLE_WEIGHT_STRUCT kan.liang
2021-02-03 20:44   ` Arnaldo Carvalho de Melo
2021-02-02 20:09 ` [PATCH 8/9] perf stat: Support L2 Topdown events kan.liang
2021-02-02 20:09 ` [PATCH 9/9] perf, tools: Update topdown documentation for Sapphire Rapids kan.liang

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