[PATCH v9 0/3] Altera Cyclone Passive Serial SPI FPGA Manager

[PATCH v9 0/3] Altera Cyclone Passive Serial SPI FPGA Manager

[Joshua Clayton]

>From c429cec34a880c0d5438091f436a5946a4db3fc0 Mon Sep 17 00:00:00 2001
Message-Id: <cover.1485211400.git.stillcompiling@gmail.com>
From: Joshua Clayton <stillcompiling@gmail.com>
Date: Mon, 23 Jan 2017 14:43:20 -0800
Subject: [PATCH v8 0/3] Altera Cyclone Passive Serial SPI FPGA Manager

This series adds an FPGA manager for Altera cyclone FPGAs
that can program them using an spi port and a couple of gpios, using
Alteras passive serial protocol.

Changes from v8:
- List the confd pin as optional (it is an additional way to confirm
  the FPGA is done loading, but is not accessible in my hardare)

Changes from v7:
Add Rob Herrings Ack on the bindings change (Thanks!)
Change const u8* to const char * to make sparse happy

Changes from v6:
- moved bitrev8x4() out (I'll submit it in a separate patch set)
- Changed the dts format to match what is already done in barebox
  (see https://git.pengutronix.de/cgit/barebox/tree/Documentation/devicetree/bindings/firmware/altr,passive-serial.txt)
- Changed error message from "Status pin should be low" to "Status
  pin failed to show a reset" for better clarity
- Fixed any whitespace problems that had crept in.

Changes from v5:
- Rebased on next-20161214xi
- Corrected for FPGA Mgr API change in  write_init() and write_complete()
- Better describe the device cyclone-ps-spi runs on in the file header.
- Split the bitrev8x4 patch into generic and arch specific patches...
- Added AARCH64 and MIPS implementations of bitrev8x4()... they all have to 
  have an implementation for it to compile cleanly across platforms
- Added the changes to imx6q-evi.dts to the patch set.

Changes from v4:
- Added the needed return statement to __arch_bitrev8x4()
- Added Rob Herrings ACK for and fix a typo in the commit log of patch 2

Changes from v3:
- Fixed up the state() function to return the state of the status pin
  reqested by Alan Tull
- Switched the pin to ACTIVE_LOW and coresponding logic level, and updated
  the corresponding documentation. Thanks Rob Herring for pointing out my
  mistake.
- Per Rob Herring, switched from "gpio" to "gpios" in dts

Changes from v2:
- Merged patch 3 and 4 as suggested in review by Moritz Fischer
- Changed FPGA_MIN_DELAY from 250 to 50 ms is the time advertized by
  Altera. This now works, as we don't assume it is done

Changes from v1:
- Changed the name from cyclone-spi-fpga-mgr to cyclone-ps-spi-fpga-mgr
  This name change was requested by Alan Tull, to be specific about which
  programming method is being employed on the fpga.
- Changed the name of the reset-gpio to config-gpio to closer match the
  way the pins are described in the Altera manual
- Moved MODULE_LICENCE, _AUTHOR, and _DESCRIPTION to the bottom

- Added a bitrev8x4() function to the bitrev headers and implemented ARM
 const, runtime, and ARM specific faster versions (This may end up
 needing to be a standalone patch)

- Moved the bitswapping into cyclonespi_write(), as requested.
  This falls short of my desired generic lsb first spi support, but is a step
  in that direction.

- Fixed whitespace problems introduced during refactoring

- Replaced magic number for initial delay with a descriptive macro
- Poll the fpga to see when it is ready rather than a fixed 1 ms sleep

*** BLURB HERE ***

Joshua Clayton (3):
  doc: dt: add cyclone-ps-spi binding document
  fpga manager: Add cyclone-ps-spi driver for Altera FPGAs
  ARM: dts: imx6q-evi: support cyclone-ps-spi

 .../bindings/fpga/altera-passive-serial.txt        |  29 ++++
 arch/arm/boot/dts/imx6q-evi.dts                    |  16 ++
 drivers/fpga/Kconfig                               |   7 +
 drivers/fpga/Makefile                              |   1 +
 drivers/fpga/cyclone-ps-spi.c                      | 185 +++++++++++++++++++++
 5 files changed, 238 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/altera-passive-serial.txt
 create mode 100644 drivers/fpga/cyclone-ps-spi.c

-- 
2.9.3

[PATCH v9 1/3] doc: dt: add cyclone-ps-spi binding document

[Joshua Clayton]

Describe a cyclone-ps-spi devicetree entry, required features

Signed-off-by: Joshua Clayton <stillcompiling@gmail.com>
---
 .../bindings/fpga/altera-passive-serial.txt        | 29 ++++++++++++++++++++++
 1 file changed, 29 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/altera-passive-serial.txt

diff --git a/Documentation/devicetree/bindings/fpga/altera-passive-serial.txt b/Documentation/devicetree/bindings/fpga/altera-passive-serial.txt
new file mode 100644
index 0000000..774e6a7
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/altera-passive-serial.txt
@@ -0,0 +1,29 @@
+Altera Cyclone Passive Serial SPI FPGA Manager
+
+Altera Cyclone FPGAs support a method of loading the bitstream over what is
+referred to as "passive serial".
+The passive serial link is not technically spi, and might require extra
+circuits in order to play nicely with other spi slaves on the same bus.
+
+See https://www.altera.com/literature/hb/cyc/cyc_c51013.pdf
+
+Required properties:
+- compatible: should contain "altr,fpga-passive-serial"
+- reg: spi chip select of the FPGA
+- nconfig-gpios: config pin (referred to as nCONFIG in the cyclone manual)
+- nstat-gpios: status pin (referred to as nSTATUS in the cyclone manual)
+
+Optional properties:
+- confd-gpios: confd pin (referred to as CONF_DONE in the cyclone manual)
+
+
+
+Example:
+	fpga_spi: evi-fpga-spi@0 {
+		compatible = "altr,cyclone-ps-spi-fpga-mgr";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+		nconfig-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
+		nstat-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
+		confd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
+	};
-- 
2.9.3

Re: [PATCH v9 1/3] doc: dt: add cyclone-ps-spi binding document

[Rob Herring]

On Tue, Jan 24, 2017 at 02:19:32PM -0800, Joshua Clayton wrote:
> Describe a cyclone-ps-spi devicetree entry, required features
> 
> Signed-off-by: Joshua Clayton <stillcompiling@gmail.com>
> ---
>  .../bindings/fpga/altera-passive-serial.txt        | 29 ++++++++++++++++++++++
>  1 file changed, 29 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/fpga/altera-passive-serial.txt

This is a minor change, you could have kept my ack.

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH v9 1/3] doc: dt: add cyclone-ps-spi binding document

[Joshua Clayton]

Thanks, Rob.


On 01/27/2017 02:28 PM, Rob Herring wrote:
> On Tue, Jan 24, 2017 at 02:19:32PM -0800, Joshua Clayton wrote:
>> Describe a cyclone-ps-spi devicetree entry, required features
>>
>> Signed-off-by: Joshua Clayton <stillcompiling@gmail.com>
>> ---
>>  .../bindings/fpga/altera-passive-serial.txt        | 29 ++++++++++++++++++++++
>>  1 file changed, 29 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/fpga/altera-passive-serial.txt
> This is a minor change, you could have kept my ack.
>
> Acked-by: Rob Herring <robh@kernel.org>
I know you have a lot of these to wade through.
I'll remember that going forward.

[PATCH v9 2/3] fpga manager: Add cyclone-ps-spi driver for Altera FPGAs

[Joshua Clayton]

cyclone-ps-spi loads FPGA firmware over spi, using the "passive serial"
interface on Altera Cyclone FPGAS.

This is one of the simpler ways to set up an FPGA at runtime.
The signal interface is close to unidirectional spi with lsb first.

Signed-off-by: Joshua Clayton <stillcompiling@gmail.com>
---
 drivers/fpga/Kconfig          |   7 ++
 drivers/fpga/Makefile         |   1 +
 drivers/fpga/cyclone-ps-spi.c | 185 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 193 insertions(+)
 create mode 100644 drivers/fpga/cyclone-ps-spi.c

diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index ce861a2..e6c032d 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -20,6 +20,13 @@ config FPGA_REGION
 	  FPGA Regions allow loading FPGA images under control of
 	  the Device Tree.
 
+config FPGA_MGR_CYCLONE_PS_SPI
+	tristate "Altera Cyclone FPGA Passive Serial over SPI"
+	depends on SPI
+	help
+	  FPGA manager driver support for Altera Cyclone using the
+	  passive serial interface over SPI
+
 config FPGA_MGR_SOCFPGA
 	tristate "Altera SOCFPGA FPGA Manager"
 	depends on ARCH_SOCFPGA || COMPILE_TEST
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 8df07bc..a112bef 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -6,6 +6,7 @@
 obj-$(CONFIG_FPGA)			+= fpga-mgr.o
 
 # FPGA Manager Drivers
+obj-$(CONFIG_FPGA_MGR_CYCLONE_PS_SPI)	+= cyclone-ps-spi.o
 obj-$(CONFIG_FPGA_MGR_SOCFPGA)		+= socfpga.o
 obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10)	+= socfpga-a10.o
 obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)	+= zynq-fpga.o
diff --git a/drivers/fpga/cyclone-ps-spi.c b/drivers/fpga/cyclone-ps-spi.c
new file mode 100644
index 0000000..56c3853
--- /dev/null
+++ b/drivers/fpga/cyclone-ps-spi.c
@@ -0,0 +1,185 @@
+/**
+ * Altera Cyclone Passive Serial SPI Driver
+ *
+ *  Copyright (c) 2017 United Western Technologies, Corporation
+ *
+ *  Joshua Clayton <stillcompiling@gmail.com>
+ *
+ * Manage Altera FPGA firmware that is loaded over spi using the passive
+ * serial configuration method.
+ * Firmware must be in binary "rbf" format.
+ * Works on Cyclone V. Should work on cyclone series.
+ * May work on other Altera FPGAs.
+ *
+ */
+
+#include <linux/bitrev.h>
+#include <linux/delay.h>
+#include <linux/fpga/fpga-mgr.h>
+#include <linux/gpio/consumer.h>
+#include <linux/module.h>
+#include <linux/of_gpio.h>
+#include <linux/spi/spi.h>
+#include <linux/sizes.h>
+
+#define FPGA_RESET_TIME		50   /* time in usecs to trigger FPGA config */
+#define FPGA_MIN_DELAY		50   /* min usecs to wait for config status */
+#define FPGA_MAX_DELAY		1000 /* max usecs to wait for config status */
+
+struct cyclonespi_conf {
+	struct gpio_desc *config;
+	struct gpio_desc *status;
+	struct spi_device *spi;
+};
+
+static const struct of_device_id of_ef_match[] = {
+	{ .compatible = "altr,fpga-passive-serial", },
+	{}
+};
+MODULE_DEVICE_TABLE(of, of_ef_match);
+
+static enum fpga_mgr_states cyclonespi_state(struct fpga_manager *mgr)
+{
+	struct cyclonespi_conf *conf = (struct cyclonespi_conf *)mgr->priv;
+
+	if (gpiod_get_value(conf->status))
+		return FPGA_MGR_STATE_RESET;
+
+	return FPGA_MGR_STATE_UNKNOWN;
+}
+
+static int cyclonespi_write_init(struct fpga_manager *mgr,
+				 struct fpga_image_info *info,
+				 const char *buf, size_t count)
+{
+	struct cyclonespi_conf *conf = (struct cyclonespi_conf *)mgr->priv;
+	int i;
+
+	if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) {
+		dev_err(&mgr->dev, "Partial reconfiguration not supported.\n");
+		return -EINVAL;
+	}
+
+	gpiod_set_value(conf->config, 1);
+	usleep_range(FPGA_RESET_TIME, FPGA_RESET_TIME + 20);
+	if (!gpiod_get_value(conf->status)) {
+		dev_err(&mgr->dev, "Status pin failed to show a reset\n");
+		return -EIO;
+	}
+
+	gpiod_set_value(conf->config, 0);
+	for (i = 0; i < (FPGA_MAX_DELAY / FPGA_MIN_DELAY); i++) {
+		usleep_range(FPGA_MIN_DELAY, FPGA_MIN_DELAY + 20);
+		if (!gpiod_get_value(conf->status))
+			return 0;
+	}
+
+	dev_err(&mgr->dev, "Status pin not ready.\n");
+	return -EIO;
+}
+
+static void rev_buf(char *buf, size_t len)
+{
+	const char *fw_end = (buf + len);
+
+	/* set buffer to lsb first */
+	while (buf < fw_end) {
+		*buf = bitrev8(*buf);
+		buf++;
+	}
+}
+
+static int cyclonespi_write(struct fpga_manager *mgr, const char *buf,
+			    size_t count)
+{
+	struct cyclonespi_conf *conf = (struct cyclonespi_conf *)mgr->priv;
+	const char *fw_data = buf;
+	const char *fw_data_end = fw_data + count;
+
+	while (fw_data < fw_data_end) {
+		int ret;
+		size_t stride = min(fw_data_end - fw_data, SZ_4K);
+
+		rev_buf(fw_data, stride);
+		ret = spi_write(conf->spi, fw_data, stride);
+		if (ret) {
+			dev_err(&mgr->dev, "spi error in firmware write: %d\n",
+				ret);
+			return ret;
+		}
+		fw_data += stride;
+	}
+
+	return 0;
+}
+
+static int cyclonespi_write_complete(struct fpga_manager *mgr,
+				     struct fpga_image_info *info)
+{
+	struct cyclonespi_conf *conf = (struct cyclonespi_conf *)mgr->priv;
+
+	if (gpiod_get_value(conf->status)) {
+		dev_err(&mgr->dev, "Error during configuration.\n");
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static const struct fpga_manager_ops cyclonespi_ops = {
+	.state = cyclonespi_state,
+	.write_init = cyclonespi_write_init,
+	.write = cyclonespi_write,
+	.write_complete = cyclonespi_write_complete,
+};
+
+static int cyclonespi_probe(struct spi_device *spi)
+{
+	struct cyclonespi_conf *conf = devm_kzalloc(&spi->dev, sizeof(*conf),
+						    GFP_KERNEL);
+
+	if (!conf)
+		return -ENOMEM;
+
+	conf->spi = spi;
+	conf->config = devm_gpiod_get(&spi->dev, "nconfig", GPIOD_OUT_HIGH);
+	if (IS_ERR(conf->config)) {
+		dev_err(&spi->dev, "Failed to get config gpio: %ld\n",
+			PTR_ERR(conf->config));
+		return PTR_ERR(conf->config);
+	}
+
+	conf->status = devm_gpiod_get(&spi->dev, "nstat", GPIOD_IN);
+	if (IS_ERR(conf->status)) {
+		dev_err(&spi->dev, "Failed to get status gpio: %ld\n",
+			PTR_ERR(conf->status));
+		return PTR_ERR(conf->status);
+	}
+
+	return fpga_mgr_register(&spi->dev,
+				 "Altera Cyclone PS SPI FPGA Manager",
+				 &cyclonespi_ops, conf);
+}
+
+static int cyclonespi_remove(struct spi_device *spi)
+{
+	fpga_mgr_unregister(&spi->dev);
+
+	return 0;
+}
+
+static struct spi_driver cyclonespi_driver = {
+	.driver = {
+		.name = "cyclone-ps-spi",
+		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(of_ef_match),
+	},
+	.probe = cyclonespi_probe,
+	.remove = cyclonespi_remove,
+};
+
+module_spi_driver(cyclonespi_driver)
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Joshua Clayton <stillcompiling@gmail.com>");
+MODULE_DESCRIPTION("Module to load Altera FPGA firmware over spi");
-- 
2.9.3

Re: [PATCH v9 2/3] fpga manager: Add cyclone-ps-spi driver for Altera FPGAs

[Anatolij Gustschin]

Hi Joshua,

On Tue, 24 Jan 2017 14:19:33 -0800
Joshua Clayton stillcompiling@gmail.com wrote:
...
>+static int cyclonespi_write(struct fpga_manager *mgr, const char *buf,
>+			    size_t count)
>+{
>+	struct cyclonespi_conf *conf = (struct cyclonespi_conf *)mgr->priv;
>+	const char *fw_data = buf;
>+	const char *fw_data_end = fw_data + count;
>+
>+	while (fw_data < fw_data_end) {
>+		int ret;
>+		size_t stride = min(fw_data_end - fw_data, SZ_4K);
>+
>+		rev_buf(fw_data, stride);

Can we make rev_buf() optional here? I've tested this driver with
Stratix-V FPGA using orion_spi driver. It works without swapping
the data.

Thanks,
Anatolij

Re: [PATCH v9 2/3] fpga manager: Add cyclone-ps-spi driver for Altera FPGAs

[Alan Tull]

On Wed, Feb 15, 2017 at 9:26 AM, Anatolij Gustschin <agust@denx.de> wrote:
> Hi Joshua,
>
> On Tue, 24 Jan 2017 14:19:33 -0800
> Joshua Clayton stillcompiling@gmail.com wrote:
> ...
>>+static int cyclonespi_write(struct fpga_manager *mgr, const char *buf,
>>+                          size_t count)
>>+{
>>+      struct cyclonespi_conf *conf = (struct cyclonespi_conf *)mgr->priv;
>>+      const char *fw_data = buf;
>>+      const char *fw_data_end = fw_data + count;
>>+
>>+      while (fw_data < fw_data_end) {
>>+              int ret;
>>+              size_t stride = min(fw_data_end - fw_data, SZ_4K);
>>+
>>+              rev_buf(fw_data, stride);
>
> Can we make rev_buf() optional here? I've tested this driver with
> Stratix-V FPGA using orion_spi driver. It works without swapping
> the data.

I replied earlier, but something in my email settings bounced.

The way to make it optional is to add a bit to the flags of the
fpga_image_info struct.

Alan

>
> Thanks,
> Anatolij

Re: [PATCH v9 2/3] fpga manager: Add cyclone-ps-spi driver for Altera FPGAs

[Joshua Clayton]

On 02/15/2017 09:14 AM, Alan Tull wrote:
> On Wed, Feb 15, 2017 at 9:26 AM, Anatolij Gustschin <agust@denx.de> wrote:
>> Hi Joshua,
>>
>> On Tue, 24 Jan 2017 14:19:33 -0800
>> Joshua Clayton stillcompiling@gmail.com wrote:
>> ...
>>> +static int cyclonespi_write(struct fpga_manager *mgr, const char *buf,
>>> +                          size_t count)
>>> +{
>>> +      struct cyclonespi_conf *conf = (struct cyclonespi_conf *)mgr->priv;
>>> +      const char *fw_data = buf;
>>> +      const char *fw_data_end = fw_data + count;
>>> +
>>> +      while (fw_data < fw_data_end) {
>>> +              int ret;
>>> +              size_t stride = min(fw_data_end - fw_data, SZ_4K);
>>> +
>>> +              rev_buf(fw_data, stride);
>> Can we make rev_buf() optional here? I've tested this driver with
>> Stratix-V FPGA using orion_spi driver. It works without swapping
>> the data.
Thanks for testing!
I'd be happy to make it an optional feature, rather than integral.
> I replied earlier, but something in my email settings bounced.
>
> The way to make it optional is to add a bit to the flags of the
> fpga_image_info struct.
>
> Alan
OK.
>
>> Thanks,
>> Anatolij

[PATCH v9 3/3] ARM: dts: imx6q-evi: support cyclone-ps-spi

[Joshua Clayton]

Add support for Altera cyclone V FPGA connected to an spi port
to the evi devicetree file

Signed-off-by: Joshua Clayton <stillcompiling@gmail.com>
---
 arch/arm/boot/dts/imx6q-evi.dts | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/imx6q-evi.dts
index 79a0bd5..e531bf7 100644
--- a/arch/arm/boot/dts/imx6q-evi.dts
+++ b/arch/arm/boot/dts/imx6q-evi.dts
@@ -83,6 +83,15 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1cs>;
 	status = "okay";
+
+	fpga_spi: cyclonespi@0 {
+		compatible = "altr,fpga-passive-serial";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+		pinctrl-0 = <&pinctrl_fpgaspi>;
+		nconfig-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
+		nstat-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
+	};
 };
 
 &ecspi3 {
@@ -316,6 +325,13 @@
 		>;
 	};
 
+	pinctrl_fpgaspi: fpgaspigrp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
+			MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
+		>;
+	};
+
 	pinctrl_gpminand: gpminandgrp {
 		fsl,pins = <
 			MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
-- 
2.9.3