[PATCH v5 0/6] soc: qcom: llcc: Add support for QDU1000/QRU1000

[PATCH v5 0/6] soc: qcom: llcc: Add support for QDU1000/QRU1000

[Komal Bajaj]

This patch series does the following -
 * Refactor LLCC driver to support multiple configuration
 * Add stub function for nvmem_cell_read_u8
 * Add support for multi channel DDR configuration in LLCC
 * Add LLCC support for the Qualcomm QDU1000 and QRU1000 SoCs

Changes in v5 -
 - Seperated out the secure qfprom driver changes to a separate series [1].
 - Created a wrapper struct with a pointer to qcom_llcc_config and
   length of array qcom_llcc_config.
 - Added stub function for nvmem_cell_read_u8.
 - Split commit 6/6 in the previous series into two commits.

Changes in v4 -
 - Created a separate driver for reading from secure fuse region as suggested.
 - Added patch for dt-bindings of secure qfprom driver accordingly.
 - Added new properties in the dt-bindings for LLCC. 
 - Implemented new logic to read the nvmem cell as suggested by Bjorn.
 - Separating the DT patches from this series as per suggestion.

Changes in v3-
 - Addressed comments from Krzysztof and Mani.
 - Using qfprom to read DDR configuration from feature register.

Changes in v2:
  - Addressing comments from Konrad.

[1] https://lore.kernel.org/linux-arm-msm/20230724082946.7441-1-quic_kbajaj@quicinc.com/

Komal Bajaj (6):
  dt-bindings: cache: qcom,llcc: Add LLCC compatible for QDU1000/QRU1000
  soc: qcom: llcc: Refactor llcc driver to support multiple
    configuration
  nvmem: core: Add stub for nvmem_cell_read_u8
  soc: qcom: Add LLCC support for multi channel DDR
  soc: qcom: llcc: Updating the macro name
  soc: qcom: llcc: Add QDU1000 and QRU1000 LLCC support

 .../devicetree/bindings/cache/qcom,llcc.yaml  |  10 +
 drivers/soc/qcom/llcc-qcom.c                  | 357 +++++++++++++-----
 include/linux/nvmem-consumer.h                |   6 +
 include/linux/soc/qcom/llcc-qcom.h            |   2 +-
 4 files changed, 287 insertions(+), 88 deletions(-)

-- 
2.40.1

[PATCH v5 1/6] dt-bindings: cache: qcom,llcc: Add LLCC compatible for QDU1000/QRU1000

[Komal Bajaj]

Add LLCC compatible for QDU1000/QRU1000 SoCs and add optional
nvmem-cells and nvmem-cell-names properties to support multiple
configurations for multi channel DDR.

Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
---
 Documentation/devicetree/bindings/cache/qcom,llcc.yaml | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
index 44892aa589fd..580f9a97ddf7 100644
--- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
+++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
@@ -20,6 +20,7 @@ description: |
 properties:
   compatible:
     enum:
+      - qcom,qdu1000-llcc
       - qcom,sc7180-llcc
       - qcom,sc7280-llcc
       - qcom,sc8180x-llcc
@@ -44,6 +45,14 @@ properties:
   interrupts:
     maxItems: 1
 
+  nvmem-cells:
+    items:
+      - description: Reference to an nvmem node for multi channel DDR
+
+  nvmem-cell-names:
+    items:
+      - const: multi-chan-ddr
+
 required:
   - compatible
   - reg
@@ -92,6 +101,7 @@ allOf:
         compatible:
           contains:
             enum:
+              - qcom,qdu1000-llcc
               - qcom,sc8180x-llcc
               - qcom,sc8280xp-llcc
     then:
-- 
2.40.1

[PATCH v5 2/6] soc: qcom: llcc: Refactor llcc driver to support multiple configuration

[Komal Bajaj]

Refactor driver to support multiple configuration for llcc on a target.

Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
---
 drivers/soc/qcom/llcc-qcom.c | 264 +++++++++++++++++++++++------------
 1 file changed, 178 insertions(+), 86 deletions(-)

diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index 67c19ed2219a..321f8d2079f7 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -127,6 +127,12 @@ struct qcom_llcc_config {
 	bool no_edac;
 };
 
+struct qcom_sct_config {
+	const struct qcom_llcc_config *llcc_config;
+	int num_cfgs;
+};
+
+
 enum llcc_reg_offset {
 	LLCC_COMMON_HW_INFO,
 	LLCC_COMMON_STATUS0,
@@ -423,101 +429,185 @@ static const u32 llcc_v2_1_reg_offset[] = {
 	[LLCC_COMMON_STATUS0]	= 0x0003400c,
 };
 
-static const struct qcom_llcc_config sc7180_cfg = {
-	.sct_data	= sc7180_data,
-	.size		= ARRAY_SIZE(sc7180_data),
-	.need_llcc_cfg	= true,
-	.reg_offset	= llcc_v1_reg_offset,
-	.edac_reg_offset = &llcc_v1_edac_reg_offset,
+static const struct qcom_llcc_config sc7180_cfg[] = {
+	{
+		.sct_data	= sc7180_data,
+		.size		= ARRAY_SIZE(sc7180_data),
+		.need_llcc_cfg	= true,
+		.reg_offset	= llcc_v1_reg_offset,
+		.edac_reg_offset = &llcc_v1_edac_reg_offset,
+	},
+};
+
+static const struct qcom_llcc_config sc7280_cfg[] = {
+	{
+		.sct_data	= sc7280_data,
+		.size		= ARRAY_SIZE(sc7280_data),
+		.need_llcc_cfg	= true,
+		.reg_offset	= llcc_v1_reg_offset,
+		.edac_reg_offset = &llcc_v1_edac_reg_offset,
+	},
+};
+
+static const struct qcom_llcc_config sc8180x_cfg[] = {
+	{
+		.sct_data	= sc8180x_data,
+		.size		= ARRAY_SIZE(sc8180x_data),
+		.need_llcc_cfg	= true,
+		.reg_offset	= llcc_v1_reg_offset,
+		.edac_reg_offset = &llcc_v1_edac_reg_offset,
+	},
+};
+
+static const struct qcom_llcc_config sc8280xp_cfg[] = {
+	{
+		.sct_data	= sc8280xp_data,
+		.size		= ARRAY_SIZE(sc8280xp_data),
+		.need_llcc_cfg	= true,
+		.reg_offset	= llcc_v1_reg_offset,
+		.edac_reg_offset = &llcc_v1_edac_reg_offset,
+	},
+};
+
+static const struct qcom_llcc_config sdm845_cfg[] = {
+	{
+		.sct_data	= sdm845_data,
+		.size		= ARRAY_SIZE(sdm845_data),
+		.need_llcc_cfg	= false,
+		.reg_offset	= llcc_v1_reg_offset,
+		.edac_reg_offset = &llcc_v1_edac_reg_offset,
+		.no_edac	= true,
+	},
+};
+
+static const struct qcom_llcc_config sm6350_cfg[] = {
+	{
+		.sct_data	= sm6350_data,
+		.size		= ARRAY_SIZE(sm6350_data),
+		.need_llcc_cfg	= true,
+		.reg_offset	= llcc_v1_reg_offset,
+		.edac_reg_offset = &llcc_v1_edac_reg_offset,
+	},
+};
+
+static const struct qcom_llcc_config sm7150_cfg[] = {
+	{
+		.sct_data       = sm7150_data,
+		.size           = ARRAY_SIZE(sm7150_data),
+		.need_llcc_cfg	= true,
+		.reg_offset	= llcc_v1_reg_offset,
+		.edac_reg_offset = &llcc_v1_edac_reg_offset,
+	},
+};
+
+static const struct qcom_llcc_config sm8150_cfg[] = {
+	{
+		.sct_data       = sm8150_data,
+		.size           = ARRAY_SIZE(sm8150_data),
+		.need_llcc_cfg	= true,
+		.reg_offset	= llcc_v1_reg_offset,
+		.edac_reg_offset = &llcc_v1_edac_reg_offset,
+	},
+};
+
+static const struct qcom_llcc_config sm8250_cfg[] = {
+	{
+		.sct_data       = sm8250_data,
+		.size           = ARRAY_SIZE(sm8250_data),
+		.need_llcc_cfg	= true,
+		.reg_offset	= llcc_v1_reg_offset,
+		.edac_reg_offset = &llcc_v1_edac_reg_offset,
+	},
+};
+
+static const struct qcom_llcc_config sm8350_cfg[] = {
+	{
+		.sct_data       = sm8350_data,
+		.size           = ARRAY_SIZE(sm8350_data),
+		.need_llcc_cfg	= true,
+		.reg_offset	= llcc_v1_reg_offset,
+		.edac_reg_offset = &llcc_v1_edac_reg_offset,
+	},
+};
+
+static const struct qcom_llcc_config sm8450_cfg[] = {
+	{
+		.sct_data       = sm8450_data,
+		.size           = ARRAY_SIZE(sm8450_data),
+		.need_llcc_cfg	= true,
+		.reg_offset	= llcc_v2_1_reg_offset,
+		.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
+	},
+};
+
+static const struct qcom_llcc_config sm8550_cfg[] = {
+	{
+		.sct_data       = sm8550_data,
+		.size           = ARRAY_SIZE(sm8550_data),
+		.need_llcc_cfg	= true,
+		.reg_offset	= llcc_v2_1_reg_offset,
+		.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
+	},
+};
+
+static const struct qcom_sct_config sc7180_cfgs = {
+	.llcc_config	= sc7180_cfg,
+	.num_cfgs	= 1,
 };
 
-static const struct qcom_llcc_config sc7280_cfg = {
-	.sct_data	= sc7280_data,
-	.size		= ARRAY_SIZE(sc7280_data),
-	.need_llcc_cfg	= true,
-	.reg_offset	= llcc_v1_reg_offset,
-	.edac_reg_offset = &llcc_v1_edac_reg_offset,
+static const struct qcom_sct_config sc7280_cfgs = {
+	.llcc_config	= sc7280_cfg,
+	.num_cfgs	= 1,
 };
 
-static const struct qcom_llcc_config sc8180x_cfg = {
-	.sct_data	= sc8180x_data,
-	.size		= ARRAY_SIZE(sc8180x_data),
-	.need_llcc_cfg	= true,
-	.reg_offset	= llcc_v1_reg_offset,
-	.edac_reg_offset = &llcc_v1_edac_reg_offset,
+static const struct qcom_sct_config sc8180x_cfgs = {
+	.llcc_config	= sc8180x_cfg,
+	.num_cfgs	= 1,
 };
 
-static const struct qcom_llcc_config sc8280xp_cfg = {
-	.sct_data	= sc8280xp_data,
-	.size		= ARRAY_SIZE(sc8280xp_data),
-	.need_llcc_cfg	= true,
-	.reg_offset	= llcc_v1_reg_offset,
-	.edac_reg_offset = &llcc_v1_edac_reg_offset,
+static const struct qcom_sct_config sc8280xp_cfgs = {
+	.llcc_config	= sc8280xp_cfg,
+	.num_cfgs	= 1,
 };
 
-static const struct qcom_llcc_config sdm845_cfg = {
-	.sct_data	= sdm845_data,
-	.size		= ARRAY_SIZE(sdm845_data),
-	.need_llcc_cfg	= false,
-	.reg_offset	= llcc_v1_reg_offset,
-	.edac_reg_offset = &llcc_v1_edac_reg_offset,
-	.no_edac	= true,
+static const struct qcom_sct_config sdm845_cfgs = {
+	.llcc_config	= sdm845_cfg,
+	.num_cfgs	= 1,
 };
 
-static const struct qcom_llcc_config sm6350_cfg = {
-	.sct_data	= sm6350_data,
-	.size		= ARRAY_SIZE(sm6350_data),
-	.need_llcc_cfg	= true,
-	.reg_offset	= llcc_v1_reg_offset,
-	.edac_reg_offset = &llcc_v1_edac_reg_offset,
+static const struct qcom_sct_config sm6350_cfgs = {
+	.llcc_config	= sm6350_cfg,
+	.num_cfgs	= 1,
 };
 
-static const struct qcom_llcc_config sm7150_cfg = {
-	.sct_data       = sm7150_data,
-	.size           = ARRAY_SIZE(sm7150_data),
-	.need_llcc_cfg	= true,
-	.reg_offset	= llcc_v1_reg_offset,
-	.edac_reg_offset = &llcc_v1_edac_reg_offset,
+static const struct qcom_sct_config sm7150_cfgs = {
+	.llcc_config	= sm7150_cfg,
+	.num_cfgs	= 1,
 };
 
-static const struct qcom_llcc_config sm8150_cfg = {
-	.sct_data       = sm8150_data,
-	.size           = ARRAY_SIZE(sm8150_data),
-	.need_llcc_cfg	= true,
-	.reg_offset	= llcc_v1_reg_offset,
-	.edac_reg_offset = &llcc_v1_edac_reg_offset,
+static const struct qcom_sct_config sm8150_cfgs = {
+	.llcc_config	= sm8150_cfg,
+	.num_cfgs	= 1,
 };
 
-static const struct qcom_llcc_config sm8250_cfg = {
-	.sct_data       = sm8250_data,
-	.size           = ARRAY_SIZE(sm8250_data),
-	.need_llcc_cfg	= true,
-	.reg_offset	= llcc_v1_reg_offset,
-	.edac_reg_offset = &llcc_v1_edac_reg_offset,
+static const struct qcom_sct_config sm8250_cfgs = {
+	.llcc_config	= sm8250_cfg,
+	.num_cfgs	= 1,
 };
 
-static const struct qcom_llcc_config sm8350_cfg = {
-	.sct_data       = sm8350_data,
-	.size           = ARRAY_SIZE(sm8350_data),
-	.need_llcc_cfg	= true,
-	.reg_offset	= llcc_v1_reg_offset,
-	.edac_reg_offset = &llcc_v1_edac_reg_offset,
+static const struct qcom_sct_config sm8350_cfgs = {
+	.llcc_config	= sm8350_cfg,
+	.num_cfgs	= 1,
 };
 
-static const struct qcom_llcc_config sm8450_cfg = {
-	.sct_data       = sm8450_data,
-	.size           = ARRAY_SIZE(sm8450_data),
-	.need_llcc_cfg	= true,
-	.reg_offset	= llcc_v2_1_reg_offset,
-	.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
+static const struct qcom_sct_config sm8450_cfgs = {
+	.llcc_config	= sm8450_cfg,
+	.num_cfgs	= 1,
 };
 
-static const struct qcom_llcc_config sm8550_cfg = {
-	.sct_data       = sm8550_data,
-	.size           = ARRAY_SIZE(sm8550_data),
-	.need_llcc_cfg	= true,
-	.reg_offset	= llcc_v2_1_reg_offset,
-	.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
+static const struct qcom_sct_config sm8550_cfgs = {
+	.llcc_config	= sm8550_cfg,
+	.num_cfgs	= 1,
 };
 
 static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER;
@@ -939,6 +1029,7 @@ static int qcom_llcc_probe(struct platform_device *pdev)
 	struct device *dev = &pdev->dev;
 	int ret, i;
 	struct platform_device *llcc_edac;
+	const struct qcom_sct_config *cfgs;
 	const struct qcom_llcc_config *cfg;
 	const struct llcc_slice_config *llcc_cfg;
 	u32 sz;
@@ -958,7 +1049,8 @@ static int qcom_llcc_probe(struct platform_device *pdev)
 		goto err;
 	}
 
-	cfg = of_device_get_match_data(&pdev->dev);
+	cfgs = of_device_get_match_data(&pdev->dev);
+	cfg = &cfgs->llcc_config[0];
 
 	ret = regmap_read(regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], &num_banks);
 	if (ret)
@@ -1051,18 +1143,18 @@ static int qcom_llcc_probe(struct platform_device *pdev)
 }
 
 static const struct of_device_id qcom_llcc_of_match[] = {
-	{ .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfg },
-	{ .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfg },
-	{ .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfg },
-	{ .compatible = "qcom,sc8280xp-llcc", .data = &sc8280xp_cfg },
-	{ .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfg },
-	{ .compatible = "qcom,sm6350-llcc", .data = &sm6350_cfg },
-	{ .compatible = "qcom,sm7150-llcc", .data = &sm7150_cfg },
-	{ .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfg },
-	{ .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfg },
-	{ .compatible = "qcom,sm8350-llcc", .data = &sm8350_cfg },
-	{ .compatible = "qcom,sm8450-llcc", .data = &sm8450_cfg },
-	{ .compatible = "qcom,sm8550-llcc", .data = &sm8550_cfg },
+	{ .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfgs },
+	{ .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfgs },
+	{ .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfgs },
+	{ .compatible = "qcom,sc8280xp-llcc", .data = &sc8280xp_cfgs },
+	{ .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfgs },
+	{ .compatible = "qcom,sm6350-llcc", .data = &sm6350_cfgs },
+	{ .compatible = "qcom,sm7150-llcc", .data = &sm7150_cfgs },
+	{ .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfgs },
+	{ .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfgs },
+	{ .compatible = "qcom,sm8350-llcc", .data = &sm8350_cfgs },
+	{ .compatible = "qcom,sm8450-llcc", .data = &sm8450_cfgs },
+	{ .compatible = "qcom,sm8550-llcc", .data = &sm8550_cfgs },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, qcom_llcc_of_match);
-- 
2.40.1

[PATCH v5 3/6] nvmem: core: Add stub for nvmem_cell_read_u8

[Komal Bajaj]

This change add the stub function for nvmem_cell_read_u8.
This will be helpful when a driver uses this function and
CONFIG_NVMEM is not enabled.

Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
---
 include/linux/nvmem-consumer.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/include/linux/nvmem-consumer.h b/include/linux/nvmem-consumer.h
index fa030d93b768..5c88635d4c2b 100644
--- a/include/linux/nvmem-consumer.h
+++ b/include/linux/nvmem-consumer.h
@@ -125,6 +125,12 @@ static inline int nvmem_cell_write(struct nvmem_cell *cell,
 	return -EOPNOTSUPP;
 }
 
+static inline int nvmem_cell_read_u8(struct device *dev,
+				     const char *cell_id, u8 *val)
+{
+	return -EOPNOTSUPP;
+}
+
 static inline int nvmem_cell_read_u16(struct device *dev,
 				      const char *cell_id, u16 *val)
 {
-- 
2.40.1

[PATCH v5 4/6] soc: qcom: Add LLCC support for multi channel DDR

[Komal Bajaj]

Add LLCC support for multi channel DDR configuration
based on a feature register.

Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
---
 drivers/soc/qcom/llcc-qcom.c | 26 +++++++++++++++++++++++++-
 1 file changed, 25 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index 321f8d2079f7..1d2b08dfecea 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -12,6 +12,7 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/mutex.h>
+#include <linux/nvmem-consumer.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
 #include <linux/regmap.h>
@@ -997,6 +998,19 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev,
 	return ret;
 }
 
+static int qcom_llcc_get_cfg_index(struct platform_device *pdev, u8 *cfg_index)
+{
+	int ret;
+
+	ret = nvmem_cell_read_u8(&pdev->dev, "multi-chan-ddr", cfg_index);
+	if (ret == -ENOENT || ret == -EOPNOTSUPP) {
+		*cfg_index = 0;
+		return 0;
+	}
+
+	return ret;
+}
+
 static int qcom_llcc_remove(struct platform_device *pdev)
 {
 	/* Set the global pointer to a error code to avoid referencing it */
@@ -1033,6 +1047,7 @@ static int qcom_llcc_probe(struct platform_device *pdev)
 	const struct qcom_llcc_config *cfg;
 	const struct llcc_slice_config *llcc_cfg;
 	u32 sz;
+	u8 cfg_index;
 	u32 version;
 	struct regmap *regmap;
 
@@ -1050,7 +1065,16 @@ static int qcom_llcc_probe(struct platform_device *pdev)
 	}
 
 	cfgs = of_device_get_match_data(&pdev->dev);
-	cfg = &cfgs->llcc_config[0];
+	ret = qcom_llcc_get_cfg_index(pdev, &cfg_index);
+	 if (ret)
+		goto err;
+
+	if (cfg_index >= cfgs->num_cfgs) {
+		ret = -EINVAL;
+		goto err;
+	}
+
+	cfg = &cfgs->llcc_config[cfg_index];
 
 	ret = regmap_read(regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], &num_banks);
 	if (ret)
-- 
2.40.1

[PATCH v5 5/6] soc: qcom: llcc: Updating the macro name

[Komal Bajaj]

Updating macro name for LLCC_DRE to LLCC_ECC as per
the latest specification.

Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
---
 drivers/soc/qcom/llcc-qcom.c       | 2 +-
 include/linux/soc/qcom/llcc-qcom.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index 1d2b08dfecea..228ffb4a8971 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -193,7 +193,7 @@ static const struct llcc_slice_config sc8280xp_data[] = {
 	{ LLCC_MMUHWT,   13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
 	{ LLCC_DISP,     16, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
 	{ LLCC_AUDHW,    22, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
-	{ LLCC_DRE,      26, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
+	{ LLCC_ECC,      26, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
 	{ LLCC_CVP,      28, 512,  3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
 	{ LLCC_APTCM,    30, 1024, 3, 1, 0x0,   0x1, 1, 0, 0, 1, 0, 0 },
 	{ LLCC_WRCACHE,  31, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h
index 93417ba1ead4..1a886666bbb6 100644
--- a/include/linux/soc/qcom/llcc-qcom.h
+++ b/include/linux/soc/qcom/llcc-qcom.h
@@ -30,7 +30,7 @@
 #define LLCC_NPU         23
 #define LLCC_WLHW        24
 #define LLCC_PIMEM       25
-#define LLCC_DRE         26
+#define LLCC_ECC         26
 #define LLCC_CVP         28
 #define LLCC_MODPE       29
 #define LLCC_APTCM       30
-- 
2.40.1

[PATCH v5 6/6] soc: qcom: llcc: Add QDU1000 and QRU1000 LLCC support

[Komal Bajaj]

Add LLCC configuration data for QDU1000 and QRU1000 SoCs.

Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
---
 drivers/soc/qcom/llcc-qcom.c | 67 ++++++++++++++++++++++++++++++++++++
 1 file changed, 67 insertions(+)

diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index 228ffb4a8971..95766260b3b8 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -364,6 +364,36 @@ static const struct llcc_slice_config sm8550_data[] =  {
 	{LLCC_VIDVSP,   28,  256, 4, 1, 0xFFFFFF, 0x0,   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
 };
 
+static const struct llcc_slice_config qdu1000_data_2ch[] = {
+	{ LLCC_MDMHPGRW, 7, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+	{ LLCC_MODHW,    9, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+	{ LLCC_MDMPNG,  21, 256, 0, 1, 0x3,   0x0, 0, 0, 0, 1, 0, 0, 0 },
+	{ LLCC_ECC,     26, 512, 3, 1, 0xffc, 0x0, 0, 0, 0, 0, 1, 0, 0 },
+	{ LLCC_MODPE,   29, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+	{ LLCC_APTCM,   30, 256, 3, 1, 0x0,   0xC, 1, 0, 0, 1, 0, 0, 0 },
+	{ LLCC_WRCACHE, 31, 128, 1, 1, 0x3,   0x0, 0, 0, 0, 0, 1, 0, 0 },
+};
+
+static const struct llcc_slice_config qdu1000_data_4ch[] = {
+	{ LLCC_MDMHPGRW, 7, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+	{ LLCC_MODHW,    9, 512,  1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+	{ LLCC_MDMPNG,  21, 512,  0, 1, 0x3,   0x0, 0, 0, 0, 1, 0, 0, 0 },
+	{ LLCC_ECC,     26, 1024, 3, 1, 0xffc, 0x0, 0, 0, 0, 0, 1, 0, 0 },
+	{ LLCC_MODPE,   29, 512,  1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+	{ LLCC_APTCM,   30, 512,  3, 1, 0x0,   0xC, 1, 0, 0, 1, 0, 0, 0 },
+	{ LLCC_WRCACHE, 31, 256,  1, 1, 0x3,   0x0, 0, 0, 0, 0, 1, 0, 0 },
+};
+
+static const struct llcc_slice_config qdu1000_data_8ch[] = {
+	{ LLCC_MDMHPGRW, 7, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+	{ LLCC_MODHW,    9, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+	{ LLCC_MDMPNG,  21, 1024, 0, 1, 0x3,   0x0, 0, 0, 0, 1, 0, 0, 0 },
+	{ LLCC_ECC,     26, 2048, 3, 1, 0xffc, 0x0, 0, 0, 0, 0, 1, 0, 0 },
+	{ LLCC_MODPE,   29, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+	{ LLCC_APTCM,   30, 1024, 3, 1, 0x0,   0xC, 1, 0, 0, 1, 0, 0, 0 },
+	{ LLCC_WRCACHE, 31, 512,  1, 1, 0x3,   0x0, 0, 0, 0, 0, 1, 0, 0 },
+};
+
 static const struct llcc_edac_reg_offset llcc_v1_edac_reg_offset = {
 	.trp_ecc_error_status0 = 0x20344,
 	.trp_ecc_error_status1 = 0x20348,
@@ -551,6 +581,37 @@ static const struct qcom_llcc_config sm8550_cfg[] = {
 	},
 };
 
+static const struct qcom_llcc_config qdu1000_cfg[] = {
+	{
+		.sct_data       = qdu1000_data_8ch,
+		.size		= ARRAY_SIZE(qdu1000_data_8ch),
+		.need_llcc_cfg	= true,
+		.reg_offset	= llcc_v2_1_reg_offset,
+		.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
+	},
+	{
+		.sct_data       = qdu1000_data_4ch,
+		.size           = ARRAY_SIZE(qdu1000_data_4ch),
+		.need_llcc_cfg  = true,
+		.reg_offset     = llcc_v2_1_reg_offset,
+		.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
+	},
+	{
+		.sct_data       = qdu1000_data_4ch,
+		.size           = ARRAY_SIZE(qdu1000_data_4ch),
+		.need_llcc_cfg  = true,
+		.reg_offset     = llcc_v2_1_reg_offset,
+		.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
+	},
+	{
+		.sct_data       = qdu1000_data_2ch,
+		.size           = ARRAY_SIZE(qdu1000_data_2ch),
+		.need_llcc_cfg  = true,
+		.reg_offset     = llcc_v2_1_reg_offset,
+		.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
+	},
+};
+
 static const struct qcom_sct_config sc7180_cfgs = {
 	.llcc_config	= sc7180_cfg,
 	.num_cfgs	= 1,
@@ -611,6 +672,11 @@ static const struct qcom_sct_config sm8550_cfgs = {
 	.num_cfgs	= 1,
 };
 
+static const struct qcom_sct_config qdu1000_cfgs = {
+	.llcc_config	= qdu1000_cfg,
+	.num_cfgs	= 1,
+};
+
 static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER;
 
 /**
@@ -1167,6 +1233,7 @@ static int qcom_llcc_probe(struct platform_device *pdev)
 }
 
 static const struct of_device_id qcom_llcc_of_match[] = {
+	{ .compatible = "qcom,qdu1000-llcc", .data = &qdu1000_cfgs},
 	{ .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfgs },
 	{ .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfgs },
 	{ .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfgs },
-- 
2.40.1

Re: [PATCH v5 1/6] dt-bindings: cache: qcom,llcc: Add LLCC compatible for QDU1000/QRU1000

[Krzysztof Kozlowski]

On 24/07/2023 10:41, Komal Bajaj wrote:
> Add LLCC compatible for QDU1000/QRU1000 SoCs and add optional
> nvmem-cells and nvmem-cell-names properties to support multiple
> configurations for multi channel DDR.
> 
> Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
> ---


Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH v5 2/6] soc: qcom: llcc: Refactor llcc driver to support multiple configuration

[Mukesh Ojha]

On 7/24/2023 2:11 PM, Komal Bajaj wrote:
> Refactor driver to support multiple configuration for llcc on a target.
> 
> Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
> ---
>   drivers/soc/qcom/llcc-qcom.c | 264 +++++++++++++++++++++++------------
>   1 file changed, 178 insertions(+), 86 deletions(-)
> 
> diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
> index 67c19ed2219a..321f8d2079f7 100644
> --- a/drivers/soc/qcom/llcc-qcom.c
> +++ b/drivers/soc/qcom/llcc-qcom.c
> @@ -127,6 +127,12 @@ struct qcom_llcc_config {
>   	bool no_edac;
>   };
>   
> +struct qcom_sct_config

const ?
  > +	const struct qcom_llcc_config *llcc_config;
> +	int num_cfgs;
> +};
> +
> +
>   enum llcc_reg_offset {
>   	LLCC_COMMON_HW_INFO,
>   	LLCC_COMMON_STATUS0,
> @@ -423,101 +429,185 @@ static const u32 llcc_v2_1_reg_offset[] = {
>   	[LLCC_COMMON_STATUS0]	= 0x0003400c,
>   };
>   
> -static const struct qcom_llcc_config sc7180_cfg = {
> -	.sct_data	= sc7180_data,
> -	.size		= ARRAY_SIZE(sc7180_data),
> -	.need_llcc_cfg	= true,
> -	.reg_offset	= llcc_v1_reg_offset,
> -	.edac_reg_offset = &llcc_v1_edac_reg_offset,
> +static const struct qcom_llcc_config sc7180_cfg[] = {
> +	{
> +		.sct_data	= sc7180_data,
> +		.size		= ARRAY_SIZE(sc7180_data),
> +		.need_llcc_cfg	= true,
> +		.reg_offset	= llcc_v1_reg_offset,
> +		.edac_reg_offset = &llcc_v1_edac_reg_offset,
> +	},
> +};
> +
> +static const struct qcom_llcc_config sc7280_cfg[] = {
> +	{
> +		.sct_data	= sc7280_data,
> +		.size		= ARRAY_SIZE(sc7280_data),
> +		.need_llcc_cfg	= true,
> +		.reg_offset	= llcc_v1_reg_offset,
> +		.edac_reg_offset = &llcc_v1_edac_reg_offset,
> +	},
> +};
> +
> +static const struct qcom_llcc_config sc8180x_cfg[] = {
> +	{
> +		.sct_data	= sc8180x_data,
> +		.size		= ARRAY_SIZE(sc8180x_data),
> +		.need_llcc_cfg	= true,
> +		.reg_offset	= llcc_v1_reg_offset,
> +		.edac_reg_offset = &llcc_v1_edac_reg_offset,
> +	},
> +};
> +
> +static const struct qcom_llcc_config sc8280xp_cfg[] = {
> +	{
> +		.sct_data	= sc8280xp_data,
> +		.size		= ARRAY_SIZE(sc8280xp_data),
> +		.need_llcc_cfg	= true,
> +		.reg_offset	= llcc_v1_reg_offset,
> +		.edac_reg_offset = &llcc_v1_edac_reg_offset,
> +	},
> +};
> +
> +static const struct qcom_llcc_config sdm845_cfg[] = {
> +	{
> +		.sct_data	= sdm845_data,
> +		.size		= ARRAY_SIZE(sdm845_data),
> +		.need_llcc_cfg	= false,
> +		.reg_offset	= llcc_v1_reg_offset,
> +		.edac_reg_offset = &llcc_v1_edac_reg_offset,
> +		.no_edac	= true,
> +	},
> +};
> +
> +static const struct qcom_llcc_config sm6350_cfg[] = {
> +	{
> +		.sct_data	= sm6350_data,
> +		.size		= ARRAY_SIZE(sm6350_data),
> +		.need_llcc_cfg	= true,
> +		.reg_offset	= llcc_v1_reg_offset,
> +		.edac_reg_offset = &llcc_v1_edac_reg_offset,
> +	},
> +};
> +
> +static const struct qcom_llcc_config sm7150_cfg[] = {
> +	{
> +		.sct_data       = sm7150_data,
> +		.size           = ARRAY_SIZE(sm7150_data),
> +		.need_llcc_cfg	= true,
> +		.reg_offset	= llcc_v1_reg_offset,
> +		.edac_reg_offset = &llcc_v1_edac_reg_offset,
> +	},
> +};
> +
> +static const struct qcom_llcc_config sm8150_cfg[] = {
> +	{
> +		.sct_data       = sm8150_data,
> +		.size           = ARRAY_SIZE(sm8150_data),
> +		.need_llcc_cfg	= true,
> +		.reg_offset	= llcc_v1_reg_offset,
> +		.edac_reg_offset = &llcc_v1_edac_reg_offset,
> +	},
> +};
> +
> +static const struct qcom_llcc_config sm8250_cfg[] = {
> +	{
> +		.sct_data       = sm8250_data,
> +		.size           = ARRAY_SIZE(sm8250_data),
> +		.need_llcc_cfg	= true,
> +		.reg_offset	= llcc_v1_reg_offset,
> +		.edac_reg_offset = &llcc_v1_edac_reg_offset,
> +	},
> +};
> +
> +static const struct qcom_llcc_config sm8350_cfg[] = {
> +	{
> +		.sct_data       = sm8350_data,
> +		.size           = ARRAY_SIZE(sm8350_data),
> +		.need_llcc_cfg	= true,
> +		.reg_offset	= llcc_v1_reg_offset,
> +		.edac_reg_offset = &llcc_v1_edac_reg_offset,
> +	},
> +};
> +
> +static const struct qcom_llcc_config sm8450_cfg[] = {
> +	{
> +		.sct_data       = sm8450_data,
> +		.size           = ARRAY_SIZE(sm8450_data),
> +		.need_llcc_cfg	= true,
> +		.reg_offset	= llcc_v2_1_reg_offset,
> +		.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
> +	},
> +};
> +
> +static const struct qcom_llcc_config sm8550_cfg[] = {
> +	{
> +		.sct_data       = sm8550_data,
> +		.size           = ARRAY_SIZE(sm8550_data),
> +		.need_llcc_cfg	= true,
> +		.reg_offset	= llcc_v2_1_reg_offset,
> +		.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
> +	},
> +};
> +
> +static const struct qcom_sct_config sc7180_cfgs = {
> +	.llcc_config	= sc7180_cfg,
> +	.num_cfgs	= 1,
>   };
>   
> -static const struct qcom_llcc_config sc7280_cfg = {
> -	.sct_data	= sc7280_data,
> -	.size		= ARRAY_SIZE(sc7280_data),
> -	.need_llcc_cfg	= true,
> -	.reg_offset	= llcc_v1_reg_offset,
> -	.edac_reg_offset = &llcc_v1_edac_reg_offset,
> +static const struct qcom_sct_config sc7280_cfgs = {
> +	.llcc_config	= sc7280_cfg,
> +	.num_cfgs	= 1,
>   };
>   
> -static const struct qcom_llcc_config sc8180x_cfg = {
> -	.sct_data	= sc8180x_data,
> -	.size		= ARRAY_SIZE(sc8180x_data),
> -	.need_llcc_cfg	= true,
> -	.reg_offset	= llcc_v1_reg_offset,
> -	.edac_reg_offset = &llcc_v1_edac_reg_offset,
> +static const struct qcom_sct_config sc8180x_cfgs = {
> +	.llcc_config	= sc8180x_cfg,
> +	.num_cfgs	= 1,
>   };
>   
> -static const struct qcom_llcc_config sc8280xp_cfg = {
> -	.sct_data	= sc8280xp_data,
> -	.size		= ARRAY_SIZE(sc8280xp_data),
> -	.need_llcc_cfg	= true,
> -	.reg_offset	= llcc_v1_reg_offset,
> -	.edac_reg_offset = &llcc_v1_edac_reg_offset,
> +static const struct qcom_sct_config sc8280xp_cfgs = {
> +	.llcc_config	= sc8280xp_cfg,
> +	.num_cfgs	= 1,
>   };
>   
> -static const struct qcom_llcc_config sdm845_cfg = {
> -	.sct_data	= sdm845_data,
> -	.size		= ARRAY_SIZE(sdm845_data),
> -	.need_llcc_cfg	= false,
> -	.reg_offset	= llcc_v1_reg_offset,
> -	.edac_reg_offset = &llcc_v1_edac_reg_offset,
> -	.no_edac	= true,
> +static const struct qcom_sct_config sdm845_cfgs = {
> +	.llcc_config	= sdm845_cfg,
> +	.num_cfgs	= 1,
>   };
>   
> -static const struct qcom_llcc_config sm6350_cfg = {
> -	.sct_data	= sm6350_data,
> -	.size		= ARRAY_SIZE(sm6350_data),
> -	.need_llcc_cfg	= true,
> -	.reg_offset	= llcc_v1_reg_offset,
> -	.edac_reg_offset = &llcc_v1_edac_reg_offset,
> +static const struct qcom_sct_config sm6350_cfgs = {
> +	.llcc_config	= sm6350_cfg,
> +	.num_cfgs	= 1,
>   };
>   
> -static const struct qcom_llcc_config sm7150_cfg = {
> -	.sct_data       = sm7150_data,
> -	.size           = ARRAY_SIZE(sm7150_data),
> -	.need_llcc_cfg	= true,
> -	.reg_offset	= llcc_v1_reg_offset,
> -	.edac_reg_offset = &llcc_v1_edac_reg_offset,
> +static const struct qcom_sct_config sm7150_cfgs = {
> +	.llcc_config	= sm7150_cfg,
> +	.num_cfgs	= 1,
>   };
>   
> -static const struct qcom_llcc_config sm8150_cfg = {
> -	.sct_data       = sm8150_data,
> -	.size           = ARRAY_SIZE(sm8150_data),
> -	.need_llcc_cfg	= true,
> -	.reg_offset	= llcc_v1_reg_offset,
> -	.edac_reg_offset = &llcc_v1_edac_reg_offset,
> +static const struct qcom_sct_config sm8150_cfgs = {
> +	.llcc_config	= sm8150_cfg,
> +	.num_cfgs	= 1,
>   };
>   
> -static const struct qcom_llcc_config sm8250_cfg = {
> -	.sct_data       = sm8250_data,
> -	.size           = ARRAY_SIZE(sm8250_data),
> -	.need_llcc_cfg	= true,
> -	.reg_offset	= llcc_v1_reg_offset,
> -	.edac_reg_offset = &llcc_v1_edac_reg_offset,
> +static const struct qcom_sct_config sm8250_cfgs = {
> +	.llcc_config	= sm8250_cfg,
> +	.num_cfgs	= 1,
>   };
>   
> -static const struct qcom_llcc_config sm8350_cfg = {
> -	.sct_data       = sm8350_data,
> -	.size           = ARRAY_SIZE(sm8350_data),
> -	.need_llcc_cfg	= true,
> -	.reg_offset	= llcc_v1_reg_offset,
> -	.edac_reg_offset = &llcc_v1_edac_reg_offset,
> +static const struct qcom_sct_config sm8350_cfgs = {
> +	.llcc_config	= sm8350_cfg,
> +	.num_cfgs	= 1,
>   };
>   
> -static const struct qcom_llcc_config sm8450_cfg = {
> -	.sct_data       = sm8450_data,
> -	.size           = ARRAY_SIZE(sm8450_data),
> -	.need_llcc_cfg	= true,
> -	.reg_offset	= llcc_v2_1_reg_offset,
> -	.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
> +static const struct qcom_sct_config sm8450_cfgs = {
> +	.llcc_config	= sm8450_cfg,
> +	.num_cfgs	= 1,
>   };
>   
> -static const struct qcom_llcc_config sm8550_cfg = {
> -	.sct_data       = sm8550_data,
> -	.size           = ARRAY_SIZE(sm8550_data),
> -	.need_llcc_cfg	= true,
> -	.reg_offset	= llcc_v2_1_reg_offset,
> -	.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
> +static const struct qcom_sct_config sm8550_cfgs = {
> +	.llcc_config	= sm8550_cfg,
> +	.num_cfgs	= 1,

num prefix itself take care of singular/plural, num_config would do
good.


>   };
>   
>   static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER;
> @@ -939,6 +1029,7 @@ static int qcom_llcc_probe(struct platform_device *pdev)
>   	struct device *dev = &pdev->dev;
>   	int ret, i;
>   	struct platform_device *llcc_edac;
> +	const struct qcom_sct_config *cfgs;
>   	const struct qcom_llcc_config *cfg;
>   	const struct llcc_slice_config *llcc_cfg;
>   	u32 sz;
> @@ -958,7 +1049,8 @@ static int qcom_llcc_probe(struct platform_device *pdev)
>   		goto err;
>   	}
>   
> -	cfg = of_device_get_match_data(&pdev->dev);
> +	cfgs = of_device_get_match_data(&pdev->dev);
> +	cfg = &cfgs->llcc_config[0];

Hardcoding without check ?

#define DEFAULT_NUM_CFG    1

if (cfgs->num_cfgs != DEFAULT_NUM_CFG)
      ret = -EINVAL;
      goto err;

cfg = &cfgs->llcc_config[DEFAULT_NUM_CFG - 1];

I would let others comment as well..


-Mukesh

>   
>   	ret = regmap_read(regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], &num_banks);
>   	if (ret)
> @@ -1051,18 +1143,18 @@ static int qcom_llcc_probe(struct platform_device *pdev)
>   }
>   
>   static const struct of_device_id qcom_llcc_of_match[] = {
> -	{ .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfg },
> -	{ .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfg },
> -	{ .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfg },
> -	{ .compatible = "qcom,sc8280xp-llcc", .data = &sc8280xp_cfg },
> -	{ .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfg },
> -	{ .compatible = "qcom,sm6350-llcc", .data = &sm6350_cfg },
> -	{ .compatible = "qcom,sm7150-llcc", .data = &sm7150_cfg },
> -	{ .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfg },
> -	{ .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfg },
> -	{ .compatible = "qcom,sm8350-llcc", .data = &sm8350_cfg },
> -	{ .compatible = "qcom,sm8450-llcc", .data = &sm8450_cfg },
> -	{ .compatible = "qcom,sm8550-llcc", .data = &sm8550_cfg },
> +	{ .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfgs },
> +	{ .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfgs },
> +	{ .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfgs },
> +	{ .compatible = "qcom,sc8280xp-llcc", .data = &sc8280xp_cfgs },
> +	{ .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfgs },
> +	{ .compatible = "qcom,sm6350-llcc", .data = &sm6350_cfgs },
> +	{ .compatible = "qcom,sm7150-llcc", .data = &sm7150_cfgs },
> +	{ .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfgs },
> +	{ .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfgs },
> +	{ .compatible = "qcom,sm8350-llcc", .data = &sm8350_cfgs },
> +	{ .compatible = "qcom,sm8450-llcc", .data = &sm8450_cfgs },
> +	{ .compatible = "qcom,sm8550-llcc", .data = &sm8550_cfgs },
>   	{ }
>   };
>   MODULE_DEVICE_TABLE(of, qcom_llcc_of_match);

Re: [PATCH v5 3/6] nvmem: core: Add stub for nvmem_cell_read_u8

[Mukesh Ojha]

On 7/24/2023 2:11 PM, Komal Bajaj wrote:
> This change add the stub function for nvmem_cell_read_u8.

"Add the stub nvmem_cell_read_u8() function for drivers running with
CONFIG_NVMEM disabled"

-Mukesh

> This will be helpful when a driver uses this function and



-Mukesh

> CONFIG_NVMEM is not enabled.
> 
> Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
> ---
>   include/linux/nvmem-consumer.h | 6 ++++++
>   1 file changed, 6 insertions(+)
> 
> diff --git a/include/linux/nvmem-consumer.h b/include/linux/nvmem-consumer.h
> index fa030d93b768..5c88635d4c2b 100644
> --- a/include/linux/nvmem-consumer.h
> +++ b/include/linux/nvmem-consumer.h
> @@ -125,6 +125,12 @@ static inline int nvmem_cell_write(struct nvmem_cell *cell,
>   	return -EOPNOTSUPP;
>   }
>   
> +static inline int nvmem_cell_read_u8(struct device *dev,
> +				     const char *cell_id, u8 *val)
> +{
> +	return -EOPNOTSUPP;
> +}
> +
>   static inline int nvmem_cell_read_u16(struct device *dev,
>   				      const char *cell_id, u16 *val)
>   {

Re: [PATCH v5 4/6] soc: qcom: Add LLCC support for multi channel DDR

[Mukesh Ojha]

On 7/24/2023 2:11 PM, Komal Bajaj wrote:
> Add LLCC support for multi channel DDR configuration
> based on a feature register.
> 
> Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
> ---
>   drivers/soc/qcom/llcc-qcom.c | 26 +++++++++++++++++++++++++-
>   1 file changed, 25 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
> index 321f8d2079f7..1d2b08dfecea 100644
> --- a/drivers/soc/qcom/llcc-qcom.c
> +++ b/drivers/soc/qcom/llcc-qcom.c
> @@ -12,6 +12,7 @@
>   #include <linux/kernel.h>
>   #include <linux/module.h>
>   #include <linux/mutex.h>
> +#include <linux/nvmem-consumer.h>
>   #include <linux/of.h>
>   #include <linux/of_device.h>
>   #include <linux/regmap.h>
> @@ -997,6 +998,19 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev,
>   	return ret;
>   }
>   
> +static int qcom_llcc_get_cfg_index(struct platform_device *pdev, u8 *cfg_index)
> +{
> +	int ret;
> +
> +	ret = nvmem_cell_read_u8(&pdev->dev, "multi-chan-ddr", cfg_index);
> +	if (ret == -ENOENT || ret == -EOPNOTSUPP) {
> +		*cfg_index = 0;
> +		return 0;
> +	}
> +
> +	return ret;
> +}
> +
>   static int qcom_llcc_remove(struct platform_device *pdev)
>   {
>   	/* Set the global pointer to a error code to avoid referencing it */
> @@ -1033,6 +1047,7 @@ static int qcom_llcc_probe(struct platform_device *pdev)
>   	const struct qcom_llcc_config *cfg;
>   	const struct llcc_slice_config *llcc_cfg;
>   	u32 sz;
> +	u8 cfg_index;
>   	u32 version;
>   	struct regmap *regmap;
>   
> @@ -1050,7 +1065,16 @@ static int qcom_llcc_probe(struct platform_device *pdev)
>   	}
>   
>   	cfgs = of_device_get_match_data(&pdev->dev);
> -	cfg = &cfgs->llcc_config[0];
> +	ret = qcom_llcc_get_cfg_index(pdev, &cfg_index);
> +	 if (ret)

alignment.. ?

-Mukesh

> +		goto err;
> +
> +	if (cfg_index >= cfgs->num_cfgs) {
> +		ret = -EINVAL;
> +		goto err;
> +	}
> +
> +	cfg = &cfgs->llcc_config[cfg_index];
>   
>   	ret = regmap_read(regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], &num_banks);
>   	if (ret)

Re: [PATCH v5 5/6] soc: qcom: llcc: Updating the macro name

[Mukesh Ojha]

On 7/24/2023 2:11 PM, Komal Bajaj wrote:
> Updating macro name for LLCC_DRE to LLCC_ECC as per
> the latest specification.
> 
> Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>

Reviewed-by: Mukesh Ojha <quic_mojha@quicinc.com>

-Mukesh

> ---
>   drivers/soc/qcom/llcc-qcom.c       | 2 +-
>   include/linux/soc/qcom/llcc-qcom.h | 2 +-
>   2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
> index 1d2b08dfecea..228ffb4a8971 100644
> --- a/drivers/soc/qcom/llcc-qcom.c
> +++ b/drivers/soc/qcom/llcc-qcom.c
> @@ -193,7 +193,7 @@ static const struct llcc_slice_config sc8280xp_data[] = {
>   	{ LLCC_MMUHWT,   13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
>   	{ LLCC_DISP,     16, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
>   	{ LLCC_AUDHW,    22, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
> -	{ LLCC_DRE,      26, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
> +	{ LLCC_ECC,      26, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
>   	{ LLCC_CVP,      28, 512,  3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
>   	{ LLCC_APTCM,    30, 1024, 3, 1, 0x0,   0x1, 1, 0, 0, 1, 0, 0 },
>   	{ LLCC_WRCACHE,  31, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
> diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h
> index 93417ba1ead4..1a886666bbb6 100644
> --- a/include/linux/soc/qcom/llcc-qcom.h
> +++ b/include/linux/soc/qcom/llcc-qcom.h
> @@ -30,7 +30,7 @@
>   #define LLCC_NPU         23
>   #define LLCC_WLHW        24
>   #define LLCC_PIMEM       25
> -#define LLCC_DRE         26
> +#define LLCC_ECC         26
>   #define LLCC_CVP         28
>   #define LLCC_MODPE       29
>   #define LLCC_APTCM       30

Re: [PATCH v5 6/6] soc: qcom: llcc: Add QDU1000 and QRU1000 LLCC support

[Mukesh Ojha]

On 7/24/2023 2:11 PM, Komal Bajaj wrote:
> Add LLCC configuration data for QDU1000 and QRU1000 SoCs.
> 
> Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
> ---
>   drivers/soc/qcom/llcc-qcom.c | 67 ++++++++++++++++++++++++++++++++++++
>   1 file changed, 67 insertions(+)
> 
> diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
> index 228ffb4a8971..95766260b3b8 100644
> --- a/drivers/soc/qcom/llcc-qcom.c
> +++ b/drivers/soc/qcom/llcc-qcom.c
> @@ -364,6 +364,36 @@ static const struct llcc_slice_config sm8550_data[] =  {
>   	{LLCC_VIDVSP,   28,  256, 4, 1, 0xFFFFFF, 0x0,   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
>   };
>   
> +static const struct llcc_slice_config qdu1000_data_2ch[] = {
> +	{ LLCC_MDMHPGRW, 7, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
> +	{ LLCC_MODHW,    9, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
> +	{ LLCC_MDMPNG,  21, 256, 0, 1, 0x3,   0x0, 0, 0, 0, 1, 0, 0, 0 },
> +	{ LLCC_ECC,     26, 512, 3, 1, 0xffc, 0x0, 0, 0, 0, 0, 1, 0, 0 },
> +	{ LLCC_MODPE,   29, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
> +	{ LLCC_APTCM,   30, 256, 3, 1, 0x0,   0xC, 1, 0, 0, 1, 0, 0, 0 },
> +	{ LLCC_WRCACHE, 31, 128, 1, 1, 0x3,   0x0, 0, 0, 0, 0, 1, 0, 0 },
> +};
> +
> +static const struct llcc_slice_config qdu1000_data_4ch[] = {
> +	{ LLCC_MDMHPGRW, 7, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
> +	{ LLCC_MODHW,    9, 512,  1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
> +	{ LLCC_MDMPNG,  21, 512,  0, 1, 0x3,   0x0, 0, 0, 0, 1, 0, 0, 0 },
> +	{ LLCC_ECC,     26, 1024, 3, 1, 0xffc, 0x0, 0, 0, 0, 0, 1, 0, 0 },
> +	{ LLCC_MODPE,   29, 512,  1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
> +	{ LLCC_APTCM,   30, 512,  3, 1, 0x0,   0xC, 1, 0, 0, 1, 0, 0, 0 },
> +	{ LLCC_WRCACHE, 31, 256,  1, 1, 0x3,   0x0, 0, 0, 0, 0, 1, 0, 0 },
> +};
> +
> +static const struct llcc_slice_config qdu1000_data_8ch[] = {
> +	{ LLCC_MDMHPGRW, 7, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
> +	{ LLCC_MODHW,    9, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
> +	{ LLCC_MDMPNG,  21, 1024, 0, 1, 0x3,   0x0, 0, 0, 0, 1, 0, 0, 0 },
> +	{ LLCC_ECC,     26, 2048, 3, 1, 0xffc, 0x0, 0, 0, 0, 0, 1, 0, 0 },
> +	{ LLCC_MODPE,   29, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
> +	{ LLCC_APTCM,   30, 1024, 3, 1, 0x0,   0xC, 1, 0, 0, 1, 0, 0, 0 },
> +	{ LLCC_WRCACHE, 31, 512,  1, 1, 0x3,   0x0, 0, 0, 0, 0, 1, 0, 0 },
> +};
> +
>   static const struct llcc_edac_reg_offset llcc_v1_edac_reg_offset = {
>   	.trp_ecc_error_status0 = 0x20344,
>   	.trp_ecc_error_status1 = 0x20348,
> @@ -551,6 +581,37 @@ static const struct qcom_llcc_config sm8550_cfg[] = {
>   	},
>   };
>   
> +static const struct qcom_llcc_config qdu1000_cfg[] = {
> +	{
> +		.sct_data       = qdu1000_data_8ch,
> +		.size		= ARRAY_SIZE(qdu1000_data_8ch),
> +		.need_llcc_cfg	= true,
> +		.reg_offset	= llcc_v2_1_reg_offset,
> +		.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
> +	},
> +	{
> +		.sct_data       = qdu1000_data_4ch,
> +		.size           = ARRAY_SIZE(qdu1000_data_4ch),
> +		.need_llcc_cfg  = true,
> +		.reg_offset     = llcc_v2_1_reg_offset,
> +		.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
> +	},
> +	{
> +		.sct_data       = qdu1000_data_4ch,
> +		.size           = ARRAY_SIZE(qdu1000_data_4ch),
> +		.need_llcc_cfg  = true,
> +		.reg_offset     = llcc_v2_1_reg_offset,
> +		.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
> +	},
> +	{
> +		.sct_data       = qdu1000_data_2ch,
> +		.size           = ARRAY_SIZE(qdu1000_data_2ch),
> +		.need_llcc_cfg  = true,
> +		.reg_offset     = llcc_v2_1_reg_offset,
> +		.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
> +	},
> +};
> +
>   static const struct qcom_sct_config sc7180_cfgs = {
>   	.llcc_config	= sc7180_cfg,
>   	.num_cfgs	= 1,
> @@ -611,6 +672,11 @@ static const struct qcom_sct_config sm8550_cfgs = {
>   	.num_cfgs	= 1,
>   };
>   
> +static const struct qcom_sct_config qdu1000_cfgs = {
> +	.llcc_config	= qdu1000_cfg,
> +	.num_cfgs	= 1,


Should not this be 4 ?

-Mukesh

> +};
> +
>   static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER;
>   
>   /**
> @@ -1167,6 +1233,7 @@ static int qcom_llcc_probe(struct platform_device *pdev)
>   }
>   
>   static const struct of_device_id qcom_llcc_of_match[] = {
> +	{ .compatible = "qcom,qdu1000-llcc", .data = &qdu1000_cfgs},
>   	{ .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfgs },
>   	{ .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfgs },
>   	{ .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfgs },

Re: [PATCH v5 5/6] soc: qcom: llcc: Updating the macro name

[Konrad Dybcio]

On 24.07.2023 10:41, Komal Bajaj wrote:
> Updating macro name for LLCC_DRE to LLCC_ECC as per
> the latest specification.
> 
> Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
> ---
Nit: "updating" -> "update", as the action is complete.

On top of that, please wrap your commit messages at +/- 72 characters,
not 50.

Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
>  drivers/soc/qcom/llcc-qcom.c       | 2 +-
>  include/linux/soc/qcom/llcc-qcom.h | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
> index 1d2b08dfecea..228ffb4a8971 100644
> --- a/drivers/soc/qcom/llcc-qcom.c
> +++ b/drivers/soc/qcom/llcc-qcom.c
> @@ -193,7 +193,7 @@ static const struct llcc_slice_config sc8280xp_data[] = {
>  	{ LLCC_MMUHWT,   13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
>  	{ LLCC_DISP,     16, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
>  	{ LLCC_AUDHW,    22, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
> -	{ LLCC_DRE,      26, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
> +	{ LLCC_ECC,      26, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
>  	{ LLCC_CVP,      28, 512,  3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
>  	{ LLCC_APTCM,    30, 1024, 3, 1, 0x0,   0x1, 1, 0, 0, 1, 0, 0 },
>  	{ LLCC_WRCACHE,  31, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
> diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h
> index 93417ba1ead4..1a886666bbb6 100644
> --- a/include/linux/soc/qcom/llcc-qcom.h
> +++ b/include/linux/soc/qcom/llcc-qcom.h
> @@ -30,7 +30,7 @@
>  #define LLCC_NPU         23
>  #define LLCC_WLHW        24
>  #define LLCC_PIMEM       25
> -#define LLCC_DRE         26
> +#define LLCC_ECC         26
>  #define LLCC_CVP         28
>  #define LLCC_MODPE       29
>  #define LLCC_APTCM       30

Re: [PATCH v5 6/6] soc: qcom: llcc: Add QDU1000 and QRU1000 LLCC support

[Konrad Dybcio]

On 24.07.2023 10:41, Komal Bajaj wrote:
> Add LLCC configuration data for QDU1000 and QRU1000 SoCs.
> 
> Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
> ---
>  drivers/soc/qcom/llcc-qcom.c | 67 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 67 insertions(+)
> 
> diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
> index 228ffb4a8971..95766260b3b8 100644
> --- a/drivers/soc/qcom/llcc-qcom.c
> +++ b/drivers/soc/qcom/llcc-qcom.c
> @@ -364,6 +364,36 @@ static const struct llcc_slice_config sm8550_data[] =  {
>  	{LLCC_VIDVSP,   28,  256, 4, 1, 0xFFFFFF, 0x0,   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
>  };
>  
> +static const struct llcc_slice_config qdu1000_data_2ch[] = {
> +	{ LLCC_MDMHPGRW, 7, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
> +	{ LLCC_MODHW,    9, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
> +	{ LLCC_MDMPNG,  21, 256, 0, 1, 0x3,   0x0, 0, 0, 0, 1, 0, 0, 0 },
> +	{ LLCC_ECC,     26, 512, 3, 1, 0xffc, 0x0, 0, 0, 0, 0, 1, 0, 0 },
> +	{ LLCC_MODPE,   29, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
> +	{ LLCC_APTCM,   30, 256, 3, 1, 0x0,   0xC, 1, 0, 0, 1, 0, 0, 0 },
Please use lowercase hex.

Konrad

Re: [PATCH v5 6/6] soc: qcom: llcc: Add QDU1000 and QRU1000 LLCC support

[Konrad Dybcio]

On 24.07.2023 14:45, Mukesh Ojha wrote:
> 
> 
> On 7/24/2023 2:11 PM, Komal Bajaj wrote:
>> Add LLCC configuration data for QDU1000 and QRU1000 SoCs.
>>
>> Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
>> ---
[...]

>>   static const struct qcom_sct_config sc7180_cfgs = {
>>       .llcc_config    = sc7180_cfg,
>>       .num_cfgs    = 1,
>> @@ -611,6 +672,11 @@ static const struct qcom_sct_config sm8550_cfgs = {
>>       .num_cfgs    = 1,
>>   };
>>   +static const struct qcom_sct_config qdu1000_cfgs = {
>> +    .llcc_config    = qdu1000_cfg,
>> +    .num_cfgs    = 1,
> 
> 
> Should not this be 4 ?
Even better, use ARRAY_SIZE(name_of_arr)

Konrad

Re: [PATCH v5 2/6] soc: qcom: llcc: Refactor llcc driver to support multiple configuration

[Krzysztof Kozlowski]

On 24/07/2023 14:28, Mukesh Ojha wrote:
> On 7/24/2023 2:11 PM, Komal Bajaj wrote:
>> Refactor driver to support multiple configuration for llcc on a target.
>>
>> Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
>> ---
>>   drivers/soc/qcom/llcc-qcom.c | 264 +++++++++++++++++++++++------------
>>   1 file changed, 178 insertions(+), 86 deletions(-)
>>
>> diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
>> index 67c19ed2219a..321f8d2079f7 100644
>> --- a/drivers/soc/qcom/llcc-qcom.c
>> +++ b/drivers/soc/qcom/llcc-qcom.c
>> @@ -127,6 +127,12 @@ struct qcom_llcc_config {
>>   	bool no_edac;
>>   };
>>   
>> +struct qcom_sct_config
> 
> const ?

What (and how) should be const above?

Best regards,
Krzysztof

Re: [PATCH v5 2/6] soc: qcom: llcc: Refactor llcc driver to support multiple configuration

[Mukesh Ojha]

On 7/24/2023 5:58 PM, Mukesh Ojha wrote:
> 
> 
> On 7/24/2023 2:11 PM, Komal Bajaj wrote:
>> Refactor driver to support multiple configuration for llcc on a target.
>>
>> Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
>> ---
>>   drivers/soc/qcom/llcc-qcom.c | 264 +++++++++++++++++++++++------------
>>   1 file changed, 178 insertions(+), 86 deletions(-)
>>
>> diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
>> index 67c19ed2219a..321f8d2079f7 100644
>> --- a/drivers/soc/qcom/llcc-qcom.c
>> +++ b/drivers/soc/qcom/llcc-qcom.c
>> @@ -127,6 +127,12 @@ struct qcom_llcc_config {
>>       bool no_edac;
>>   };
>> +struct qcom_sct_config
> 
> const ?

Please ignore this comment, it looks like, I wrote something and forgot
to remove..


-Mukesh

>   > +    const struct qcom_llcc_config *llcc_config;
>> +    int num_cfgs;
>> +};
>> +
>> +
>>   enum llcc_reg_offset {
>>       LLCC_COMMON_HW_INFO,
>>       LLCC_COMMON_STATUS0,
>> @@ -423,101 +429,185 @@ static const u32 llcc_v2_1_reg_offset[] = {
>>       [LLCC_COMMON_STATUS0]    = 0x0003400c,
>>   };
>> -static const struct qcom_llcc_config sc7180_cfg = {
>> -    .sct_data    = sc7180_data,
>> -    .size        = ARRAY_SIZE(sc7180_data),
>> -    .need_llcc_cfg    = true,
>> -    .reg_offset    = llcc_v1_reg_offset,
>> -    .edac_reg_offset = &llcc_v1_edac_reg_offset,
>> +static const struct qcom_llcc_config sc7180_cfg[] = {
>> +    {
>> +        .sct_data    = sc7180_data,
>> +        .size        = ARRAY_SIZE(sc7180_data),
>> +        .need_llcc_cfg    = true,
>> +        .reg_offset    = llcc_v1_reg_offset,
>> +        .edac_reg_offset = &llcc_v1_edac_reg_offset,
>> +    },
>> +};
>> +
>> +static const struct qcom_llcc_config sc7280_cfg[] = {
>> +    {
>> +        .sct_data    = sc7280_data,
>> +        .size        = ARRAY_SIZE(sc7280_data),
>> +        .need_llcc_cfg    = true,
>> +        .reg_offset    = llcc_v1_reg_offset,
>> +        .edac_reg_offset = &llcc_v1_edac_reg_offset,
>> +    },
>> +};
>> +
>> +static const struct qcom_llcc_config sc8180x_cfg[] = {
>> +    {
>> +        .sct_data    = sc8180x_data,
>> +        .size        = ARRAY_SIZE(sc8180x_data),
>> +        .need_llcc_cfg    = true,
>> +        .reg_offset    = llcc_v1_reg_offset,
>> +        .edac_reg_offset = &llcc_v1_edac_reg_offset,
>> +    },
>> +};
>> +
>> +static const struct qcom_llcc_config sc8280xp_cfg[] = {
>> +    {
>> +        .sct_data    = sc8280xp_data,
>> +        .size        = ARRAY_SIZE(sc8280xp_data),
>> +        .need_llcc_cfg    = true,
>> +        .reg_offset    = llcc_v1_reg_offset,
>> +        .edac_reg_offset = &llcc_v1_edac_reg_offset,
>> +    },
>> +};
>> +
>> +static const struct qcom_llcc_config sdm845_cfg[] = {
>> +    {
>> +        .sct_data    = sdm845_data,
>> +        .size        = ARRAY_SIZE(sdm845_data),
>> +        .need_llcc_cfg    = false,
>> +        .reg_offset    = llcc_v1_reg_offset,
>> +        .edac_reg_offset = &llcc_v1_edac_reg_offset,
>> +        .no_edac    = true,
>> +    },
>> +};
>> +
>> +static const struct qcom_llcc_config sm6350_cfg[] = {
>> +    {
>> +        .sct_data    = sm6350_data,
>> +        .size        = ARRAY_SIZE(sm6350_data),
>> +        .need_llcc_cfg    = true,
>> +        .reg_offset    = llcc_v1_reg_offset,
>> +        .edac_reg_offset = &llcc_v1_edac_reg_offset,
>> +    },
>> +};
>> +
>> +static const struct qcom_llcc_config sm7150_cfg[] = {
>> +    {
>> +        .sct_data       = sm7150_data,
>> +        .size           = ARRAY_SIZE(sm7150_data),
>> +        .need_llcc_cfg    = true,
>> +        .reg_offset    = llcc_v1_reg_offset,
>> +        .edac_reg_offset = &llcc_v1_edac_reg_offset,
>> +    },
>> +};
>> +
>> +static const struct qcom_llcc_config sm8150_cfg[] = {
>> +    {
>> +        .sct_data       = sm8150_data,
>> +        .size           = ARRAY_SIZE(sm8150_data),
>> +        .need_llcc_cfg    = true,
>> +        .reg_offset    = llcc_v1_reg_offset,
>> +        .edac_reg_offset = &llcc_v1_edac_reg_offset,
>> +    },
>> +};
>> +
>> +static const struct qcom_llcc_config sm8250_cfg[] = {
>> +    {
>> +        .sct_data       = sm8250_data,
>> +        .size           = ARRAY_SIZE(sm8250_data),
>> +        .need_llcc_cfg    = true,
>> +        .reg_offset    = llcc_v1_reg_offset,
>> +        .edac_reg_offset = &llcc_v1_edac_reg_offset,
>> +    },
>> +};
>> +
>> +static const struct qcom_llcc_config sm8350_cfg[] = {
>> +    {
>> +        .sct_data       = sm8350_data,
>> +        .size           = ARRAY_SIZE(sm8350_data),
>> +        .need_llcc_cfg    = true,
>> +        .reg_offset    = llcc_v1_reg_offset,
>> +        .edac_reg_offset = &llcc_v1_edac_reg_offset,
>> +    },
>> +};
>> +
>> +static const struct qcom_llcc_config sm8450_cfg[] = {
>> +    {
>> +        .sct_data       = sm8450_data,
>> +        .size           = ARRAY_SIZE(sm8450_data),
>> +        .need_llcc_cfg    = true,
>> +        .reg_offset    = llcc_v2_1_reg_offset,
>> +        .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
>> +    },
>> +};
>> +
>> +static const struct qcom_llcc_config sm8550_cfg[] = {
>> +    {
>> +        .sct_data       = sm8550_data,
>> +        .size           = ARRAY_SIZE(sm8550_data),
>> +        .need_llcc_cfg    = true,
>> +        .reg_offset    = llcc_v2_1_reg_offset,
>> +        .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
>> +    },
>> +};
>> +
>> +static const struct qcom_sct_config sc7180_cfgs = {
>> +    .llcc_config    = sc7180_cfg,
>> +    .num_cfgs    = 1,
>>   };
>> -static const struct qcom_llcc_config sc7280_cfg = {
>> -    .sct_data    = sc7280_data,
>> -    .size        = ARRAY_SIZE(sc7280_data),
>> -    .need_llcc_cfg    = true,
>> -    .reg_offset    = llcc_v1_reg_offset,
>> -    .edac_reg_offset = &llcc_v1_edac_reg_offset,
>> +static const struct qcom_sct_config sc7280_cfgs = {
>> +    .llcc_config    = sc7280_cfg,
>> +    .num_cfgs    = 1,
>>   };
>> -static const struct qcom_llcc_config sc8180x_cfg = {
>> -    .sct_data    = sc8180x_data,
>> -    .size        = ARRAY_SIZE(sc8180x_data),
>> -    .need_llcc_cfg    = true,
>> -    .reg_offset    = llcc_v1_reg_offset,
>> -    .edac_reg_offset = &llcc_v1_edac_reg_offset,
>> +static const struct qcom_sct_config sc8180x_cfgs = {
>> +    .llcc_config    = sc8180x_cfg,
>> +    .num_cfgs    = 1,
>>   };
>> -static const struct qcom_llcc_config sc8280xp_cfg = {
>> -    .sct_data    = sc8280xp_data,
>> -    .size        = ARRAY_SIZE(sc8280xp_data),
>> -    .need_llcc_cfg    = true,
>> -    .reg_offset    = llcc_v1_reg_offset,
>> -    .edac_reg_offset = &llcc_v1_edac_reg_offset,
>> +static const struct qcom_sct_config sc8280xp_cfgs = {
>> +    .llcc_config    = sc8280xp_cfg,
>> +    .num_cfgs    = 1,
>>   };
>> -static const struct qcom_llcc_config sdm845_cfg = {
>> -    .sct_data    = sdm845_data,
>> -    .size        = ARRAY_SIZE(sdm845_data),
>> -    .need_llcc_cfg    = false,
>> -    .reg_offset    = llcc_v1_reg_offset,
>> -    .edac_reg_offset = &llcc_v1_edac_reg_offset,
>> -    .no_edac    = true,
>> +static const struct qcom_sct_config sdm845_cfgs = {
>> +    .llcc_config    = sdm845_cfg,
>> +    .num_cfgs    = 1,
>>   };
>> -static const struct qcom_llcc_config sm6350_cfg = {
>> -    .sct_data    = sm6350_data,
>> -    .size        = ARRAY_SIZE(sm6350_data),
>> -    .need_llcc_cfg    = true,
>> -    .reg_offset    = llcc_v1_reg_offset,
>> -    .edac_reg_offset = &llcc_v1_edac_reg_offset,
>> +static const struct qcom_sct_config sm6350_cfgs = {
>> +    .llcc_config    = sm6350_cfg,
>> +    .num_cfgs    = 1,
>>   };
>> -static const struct qcom_llcc_config sm7150_cfg = {
>> -    .sct_data       = sm7150_data,
>> -    .size           = ARRAY_SIZE(sm7150_data),
>> -    .need_llcc_cfg    = true,
>> -    .reg_offset    = llcc_v1_reg_offset,
>> -    .edac_reg_offset = &llcc_v1_edac_reg_offset,
>> +static const struct qcom_sct_config sm7150_cfgs = {
>> +    .llcc_config    = sm7150_cfg,
>> +    .num_cfgs    = 1,
>>   };
>> -static const struct qcom_llcc_config sm8150_cfg = {
>> -    .sct_data       = sm8150_data,
>> -    .size           = ARRAY_SIZE(sm8150_data),
>> -    .need_llcc_cfg    = true,
>> -    .reg_offset    = llcc_v1_reg_offset,
>> -    .edac_reg_offset = &llcc_v1_edac_reg_offset,
>> +static const struct qcom_sct_config sm8150_cfgs = {
>> +    .llcc_config    = sm8150_cfg,
>> +    .num_cfgs    = 1,
>>   };
>> -static const struct qcom_llcc_config sm8250_cfg = {
>> -    .sct_data       = sm8250_data,
>> -    .size           = ARRAY_SIZE(sm8250_data),
>> -    .need_llcc_cfg    = true,
>> -    .reg_offset    = llcc_v1_reg_offset,
>> -    .edac_reg_offset = &llcc_v1_edac_reg_offset,
>> +static const struct qcom_sct_config sm8250_cfgs = {
>> +    .llcc_config    = sm8250_cfg,
>> +    .num_cfgs    = 1,
>>   };
>> -static const struct qcom_llcc_config sm8350_cfg = {
>> -    .sct_data       = sm8350_data,
>> -    .size           = ARRAY_SIZE(sm8350_data),
>> -    .need_llcc_cfg    = true,
>> -    .reg_offset    = llcc_v1_reg_offset,
>> -    .edac_reg_offset = &llcc_v1_edac_reg_offset,
>> +static const struct qcom_sct_config sm8350_cfgs = {
>> +    .llcc_config    = sm8350_cfg,
>> +    .num_cfgs    = 1,
>>   };
>> -static const struct qcom_llcc_config sm8450_cfg = {
>> -    .sct_data       = sm8450_data,
>> -    .size           = ARRAY_SIZE(sm8450_data),
>> -    .need_llcc_cfg    = true,
>> -    .reg_offset    = llcc_v2_1_reg_offset,
>> -    .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
>> +static const struct qcom_sct_config sm8450_cfgs = {
>> +    .llcc_config    = sm8450_cfg,
>> +    .num_cfgs    = 1,
>>   };
>> -static const struct qcom_llcc_config sm8550_cfg = {
>> -    .sct_data       = sm8550_data,
>> -    .size           = ARRAY_SIZE(sm8550_data),
>> -    .need_llcc_cfg    = true,
>> -    .reg_offset    = llcc_v2_1_reg_offset,
>> -    .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
>> +static const struct qcom_sct_config sm8550_cfgs = {
>> +    .llcc_config    = sm8550_cfg,
>> +    .num_cfgs    = 1,
> 
> num prefix itself take care of singular/plural, num_config would do
> good.
> 
> 
>>   };
>>   static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER;
>> @@ -939,6 +1029,7 @@ static int qcom_llcc_probe(struct platform_device 
>> *pdev)
>>       struct device *dev = &pdev->dev;
>>       int ret, i;
>>       struct platform_device *llcc_edac;
>> +    const struct qcom_sct_config *cfgs;
>>       const struct qcom_llcc_config *cfg;
>>       const struct llcc_slice_config *llcc_cfg;
>>       u32 sz;
>> @@ -958,7 +1049,8 @@ static int qcom_llcc_probe(struct platform_device 
>> *pdev)
>>           goto err;
>>       }
>> -    cfg = of_device_get_match_data(&pdev->dev);
>> +    cfgs = of_device_get_match_data(&pdev->dev);
>> +    cfg = &cfgs->llcc_config[0];
> 
> Hardcoding without check ?
> 
> #define DEFAULT_NUM_CFG    1
> 
> if (cfgs->num_cfgs != DEFAULT_NUM_CFG)
>       ret = -EINVAL;
>       goto err;
> 
> cfg = &cfgs->llcc_config[DEFAULT_NUM_CFG - 1];
> 
> I would let others comment as well..
> 
> 
> -Mukesh
> 
>>       ret = regmap_read(regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], 
>> &num_banks);
>>       if (ret)
>> @@ -1051,18 +1143,18 @@ static int qcom_llcc_probe(struct 
>> platform_device *pdev)
>>   }
>>   static const struct of_device_id qcom_llcc_of_match[] = {
>> -    { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfg },
>> -    { .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfg },
>> -    { .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfg },
>> -    { .compatible = "qcom,sc8280xp-llcc", .data = &sc8280xp_cfg },
>> -    { .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfg },
>> -    { .compatible = "qcom,sm6350-llcc", .data = &sm6350_cfg },
>> -    { .compatible = "qcom,sm7150-llcc", .data = &sm7150_cfg },
>> -    { .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfg },
>> -    { .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfg },
>> -    { .compatible = "qcom,sm8350-llcc", .data = &sm8350_cfg },
>> -    { .compatible = "qcom,sm8450-llcc", .data = &sm8450_cfg },
>> -    { .compatible = "qcom,sm8550-llcc", .data = &sm8550_cfg },
>> +    { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfgs },
>> +    { .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfgs },
>> +    { .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfgs },
>> +    { .compatible = "qcom,sc8280xp-llcc", .data = &sc8280xp_cfgs },
>> +    { .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfgs },
>> +    { .compatible = "qcom,sm6350-llcc", .data = &sm6350_cfgs },
>> +    { .compatible = "qcom,sm7150-llcc", .data = &sm7150_cfgs },
>> +    { .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfgs },
>> +    { .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfgs },
>> +    { .compatible = "qcom,sm8350-llcc", .data = &sm8350_cfgs },
>> +    { .compatible = "qcom,sm8450-llcc", .data = &sm8450_cfgs },
>> +    { .compatible = "qcom,sm8550-llcc", .data = &sm8550_cfgs },
>>       { }
>>   };
>>   MODULE_DEVICE_TABLE(of, qcom_llcc_of_match);

Re: [PATCH v5 2/6] soc: qcom: llcc: Refactor llcc driver to support multiple configuration

[Mukesh Ojha]

On 7/24/2023 6:56 PM, Krzysztof Kozlowski wrote:
> On 24/07/2023 14:28, Mukesh Ojha wrote:
>> On 7/24/2023 2:11 PM, Komal Bajaj wrote:
>>> Refactor driver to support multiple configuration for llcc on a target.
>>>
>>> Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
>>> ---
>>>    drivers/soc/qcom/llcc-qcom.c | 264 +++++++++++++++++++++++------------
>>>    1 file changed, 178 insertions(+), 86 deletions(-)
>>>
>>> diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
>>> index 67c19ed2219a..321f8d2079f7 100644
>>> --- a/drivers/soc/qcom/llcc-qcom.c
>>> +++ b/drivers/soc/qcom/llcc-qcom.c
>>> @@ -127,6 +127,12 @@ struct qcom_llcc_config {
>>>    	bool no_edac;
>>>    };
>>>    
>>> +struct qcom_sct_config
>>
>> const ?
> 
> What (and how) should be const above?

  left over, thanks for catching..

-Mukesh

> 
> Best regards,
> Krzysztof
> 

Re: [PATCH v5 2/6] soc: qcom: llcc: Refactor llcc driver to support multiple configuration

[Komal Bajaj]

On 7/24/2023 9:41 PM, Mukesh Ojha wrote:
>
>
> On 7/24/2023 5:58 PM, Mukesh Ojha wrote:
>>
>>
>> On 7/24/2023 2:11 PM, Komal Bajaj wrote:
>>> Refactor driver to support multiple configuration for llcc on a target.
>>>
>>> Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
>>> ---
>>>   drivers/soc/qcom/llcc-qcom.c | 264 
>>> +++++++++++++++++++++++------------
>>>   1 file changed, 178 insertions(+), 86 deletions(-)
>>>
>>> diff --git a/drivers/soc/qcom/llcc-qcom.c 
>>> b/drivers/soc/qcom/llcc-qcom.c
>>> index 67c19ed2219a..321f8d2079f7 100644
>>> --- a/drivers/soc/qcom/llcc-qcom.c
>>> +++ b/drivers/soc/qcom/llcc-qcom.c
>>> @@ -127,6 +127,12 @@ struct qcom_llcc_config {
>>>       bool no_edac;
>>>   };
>>> +struct qcom_sct_config
>>
>> const ?
>
> Please ignore this comment, it looks like, I wrote something and forgot
> to remove..
>
>
> -Mukesh
>
>>   > +    const struct qcom_llcc_config *llcc_config;
>>> +    int num_cfgs;
>>> +};
>>> +
>>> +
>>>   enum llcc_reg_offset {
>>>       LLCC_COMMON_HW_INFO,
>>>       LLCC_COMMON_STATUS0,
>>> @@ -423,101 +429,185 @@ static const u32 llcc_v2_1_reg_offset[] = {
>>>       [LLCC_COMMON_STATUS0]    = 0x0003400c,
>>>   };
>>> -static const struct qcom_llcc_config sc7180_cfg = {
>>> -    .sct_data    = sc7180_data,
>>> -    .size        = ARRAY_SIZE(sc7180_data),
>>> -    .need_llcc_cfg    = true,
>>> -    .reg_offset    = llcc_v1_reg_offset,
>>> -    .edac_reg_offset = &llcc_v1_edac_reg_offset,
>>> +static const struct qcom_llcc_config sc7180_cfg[] = {
>>> +    {
>>> +        .sct_data    = sc7180_data,
>>> +        .size        = ARRAY_SIZE(sc7180_data),
>>> +        .need_llcc_cfg    = true,
>>> +        .reg_offset    = llcc_v1_reg_offset,
>>> +        .edac_reg_offset = &llcc_v1_edac_reg_offset,
>>> +    },
>>> +};
>>> +
>>> +static const struct qcom_llcc_config sc7280_cfg[] = {
>>> +    {
>>> +        .sct_data    = sc7280_data,
>>> +        .size        = ARRAY_SIZE(sc7280_data),
>>> +        .need_llcc_cfg    = true,
>>> +        .reg_offset    = llcc_v1_reg_offset,
>>> +        .edac_reg_offset = &llcc_v1_edac_reg_offset,
>>> +    },
>>> +};
>>> +
>>> +static const struct qcom_llcc_config sc8180x_cfg[] = {
>>> +    {
>>> +        .sct_data    = sc8180x_data,
>>> +        .size        = ARRAY_SIZE(sc8180x_data),
>>> +        .need_llcc_cfg    = true,
>>> +        .reg_offset    = llcc_v1_reg_offset,
>>> +        .edac_reg_offset = &llcc_v1_edac_reg_offset,
>>> +    },
>>> +};
>>> +
>>> +static const struct qcom_llcc_config sc8280xp_cfg[] = {
>>> +    {
>>> +        .sct_data    = sc8280xp_data,
>>> +        .size        = ARRAY_SIZE(sc8280xp_data),
>>> +        .need_llcc_cfg    = true,
>>> +        .reg_offset    = llcc_v1_reg_offset,
>>> +        .edac_reg_offset = &llcc_v1_edac_reg_offset,
>>> +    },
>>> +};
>>> +
>>> +static const struct qcom_llcc_config sdm845_cfg[] = {
>>> +    {
>>> +        .sct_data    = sdm845_data,
>>> +        .size        = ARRAY_SIZE(sdm845_data),
>>> +        .need_llcc_cfg    = false,
>>> +        .reg_offset    = llcc_v1_reg_offset,
>>> +        .edac_reg_offset = &llcc_v1_edac_reg_offset,
>>> +        .no_edac    = true,
>>> +    },
>>> +};
>>> +
>>> +static const struct qcom_llcc_config sm6350_cfg[] = {
>>> +    {
>>> +        .sct_data    = sm6350_data,
>>> +        .size        = ARRAY_SIZE(sm6350_data),
>>> +        .need_llcc_cfg    = true,
>>> +        .reg_offset    = llcc_v1_reg_offset,
>>> +        .edac_reg_offset = &llcc_v1_edac_reg_offset,
>>> +    },
>>> +};
>>> +
>>> +static const struct qcom_llcc_config sm7150_cfg[] = {
>>> +    {
>>> +        .sct_data       = sm7150_data,
>>> +        .size           = ARRAY_SIZE(sm7150_data),
>>> +        .need_llcc_cfg    = true,
>>> +        .reg_offset    = llcc_v1_reg_offset,
>>> +        .edac_reg_offset = &llcc_v1_edac_reg_offset,
>>> +    },
>>> +};
>>> +
>>> +static const struct qcom_llcc_config sm8150_cfg[] = {
>>> +    {
>>> +        .sct_data       = sm8150_data,
>>> +        .size           = ARRAY_SIZE(sm8150_data),
>>> +        .need_llcc_cfg    = true,
>>> +        .reg_offset    = llcc_v1_reg_offset,
>>> +        .edac_reg_offset = &llcc_v1_edac_reg_offset,
>>> +    },
>>> +};
>>> +
>>> +static const struct qcom_llcc_config sm8250_cfg[] = {
>>> +    {
>>> +        .sct_data       = sm8250_data,
>>> +        .size           = ARRAY_SIZE(sm8250_data),
>>> +        .need_llcc_cfg    = true,
>>> +        .reg_offset    = llcc_v1_reg_offset,
>>> +        .edac_reg_offset = &llcc_v1_edac_reg_offset,
>>> +    },
>>> +};
>>> +
>>> +static const struct qcom_llcc_config sm8350_cfg[] = {
>>> +    {
>>> +        .sct_data       = sm8350_data,
>>> +        .size           = ARRAY_SIZE(sm8350_data),
>>> +        .need_llcc_cfg    = true,
>>> +        .reg_offset    = llcc_v1_reg_offset,
>>> +        .edac_reg_offset = &llcc_v1_edac_reg_offset,
>>> +    },
>>> +};
>>> +
>>> +static const struct qcom_llcc_config sm8450_cfg[] = {
>>> +    {
>>> +        .sct_data       = sm8450_data,
>>> +        .size           = ARRAY_SIZE(sm8450_data),
>>> +        .need_llcc_cfg    = true,
>>> +        .reg_offset    = llcc_v2_1_reg_offset,
>>> +        .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
>>> +    },
>>> +};
>>> +
>>> +static const struct qcom_llcc_config sm8550_cfg[] = {
>>> +    {
>>> +        .sct_data       = sm8550_data,
>>> +        .size           = ARRAY_SIZE(sm8550_data),
>>> +        .need_llcc_cfg    = true,
>>> +        .reg_offset    = llcc_v2_1_reg_offset,
>>> +        .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
>>> +    },
>>> +};
>>> +
>>> +static const struct qcom_sct_config sc7180_cfgs = {
>>> +    .llcc_config    = sc7180_cfg,
>>> +    .num_cfgs    = 1,
>>>   };
>>> -static const struct qcom_llcc_config sc7280_cfg = {
>>> -    .sct_data    = sc7280_data,
>>> -    .size        = ARRAY_SIZE(sc7280_data),
>>> -    .need_llcc_cfg    = true,
>>> -    .reg_offset    = llcc_v1_reg_offset,
>>> -    .edac_reg_offset = &llcc_v1_edac_reg_offset,
>>> +static const struct qcom_sct_config sc7280_cfgs = {
>>> +    .llcc_config    = sc7280_cfg,
>>> +    .num_cfgs    = 1,
>>>   };
>>> -static const struct qcom_llcc_config sc8180x_cfg = {
>>> -    .sct_data    = sc8180x_data,
>>> -    .size        = ARRAY_SIZE(sc8180x_data),
>>> -    .need_llcc_cfg    = true,
>>> -    .reg_offset    = llcc_v1_reg_offset,
>>> -    .edac_reg_offset = &llcc_v1_edac_reg_offset,
>>> +static const struct qcom_sct_config sc8180x_cfgs = {
>>> +    .llcc_config    = sc8180x_cfg,
>>> +    .num_cfgs    = 1,
>>>   };
>>> -static const struct qcom_llcc_config sc8280xp_cfg = {
>>> -    .sct_data    = sc8280xp_data,
>>> -    .size        = ARRAY_SIZE(sc8280xp_data),
>>> -    .need_llcc_cfg    = true,
>>> -    .reg_offset    = llcc_v1_reg_offset,
>>> -    .edac_reg_offset = &llcc_v1_edac_reg_offset,
>>> +static const struct qcom_sct_config sc8280xp_cfgs = {
>>> +    .llcc_config    = sc8280xp_cfg,
>>> +    .num_cfgs    = 1,
>>>   };
>>> -static const struct qcom_llcc_config sdm845_cfg = {
>>> -    .sct_data    = sdm845_data,
>>> -    .size        = ARRAY_SIZE(sdm845_data),
>>> -    .need_llcc_cfg    = false,
>>> -    .reg_offset    = llcc_v1_reg_offset,
>>> -    .edac_reg_offset = &llcc_v1_edac_reg_offset,
>>> -    .no_edac    = true,
>>> +static const struct qcom_sct_config sdm845_cfgs = {
>>> +    .llcc_config    = sdm845_cfg,
>>> +    .num_cfgs    = 1,
>>>   };
>>> -static const struct qcom_llcc_config sm6350_cfg = {
>>> -    .sct_data    = sm6350_data,
>>> -    .size        = ARRAY_SIZE(sm6350_data),
>>> -    .need_llcc_cfg    = true,
>>> -    .reg_offset    = llcc_v1_reg_offset,
>>> -    .edac_reg_offset = &llcc_v1_edac_reg_offset,
>>> +static const struct qcom_sct_config sm6350_cfgs = {
>>> +    .llcc_config    = sm6350_cfg,
>>> +    .num_cfgs    = 1,
>>>   };
>>> -static const struct qcom_llcc_config sm7150_cfg = {
>>> -    .sct_data       = sm7150_data,
>>> -    .size           = ARRAY_SIZE(sm7150_data),
>>> -    .need_llcc_cfg    = true,
>>> -    .reg_offset    = llcc_v1_reg_offset,
>>> -    .edac_reg_offset = &llcc_v1_edac_reg_offset,
>>> +static const struct qcom_sct_config sm7150_cfgs = {
>>> +    .llcc_config    = sm7150_cfg,
>>> +    .num_cfgs    = 1,
>>>   };
>>> -static const struct qcom_llcc_config sm8150_cfg = {
>>> -    .sct_data       = sm8150_data,
>>> -    .size           = ARRAY_SIZE(sm8150_data),
>>> -    .need_llcc_cfg    = true,
>>> -    .reg_offset    = llcc_v1_reg_offset,
>>> -    .edac_reg_offset = &llcc_v1_edac_reg_offset,
>>> +static const struct qcom_sct_config sm8150_cfgs = {
>>> +    .llcc_config    = sm8150_cfg,
>>> +    .num_cfgs    = 1,
>>>   };
>>> -static const struct qcom_llcc_config sm8250_cfg = {
>>> -    .sct_data       = sm8250_data,
>>> -    .size           = ARRAY_SIZE(sm8250_data),
>>> -    .need_llcc_cfg    = true,
>>> -    .reg_offset    = llcc_v1_reg_offset,
>>> -    .edac_reg_offset = &llcc_v1_edac_reg_offset,
>>> +static const struct qcom_sct_config sm8250_cfgs = {
>>> +    .llcc_config    = sm8250_cfg,
>>> +    .num_cfgs    = 1,
>>>   };
>>> -static const struct qcom_llcc_config sm8350_cfg = {
>>> -    .sct_data       = sm8350_data,
>>> -    .size           = ARRAY_SIZE(sm8350_data),
>>> -    .need_llcc_cfg    = true,
>>> -    .reg_offset    = llcc_v1_reg_offset,
>>> -    .edac_reg_offset = &llcc_v1_edac_reg_offset,
>>> +static const struct qcom_sct_config sm8350_cfgs = {
>>> +    .llcc_config    = sm8350_cfg,
>>> +    .num_cfgs    = 1,
>>>   };
>>> -static const struct qcom_llcc_config sm8450_cfg = {
>>> -    .sct_data       = sm8450_data,
>>> -    .size           = ARRAY_SIZE(sm8450_data),
>>> -    .need_llcc_cfg    = true,
>>> -    .reg_offset    = llcc_v2_1_reg_offset,
>>> -    .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
>>> +static const struct qcom_sct_config sm8450_cfgs = {
>>> +    .llcc_config    = sm8450_cfg,
>>> +    .num_cfgs    = 1,
>>>   };
>>> -static const struct qcom_llcc_config sm8550_cfg = {
>>> -    .sct_data       = sm8550_data,
>>> -    .size           = ARRAY_SIZE(sm8550_data),
>>> -    .need_llcc_cfg    = true,
>>> -    .reg_offset    = llcc_v2_1_reg_offset,
>>> -    .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
>>> +static const struct qcom_sct_config sm8550_cfgs = {
>>> +    .llcc_config    = sm8550_cfg,
>>> +    .num_cfgs    = 1,
>>
>> num prefix itself take care of singular/plural, num_config would do
>> good.
>>
>>
>>>   };
>>>   static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER;
>>> @@ -939,6 +1029,7 @@ static int qcom_llcc_probe(struct 
>>> platform_device *pdev)
>>>       struct device *dev = &pdev->dev;
>>>       int ret, i;
>>>       struct platform_device *llcc_edac;
>>> +    const struct qcom_sct_config *cfgs;
>>>       const struct qcom_llcc_config *cfg;
>>>       const struct llcc_slice_config *llcc_cfg;
>>>       u32 sz;
>>> @@ -958,7 +1049,8 @@ static int qcom_llcc_probe(struct 
>>> platform_device *pdev)
>>>           goto err;
>>>       }
>>> -    cfg = of_device_get_match_data(&pdev->dev);
>>> +    cfgs = of_device_get_match_data(&pdev->dev);
>>> +    cfg = &cfgs->llcc_config[0];
>>
>> Hardcoding without check ?
>>
>> #define DEFAULT_NUM_CFG    1
>>
>> if (cfgs->num_cfgs != DEFAULT_NUM_CFG)
>>       ret = -EINVAL;
>>       goto err;
>>
>> cfg = &cfgs->llcc_config[DEFAULT_NUM_CFG - 1];
>>
>> I would let others comment as well..

Okay, will add a check for default llcc configuration.

Thanks
Komal

>>
>>
>> -Mukesh
>>
>>>       ret = regmap_read(regmap, 
>>> cfg->reg_offset[LLCC_COMMON_STATUS0], &num_banks);
>>>       if (ret)
>>> @@ -1051,18 +1143,18 @@ static int qcom_llcc_probe(struct 
>>> platform_device *pdev)
>>>   }
>>>   static const struct of_device_id qcom_llcc_of_match[] = {
>>> -    { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfg },
>>> -    { .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfg },
>>> -    { .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfg },
>>> -    { .compatible = "qcom,sc8280xp-llcc", .data = &sc8280xp_cfg },
>>> -    { .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfg },
>>> -    { .compatible = "qcom,sm6350-llcc", .data = &sm6350_cfg },
>>> -    { .compatible = "qcom,sm7150-llcc", .data = &sm7150_cfg },
>>> -    { .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfg },
>>> -    { .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfg },
>>> -    { .compatible = "qcom,sm8350-llcc", .data = &sm8350_cfg },
>>> -    { .compatible = "qcom,sm8450-llcc", .data = &sm8450_cfg },
>>> -    { .compatible = "qcom,sm8550-llcc", .data = &sm8550_cfg },
>>> +    { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfgs },
>>> +    { .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfgs },
>>> +    { .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfgs },
>>> +    { .compatible = "qcom,sc8280xp-llcc", .data = &sc8280xp_cfgs },
>>> +    { .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfgs },
>>> +    { .compatible = "qcom,sm6350-llcc", .data = &sm6350_cfgs },
>>> +    { .compatible = "qcom,sm7150-llcc", .data = &sm7150_cfgs },
>>> +    { .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfgs },
>>> +    { .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfgs },
>>> +    { .compatible = "qcom,sm8350-llcc", .data = &sm8350_cfgs },
>>> +    { .compatible = "qcom,sm8450-llcc", .data = &sm8450_cfgs },
>>> +    { .compatible = "qcom,sm8550-llcc", .data = &sm8550_cfgs },
>>>       { }
>>>   };
>>>   MODULE_DEVICE_TABLE(of, qcom_llcc_of_match);

Re: [PATCH v5 3/6] nvmem: core: Add stub for nvmem_cell_read_u8

[Komal Bajaj]

On 7/24/2023 6:06 PM, Mukesh Ojha wrote:
>
>
> On 7/24/2023 2:11 PM, Komal Bajaj wrote:
>> This change add the stub function for nvmem_cell_read_u8.
>
> "Add the stub nvmem_cell_read_u8() function for drivers running with
> CONFIG_NVMEM disabled"

Okay, will update the commit description.

Thanks
Komal

>
> -Mukesh
>
>> This will be helpful when a driver uses this function and
>
>
>
> -Mukesh
>
>> CONFIG_NVMEM is not enabled.
>>
>> Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
>> ---
>>   include/linux/nvmem-consumer.h | 6 ++++++
>>   1 file changed, 6 insertions(+)
>>
>> diff --git a/include/linux/nvmem-consumer.h 
>> b/include/linux/nvmem-consumer.h
>> index fa030d93b768..5c88635d4c2b 100644
>> --- a/include/linux/nvmem-consumer.h
>> +++ b/include/linux/nvmem-consumer.h
>> @@ -125,6 +125,12 @@ static inline int nvmem_cell_write(struct 
>> nvmem_cell *cell,
>>       return -EOPNOTSUPP;
>>   }
>>   +static inline int nvmem_cell_read_u8(struct device *dev,
>> +                     const char *cell_id, u8 *val)
>> +{
>> +    return -EOPNOTSUPP;
>> +}
>> +
>>   static inline int nvmem_cell_read_u16(struct device *dev,
>>                         const char *cell_id, u16 *val)
>>   {

Re: [PATCH v5 4/6] soc: qcom: Add LLCC support for multi channel DDR

[Komal Bajaj]

On 7/24/2023 6:10 PM, Mukesh Ojha wrote:
>
>
> On 7/24/2023 2:11 PM, Komal Bajaj wrote:
>> Add LLCC support for multi channel DDR configuration
>> based on a feature register.
>>
>> Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
>> ---
>>   drivers/soc/qcom/llcc-qcom.c | 26 +++++++++++++++++++++++++-
>>   1 file changed, 25 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
>> index 321f8d2079f7..1d2b08dfecea 100644
>> --- a/drivers/soc/qcom/llcc-qcom.c
>> +++ b/drivers/soc/qcom/llcc-qcom.c
>> @@ -12,6 +12,7 @@
>>   #include <linux/kernel.h>
>>   #include <linux/module.h>
>>   #include <linux/mutex.h>
>> +#include <linux/nvmem-consumer.h>
>>   #include <linux/of.h>
>>   #include <linux/of_device.h>
>>   #include <linux/regmap.h>
>> @@ -997,6 +998,19 @@ static int qcom_llcc_cfg_program(struct 
>> platform_device *pdev,
>>       return ret;
>>   }
>>   +static int qcom_llcc_get_cfg_index(struct platform_device *pdev, 
>> u8 *cfg_index)
>> +{
>> +    int ret;
>> +
>> +    ret = nvmem_cell_read_u8(&pdev->dev, "multi-chan-ddr", cfg_index);
>> +    if (ret == -ENOENT || ret == -EOPNOTSUPP) {
>> +        *cfg_index = 0;
>> +        return 0;
>> +    }
>> +
>> +    return ret;
>> +}
>> +
>>   static int qcom_llcc_remove(struct platform_device *pdev)
>>   {
>>       /* Set the global pointer to a error code to avoid referencing 
>> it */
>> @@ -1033,6 +1047,7 @@ static int qcom_llcc_probe(struct 
>> platform_device *pdev)
>>       const struct qcom_llcc_config *cfg;
>>       const struct llcc_slice_config *llcc_cfg;
>>       u32 sz;
>> +    u8 cfg_index;
>>       u32 version;
>>       struct regmap *regmap;
>>   @@ -1050,7 +1065,16 @@ static int qcom_llcc_probe(struct 
>> platform_device *pdev)
>>       }
>>         cfgs = of_device_get_match_data(&pdev->dev);
>> -    cfg = &cfgs->llcc_config[0];
>> +    ret = qcom_llcc_get_cfg_index(pdev, &cfg_index);
>> +     if (ret)
>
> alignment.. ?

Thanks for pointing it out. Will fix it in the next series.

Thanks
Komal

>
> -Mukesh
>
>> +        goto err;
>> +
>> +    if (cfg_index >= cfgs->num_cfgs) {
>> +        ret = -EINVAL;
>> +        goto err;
>> +    }
>> +
>> +    cfg = &cfgs->llcc_config[cfg_index];
>>         ret = regmap_read(regmap, 
>> cfg->reg_offset[LLCC_COMMON_STATUS0], &num_banks);
>>       if (ret)

Re: [PATCH v5 5/6] soc: qcom: llcc: Updating the macro name

[Komal Bajaj]

On 7/24/2023 6:18 PM, Konrad Dybcio wrote:
> On 24.07.2023 10:41, Komal Bajaj wrote:
>> Updating macro name for LLCC_DRE to LLCC_ECC as per
>> the latest specification.
>>
>> Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
>> ---
> Nit: "updating" -> "update", as the action is complete.
>
> On top of that, please wrap your commit messages at +/- 72 characters,
> not 50.

Sure, will update the commit message.

Thanks
Komal

>
> Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>
> Konrad
>>   drivers/soc/qcom/llcc-qcom.c       | 2 +-
>>   include/linux/soc/qcom/llcc-qcom.h | 2 +-
>>   2 files changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
>> index 1d2b08dfecea..228ffb4a8971 100644
>> --- a/drivers/soc/qcom/llcc-qcom.c
>> +++ b/drivers/soc/qcom/llcc-qcom.c
>> @@ -193,7 +193,7 @@ static const struct llcc_slice_config sc8280xp_data[] = {
>>   	{ LLCC_MMUHWT,   13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
>>   	{ LLCC_DISP,     16, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
>>   	{ LLCC_AUDHW,    22, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
>> -	{ LLCC_DRE,      26, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
>> +	{ LLCC_ECC,      26, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
>>   	{ LLCC_CVP,      28, 512,  3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
>>   	{ LLCC_APTCM,    30, 1024, 3, 1, 0x0,   0x1, 1, 0, 0, 1, 0, 0 },
>>   	{ LLCC_WRCACHE,  31, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
>> diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h
>> index 93417ba1ead4..1a886666bbb6 100644
>> --- a/include/linux/soc/qcom/llcc-qcom.h
>> +++ b/include/linux/soc/qcom/llcc-qcom.h
>> @@ -30,7 +30,7 @@
>>   #define LLCC_NPU         23
>>   #define LLCC_WLHW        24
>>   #define LLCC_PIMEM       25
>> -#define LLCC_DRE         26
>> +#define LLCC_ECC         26
>>   #define LLCC_CVP         28
>>   #define LLCC_MODPE       29
>>   #define LLCC_APTCM       30

Re: [PATCH v5 6/6] soc: qcom: llcc: Add QDU1000 and QRU1000 LLCC support

[Komal Bajaj]

On 7/24/2023 6:15 PM, Mukesh Ojha wrote:
>
>
> On 7/24/2023 2:11 PM, Komal Bajaj wrote:
>> Add LLCC configuration data for QDU1000 and QRU1000 SoCs.
>>
>> Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
>> ---
>>   drivers/soc/qcom/llcc-qcom.c | 67 ++++++++++++++++++++++++++++++++++++
>>   1 file changed, 67 insertions(+)
>>
>> diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
>> index 228ffb4a8971..95766260b3b8 100644
>> --- a/drivers/soc/qcom/llcc-qcom.c
>> +++ b/drivers/soc/qcom/llcc-qcom.c
>> @@ -364,6 +364,36 @@ static const struct llcc_slice_config 
>> sm8550_data[] =  {
>>       {LLCC_VIDVSP,   28,  256, 4, 1, 0xFFFFFF, 0x0,   0, 0, 0, 0, 0, 
>> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
>>   };
>>   +static const struct llcc_slice_config qdu1000_data_2ch[] = {
>> +    { LLCC_MDMHPGRW, 7, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
>> +    { LLCC_MODHW,    9, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
>> +    { LLCC_MDMPNG,  21, 256, 0, 1, 0x3,   0x0, 0, 0, 0, 1, 0, 0, 0 },
>> +    { LLCC_ECC,     26, 512, 3, 1, 0xffc, 0x0, 0, 0, 0, 0, 1, 0, 0 },
>> +    { LLCC_MODPE,   29, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
>> +    { LLCC_APTCM,   30, 256, 3, 1, 0x0,   0xC, 1, 0, 0, 1, 0, 0, 0 },
>> +    { LLCC_WRCACHE, 31, 128, 1, 1, 0x3,   0x0, 0, 0, 0, 0, 1, 0, 0 },
>> +};
>> +
>> +static const struct llcc_slice_config qdu1000_data_4ch[] = {
>> +    { LLCC_MDMHPGRW, 7, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
>> +    { LLCC_MODHW,    9, 512,  1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
>> +    { LLCC_MDMPNG,  21, 512,  0, 1, 0x3,   0x0, 0, 0, 0, 1, 0, 0, 0 },
>> +    { LLCC_ECC,     26, 1024, 3, 1, 0xffc, 0x0, 0, 0, 0, 0, 1, 0, 0 },
>> +    { LLCC_MODPE,   29, 512,  1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
>> +    { LLCC_APTCM,   30, 512,  3, 1, 0x0,   0xC, 1, 0, 0, 1, 0, 0, 0 },
>> +    { LLCC_WRCACHE, 31, 256,  1, 1, 0x3,   0x0, 0, 0, 0, 0, 1, 0, 0 },
>> +};
>> +
>> +static const struct llcc_slice_config qdu1000_data_8ch[] = {
>> +    { LLCC_MDMHPGRW, 7, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
>> +    { LLCC_MODHW,    9, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
>> +    { LLCC_MDMPNG,  21, 1024, 0, 1, 0x3,   0x0, 0, 0, 0, 1, 0, 0, 0 },
>> +    { LLCC_ECC,     26, 2048, 3, 1, 0xffc, 0x0, 0, 0, 0, 0, 1, 0, 0 },
>> +    { LLCC_MODPE,   29, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
>> +    { LLCC_APTCM,   30, 1024, 3, 1, 0x0,   0xC, 1, 0, 0, 1, 0, 0, 0 },
>> +    { LLCC_WRCACHE, 31, 512,  1, 1, 0x3,   0x0, 0, 0, 0, 0, 1, 0, 0 },
>> +};
>> +
>>   static const struct llcc_edac_reg_offset llcc_v1_edac_reg_offset = {
>>       .trp_ecc_error_status0 = 0x20344,
>>       .trp_ecc_error_status1 = 0x20348,
>> @@ -551,6 +581,37 @@ static const struct qcom_llcc_config 
>> sm8550_cfg[] = {
>>       },
>>   };
>>   +static const struct qcom_llcc_config qdu1000_cfg[] = {
>> +    {
>> +        .sct_data       = qdu1000_data_8ch,
>> +        .size        = ARRAY_SIZE(qdu1000_data_8ch),
>> +        .need_llcc_cfg    = true,
>> +        .reg_offset    = llcc_v2_1_reg_offset,
>> +        .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
>> +    },
>> +    {
>> +        .sct_data       = qdu1000_data_4ch,
>> +        .size           = ARRAY_SIZE(qdu1000_data_4ch),
>> +        .need_llcc_cfg  = true,
>> +        .reg_offset     = llcc_v2_1_reg_offset,
>> +        .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
>> +    },
>> +    {
>> +        .sct_data       = qdu1000_data_4ch,
>> +        .size           = ARRAY_SIZE(qdu1000_data_4ch),
>> +        .need_llcc_cfg  = true,
>> +        .reg_offset     = llcc_v2_1_reg_offset,
>> +        .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
>> +    },
>> +    {
>> +        .sct_data       = qdu1000_data_2ch,
>> +        .size           = ARRAY_SIZE(qdu1000_data_2ch),
>> +        .need_llcc_cfg  = true,
>> +        .reg_offset     = llcc_v2_1_reg_offset,
>> +        .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
>> +    },
>> +};
>> +
>>   static const struct qcom_sct_config sc7180_cfgs = {
>>       .llcc_config    = sc7180_cfg,
>>       .num_cfgs    = 1,
>> @@ -611,6 +672,11 @@ static const struct qcom_sct_config sm8550_cfgs = {
>>       .num_cfgs    = 1,
>>   };
>>   +static const struct qcom_sct_config qdu1000_cfgs = {
>> +    .llcc_config    = qdu1000_cfg,
>> +    .num_cfgs    = 1,
>
>
> Should not this be 4 ?

Yes, it should be 4. Thanks for pointing it out.

-Komal

>
> -Mukesh
>
>> +};
>> +
>>   static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER;
>>     /**
>> @@ -1167,6 +1233,7 @@ static int qcom_llcc_probe(struct 
>> platform_device *pdev)
>>   }
>>     static const struct of_device_id qcom_llcc_of_match[] = {
>> +    { .compatible = "qcom,qdu1000-llcc", .data = &qdu1000_cfgs},
>>       { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfgs },
>>       { .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfgs },
>>       { .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfgs },

Re: [PATCH v5 6/6] soc: qcom: llcc: Add QDU1000 and QRU1000 LLCC support

[Komal Bajaj]

On 7/24/2023 6:25 PM, Konrad Dybcio wrote:
> On 24.07.2023 14:45, Mukesh Ojha wrote:
>>
>> On 7/24/2023 2:11 PM, Komal Bajaj wrote:
>>> Add LLCC configuration data for QDU1000 and QRU1000 SoCs.
>>>
>>> Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
>>> ---
> [...]
>
>>>    static const struct qcom_sct_config sc7180_cfgs = {
>>>        .llcc_config    = sc7180_cfg,
>>>        .num_cfgs    = 1,
>>> @@ -611,6 +672,11 @@ static const struct qcom_sct_config sm8550_cfgs = {
>>>        .num_cfgs    = 1,
>>>    };
>>>    +static const struct qcom_sct_config qdu1000_cfgs = {
>>> +    .llcc_config    = qdu1000_cfg,
>>> +    .num_cfgs    = 1,
>>
>> Should not this be 4 ?
> Even better, use ARRAY_SIZE(name_of_arr)

Yes, Thanks for suggesting it.

-Komal

>
> Konrad