Re: Going beyond 256 PCI buses

From: Jeff Garzik <jgarzik@mandrakesoft.com>
To: Tom Gall <tom_gall@vnet.ibm.com>
Cc: linux-kernel@vger.kernel.org
Subject: Re: Going beyond 256 PCI buses
Date: Thu, 14 Jun 2001 10:14:25 -0400	[thread overview]
Message-ID: <3B28C6C1.3477493F@mandrakesoft.com> (raw)
In-Reply-To: <3B273A20.8EE88F8F@vnet.ibm.com>

Tom Gall wrote:
>   The box that I'm wrestling with, has a setup where each PHB has an
> additional id, then each PHB can have up to 256 buses.  So when you are
> talking to a device, the scheme is phbid, bus, dev etc etc. Pretty easy
> really.
> 
>   I am getting for putting something like this into the kernel at large,
> it would probably be best to have a CONFIG_GREATER_THAN_256_BUSES or
> some such.

We don't need such a CONFIG_xxx at all.  The current PCI core code
should scale up just fine.

According to the PCI spec it is -impossible- to have more than 256 buses
on a single "hose", so you simply have to implement multiple hoses, just
like Alpha (and Sparc64?) already do.  That's how the hardware is forced
to implement it...

	Jeff

-- 
Jeff Garzik      | Andre the Giant has a posse.
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