about PENTIUM4 cache line

about PENTIUM4 cache line

[michaelc]

Hi,
     I read the Intel IA-32 developer's manual recently, and I found
 the cache lines for L1 and L2 caches in Pentium4 are 64 bytes
 wide, but the thing make me confused is that the default value
 CONFIG_X86_L1_CACHE_SHIFT option in 2.4.x kernel is 7, why it's
 not 6?   Any expanation about this would be appreciated!
    

  

-- 
Best regards,
Michael Chen                          mailto:michaelc@turbolinux.com.cn

shutdown on pressing the ATX power button

[Sergei Haller]

high!

is there any way to let the system execute something by pressing the ATX
power button (preferrable executing 'shutdown -h now', but would be nice
if it was configurable)

I looked into the (very large) list archive but didnt find any answer.
if it is a kind of FAQ or off topic, please point me to the place I could
find an answer.

PS.: Im not on the list, so please CC to my address if possible.
     (but its not vital as I also could look into the archive)

Thanks in advance

        Sergei

--------------------------------------------------------------------
         eMail:       Sergei.Haller@math.uni-giessen.de
--------------------------------------------------------------------
Be careful of reading health books, you might die of a misprint.
                -- Mark Twain

Re: shutdown on pressing the ATX power button

[Pavel Machek]

Hi!

> is there any way to let the system execute something by pressing the ATX
> power button (preferrable executing 'shutdown -h now', but would be nice
> if it was configurable)
> 
> I looked into the (very large) list archive but didnt find any answer.
> if it is a kind of FAQ or off topic, please point me to the place I could
> find an answer.

Try this, and put this: into inittab

# Action on special keypress (ALT-UpArrow)
kb::kbrequest:/etc/rc/rc.reboot 2 0

--- clean/drivers/acpi/events/evevent.c	Sun Jul  8 23:26:27 2001
+++ linux/drivers/acpi/events/evevent.c	Sun Jul  8 23:25:01 2001
@@ -193,6 +168,8 @@
 
 	if ((status_register & ACPI_STATUS_POWER_BUTTON) &&
 		(enable_register & ACPI_ENABLE_POWER_BUTTON)) {
+                printk ("acpi: Power button pressed!\n");
+                kill_proc (1, SIGWINCH, 1);
 		int_status |= acpi_ev_fixed_event_dispatch (ACPI_EVENT_POWER_BUTTON);
 	}
 

-- 
I'm pavel@ucw.cz. "In my country we have almost anarchy and I don't care."
Panos Katsaloulis describing me w.r.t. patents at discuss@linmodems.org

Re: about PENTIUM4 cache line

[Jamie Lokier]

michaelc wrote:
>      I read the Intel IA-32 developer's manual recently, and I found
>  the cache lines for L1 and L2 caches in Pentium4 are 64 bytes
>  wide, but the thing make me confused is that the default value
>  CONFIG_X86_L1_CACHE_SHIFT option in 2.4.x kernel is 7, why it's
>  not 6?   Any expanation about this would be appreciated!

I don't recall seeing an answer to this.
Was there one?

Cheers,
-- Jamie

Re: about PENTIUM4 cache line

[David B. Stevens]

What's even more interesting is the following:

tux:/usr/src/linux-2.6.0-test3 # grep -r "CONFIG_X86_L1_CACHE_SHIFT" *
arch/i386/defconfig:CONFIG_X86_L1_CACHE_SHIFT=7
arch/x86_64/defconfig:CONFIG_X86_L1_CACHE_SHIFT=6
include/asm-x86_64/cache.h:#define L1_CACHE_SHIFT 
(CONFIG_X86_L1_CACHE_SHIFT)
include/linux/autoconf.h:#define CONFIG_X86_L1_CACHE_SHIFT 5
include/asm-i386/cache.h:#define L1_CACHE_SHIFT (CONFIG_X86_L1_CACHE_SHIFT)
include/asm/cache.h:#define L1_CACHE_SHIFT      (CONFIG_X86_L1_CACHE_SHIFT)
include/config/x86/l1/cache/shift.h:#define CONFIG_X86_L1_CACHE_SHIFT 5
tux:/usr/src/linux-2.6.0-test3 #

Life sure is interesting.

Cheers,
   Dave


Jamie Lokier wrote:
> michaelc wrote:
> 
>>     I read the Intel IA-32 developer's manual recently, and I found
>> the cache lines for L1 and L2 caches in Pentium4 are 64 bytes
>> wide, but the thing make me confused is that the default value
>> CONFIG_X86_L1_CACHE_SHIFT option in 2.4.x kernel is 7, why it's
>> not 6?   Any expanation about this would be appreciated!
> 
> 
> I don't recall seeing an answer to this.
> Was there one?
> 
> Cheers,
> -- Jamie
> -
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Re: about PENTIUM4 cache line

[Dave Jones]

On Sun, Aug 17, 2003 at 09:25:35PM +0100, Jamie Lokier wrote:
 > michaelc wrote:
 > >      I read the Intel IA-32 developer's manual recently, and I found
 > >  the cache lines for L1 and L2 caches in Pentium4 are 64 bytes
 > >  wide, but the thing make me confused is that the default value
 > >  CONFIG_X86_L1_CACHE_SHIFT option in 2.4.x kernel is 7, why it's
 > >  not 6?   Any expanation about this would be appreciated!
 > 
 > I don't recall seeing an answer to this.
 > Was there one?

ISTR it was something to do with how the P4 cachelines are laid out.
Something like 2 sectors of 64 byte lines.

		Dave

-- 
 Dave Jones     http://www.codemonkey.org.uk

Re: about PENTIUM4 cache line

[Dave Jones]

On Sun, Aug 17, 2003 at 04:36:51PM -0400, David B. Stevens wrote:
 > What's even more interesting is the following:

why ?

 > tux:/usr/src/linux-2.6.0-test3 # grep -r "CONFIG_X86_L1_CACHE_SHIFT" *
 > arch/i386/defconfig:CONFIG_X86_L1_CACHE_SHIFT=7
 > arch/x86_64/defconfig:CONFIG_X86_L1_CACHE_SHIFT=6

correct default values for P4 and Hammer respectively.

 > include/asm-x86_64/cache.h:#define L1_CACHE_SHIFT 
 > (CONFIG_X86_L1_CACHE_SHIFT)

Looks sane.

 > include/linux/autoconf.h:#define CONFIG_X86_L1_CACHE_SHIFT 5

compile-time generated from .config

 > include/asm-i386/cache.h:#define L1_CACHE_SHIFT (CONFIG_X86_L1_CACHE_SHIFT)
 > include/asm/cache.h:#define L1_CACHE_SHIFT      (CONFIG_X86_L1_CACHE_SHIFT)

looks sane

 > include/config/x86/l1/cache/shift.h:#define CONFIG_X86_L1_CACHE_SHIFT 5

compile time generated from .config.

		Dave

-- 
 Dave Jones     http://www.codemonkey.org.uk

Re: about PENTIUM4 cache line

[David B. Stevens]

Dave,

Thanks that explains it.

The layout as well as the size needs to be taken into account.

Cheers,
   Dave




Dave Jones wrote:
> On Sun, Aug 17, 2003 at 04:36:51PM -0400, David B. Stevens wrote:
>  > What's even more interesting is the following:
> 
> why ?
> 
>  > tux:/usr/src/linux-2.6.0-test3 # grep -r "CONFIG_X86_L1_CACHE_SHIFT" *
>  > arch/i386/defconfig:CONFIG_X86_L1_CACHE_SHIFT=7
>  > arch/x86_64/defconfig:CONFIG_X86_L1_CACHE_SHIFT=6
> 
> correct default values for P4 and Hammer respectively.
> 
>  > include/asm-x86_64/cache.h:#define L1_CACHE_SHIFT 
>  > (CONFIG_X86_L1_CACHE_SHIFT)
> 
> Looks sane.
> 
>  > include/linux/autoconf.h:#define CONFIG_X86_L1_CACHE_SHIFT 5
> 
> compile-time generated from .config
> 
>  > include/asm-i386/cache.h:#define L1_CACHE_SHIFT (CONFIG_X86_L1_CACHE_SHIFT)
>  > include/asm/cache.h:#define L1_CACHE_SHIFT      (CONFIG_X86_L1_CACHE_SHIFT)
> 
> looks sane
> 
>  > include/config/x86/l1/cache/shift.h:#define CONFIG_X86_L1_CACHE_SHIFT 5
> 
> compile time generated from .config.
> 
> 		Dave
> 

Re: about PENTIUM4 cache line

[Philippe Elie]

Jamie Lokier wrote:
> michaelc wrote:
> 
>>     I read the Intel IA-32 developer's manual recently, and I found
>> the cache lines for L1 and L2 caches in Pentium4 are 64 bytes
>> wide, but the thing make me confused is that the default value
>> CONFIG_X86_L1_CACHE_SHIFT option in 2.4.x kernel is 7, why it's
>> not 6?   Any expanation about this would be appreciated!
> 
> 
> I don't recall seeing an answer to this.
> Was there one?

There is some confusion about P4 cache line size but

Intel Software Developer's Manual VOL 1

Page 2.12, Par 2.6:
"128-byte cache line size
  - Two 64-byte sectors"

regards,
Philippe Elie