From: Mesih Kilinc <mesihkilinc@gmail.com>
To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com
Cc: Mesih Kilinc <mesihkilinc@gmail.com>,
Maxime Ripard <maxime.ripard@free-electrons.com>,
Chen-Yu Tsai <wens@csie.org>,
Russell King <linux@armlinux.org.uk>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Marc Zyngier <marc.zyngier@arm.com>,
Linus Walleij <linus.walleij@linaro.org>,
Icenowy Zheng <icenowy@aosc.io>, Rob Herring <robh+dt@kernel.org>,
Julian Calaby <julian.calaby@gmail.com>
Subject: [RFC PATCH v4 16/17] ARM: dts: suniv: add initial DTSI file for F1C100s
Date: Sun, 25 Nov 2018 10:43:19 +0300 [thread overview]
Message-ID: <3a0db6052d58eb440ea29772fc7ad2502a1dfa3b.1543131714.git.mesihkilinc@gmail.com> (raw)
In-Reply-To: <cover.1543131714.git.mesihkilinc@gmail.com>
F1C100s is one product with the suniv die, which has a 32MiB co-packaged
DDR1 DRAM chip. As we have the support for suniv pin controller and CCU now, add a
initial DTSI for it.
Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
---
arch/arm/boot/dts/suniv-f1c100s.dtsi | 147 +++++++++++++++++++++++++++++++++++
1 file changed, 147 insertions(+)
create mode 100644 arch/arm/boot/dts/suniv-f1c100s.dtsi
diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
new file mode 100644
index 0000000..11bc999
--- /dev/null
+++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
@@ -0,0 +1,147 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR X11)
+/*
+ * Copyright 2018 Icenowy Zheng <icenowy@aosc.io>
+ * Copyright 2018 Mesih Kilinc <mesihkilinc@gmail.com>
+ */
+
+#include <dt-bindings/clock/suniv-ccu-f1c100s.h>
+#include <dt-bindings/reset/suniv-ccu-f1c100s.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+
+ clocks {
+ osc24M: clk-24M {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "osc24M";
+ };
+
+ osc32k: clk-32k {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "osc32k";
+ };
+ };
+
+ cpus {
+ cpu {
+ compatible = "arm,arm926ej-s";
+ device_type = "cpu";
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ sram-controller@1c00000 {
+ compatible = "allwinner,suniv-f1c100s-system-control",
+ "allwinner,sun4i-a10-system-control";
+ reg = <0x01c00000 0x30>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ sram_d: sram@10000 {
+ compatible = "mmio-sram";
+ reg = <0x00010000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x00010000 0x1000>;
+
+ otg_sram: sram-section@0 {
+ compatible = "allwinner,suniv-f1c100s-sram-d",
+ "allwinner,sun4i-a10-sram-d";
+ reg = <0x0000 0x1000>;
+ status = "disabled";
+ };
+ };
+ };
+
+ ccu: clock@1c20000 {
+ compatible = "allwinner,suniv-f1c100s-ccu";
+ reg = <0x01c20000 0x400>;
+ clocks = <&osc24M>, <&osc32k>;
+ clock-names = "hosc", "losc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ intc: interrupt-controller@1c20400 {
+ compatible = "allwinner,suniv-f1c100s-ic";
+ reg = <0x01c20400 0x400>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ pio: pinctrl@1c20800 {
+ compatible = "allwinner,suniv-f1c100s-pinctrl";
+ reg = <0x01c20800 0x400>;
+ interrupts = <38>, <39>, <40>;
+ clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
+ clock-names = "apb", "hosc", "losc";
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #gpio-cells = <3>;
+
+ uart0_pins_a: uart-pins-pe {
+ pins = "PE0", "PE1";
+ function = "uart0";
+ };
+ };
+
+ timer@1c20c00 {
+ compatible = "allwinner,suniv-f1c100s-timer";
+ reg = <0x01c20c00 0x90>;
+ interrupts = <13>;
+ clocks = <&osc24M>;
+ };
+
+ wdt: watchdog@1c20ca0 {
+ compatible = "allwinner,suniv-f1c100s-wdt",
+ "allwinner,sun4i-a10-wdt";
+ reg = <0x01c20ca0 0x20>;
+ };
+
+ uart0: serial@1c25000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c25000 0x400>;
+ interrupts = <1>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART0>;
+ resets = <&ccu RST_BUS_UART0>;
+ status = "disabled";
+ };
+
+ uart1: serial@1c25400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c25400 0x400>;
+ interrupts = <2>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART1>;
+ resets = <&ccu RST_BUS_UART1>;
+ status = "disabled";
+ };
+
+ uart2: serial@1c25800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c25800 0x400>;
+ interrupts = <3>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART2>;
+ resets = <&ccu RST_BUS_UART2>;
+ status = "disabled";
+ };
+ };
+};
--
2.7.4
next prev parent reply other threads:[~2018-11-25 7:44 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-25 7:43 [RFC PATCH v4 00/17] initial support for "suniv" Allwinner new ARM9 SoC Mesih Kilinc
2018-11-25 7:43 ` [RFC PATCH v4 01/17] ARM: Check ARCH_MULTI_V7 to differentiate ARMv5/v7 Allwinner SoCs Mesih Kilinc
2018-11-25 7:43 ` [RFC PATCH v4 02/17] dt-bindings: arm: Add new Allwinner ARMv5 F1C100s SoC Mesih Kilinc
2018-11-26 22:48 ` Rob Herring
2018-11-25 7:43 ` [RFC PATCH v4 03/17] ARM: sunxi: add Allwinner ARMv5 SoCs Mesih Kilinc
2018-11-25 7:43 ` [RFC PATCH v4 04/17] dt-bindings: interrupt-controller: Add suniv interrupt-controller Mesih Kilinc
2018-11-26 22:49 ` Rob Herring
2018-11-25 7:43 ` [RFC PATCH v4 05/17] irqchip/sun4i: Add a struct to hold global variables Mesih Kilinc
2018-11-27 9:48 ` Maxime Ripard
2018-11-25 7:43 ` [RFC PATCH v4 06/17] irqchip/sun4i: Move IC specific register offsets to struct Mesih Kilinc
2018-11-27 9:49 ` Maxime Ripard
2018-11-25 7:43 ` [RFC PATCH v4 07/17] irqchip/sun4i: Add support for Allwinner ARMv5 F1C100s Mesih Kilinc
2018-11-27 9:49 ` Maxime Ripard
2018-11-25 7:43 ` [RFC PATCH v4 08/17] dt-bindings: timer: Add Allwinner suniv timer Mesih Kilinc
2018-11-27 1:37 ` Rob Herring
2018-11-25 7:43 ` [RFC PATCH v4 09/17] clocksource: sun4i: add a compatible for suniv Mesih Kilinc
2018-11-25 7:43 ` [RFC PATCH v4 10/17] dt-bindings: pinctrl: Add Allwinner suniv F1C100s pinctrl Mesih Kilinc
2018-11-25 12:48 ` Linus Walleij
2018-11-25 7:43 ` [RFC PATCH v4 11/17] pinctrl: sunxi: add support for suniv F1C100s (newer F-series SoCs) Mesih Kilinc
2018-11-25 12:49 ` Linus Walleij
2018-11-25 7:43 ` [RFC PATCH v4 12/17] dt-bindings: clock: Add Allwinner suniv F1C100s CCU Mesih Kilinc
2018-11-27 1:39 ` Rob Herring
2018-11-25 7:43 ` [RFC PATCH v4 13/17] clk: sunxi-ng: add support for suniv F1C100s SoC Mesih Kilinc
2018-11-28 21:53 ` Stephen Boyd
2018-11-25 7:43 ` [RFC PATCH v4 14/17] dt-bindings: sram: Add Allwinner suniv F1C100s Mesih Kilinc
2018-11-27 1:39 ` Rob Herring
2018-11-25 7:43 ` [RFC PATCH v4 15/17] dt-bindings: watchdog: Add Allwinner ARMv5 F1C100s wdt Mesih Kilinc
2018-11-27 1:40 ` Rob Herring
2018-11-25 7:43 ` Mesih Kilinc [this message]
2018-11-27 9:59 ` [RFC PATCH v4 16/17] ARM: dts: suniv: add initial DTSI file for F1C100s Maxime Ripard
2018-11-25 7:43 ` [RFC PATCH v4 17/17] ARM: suniv: f1c100s: add device tree for Lichee Pi Nano Mesih Kilinc
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