[PATCH v2 0/3] arm64: dts: ti: Introduce AM62P5 SoC and board

[PATCH v2 0/3] arm64: dts: ti: Introduce AM62P5 SoC and board

[Vignesh Raghavendra]

This series adds basic support for AM62P family of SoCs and specifically
AM62P5 variant. Also adds AM62P5-SK support with basic peripheral
like UART.

TRM at [0] and Schematics is at [1]

[0]: https://www.ti.com/lit/pdf/spruj83
[1]: https://www.ti.com/lit/zip/sprr487

Bootlog:
https://gist.github.com/r-vignesh/edae006877fe8e51370f3cea9bf8ddfc

Change log
v2:
* Fix binding doc to talk about SoC and board
* Fix comments by Andrew on v1, enable main pmx by default, use
  bootph-all and move it to dtsi as appropriate etc
* Collect Acks and R-bys

Bryan Brattlof (3):
  dt-bindings: arm: ti: Add bindings for AM62P5 SoCs
  arm64: dts: ti: Introduce AM62P5 family of SoCs
  arm64: dts: ti: Add support for the AM62P5 Starter Kit

 .../devicetree/bindings/arm/ti/k3.yaml        |   6 +
 arch/arm64/boot/dts/ti/Makefile               |   3 +
 arch/arm64/boot/dts/ti/k3-am62p-main.dtsi     | 136 ++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi      |  15 ++
 arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi   |  32 +++++
 arch/arm64/boot/dts/ti/k3-am62p.dtsi          | 122 ++++++++++++++++
 arch/arm64/boot/dts/ti/k3-am62p5-sk.dts       | 117 +++++++++++++++
 arch/arm64/boot/dts/ti/k3-am62p5.dtsi         | 107 ++++++++++++++
 arch/arm64/boot/dts/ti/k3-pinctrl.h           |   3 +
 9 files changed, 541 insertions(+)
 create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
 create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi
 create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi
 create mode 100644 arch/arm64/boot/dts/ti/k3-am62p.dtsi
 create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
 create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5.dtsi

-- 
2.41.0

[PATCH v2 1/3] dt-bindings: arm: ti: Add bindings for AM62P5 SoCs

[Vignesh Raghavendra]

From: Bryan Brattlof <bb@ti.com>

Add bindings for TI's AM62P5 family of devices.

Signed-off-by: Bryan Brattlof <bb@ti.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
 Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml
index 5ca6af492507..03d2a0d79fb0 100644
--- a/Documentation/devicetree/bindings/arm/ti/k3.yaml
+++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml
@@ -25,6 +25,12 @@ properties:
               - ti,am62a7-sk
           - const: ti,am62a7
 
+      - description: K3 AM62P5 SoC and Boards
+        items:
+          - enum:
+              - ti,am62p5-sk
+          - const: ti,am62p5
+
       - description: K3 AM625 SoC PHYTEC phyBOARD-Lyra
         items:
           - const: phytec,am625-phyboard-lyra-rdk
-- 
2.41.0

[PATCH v2 2/3] arm64: dts: ti: Introduce AM62P5 family of SoCs

[Vignesh Raghavendra]

From: Bryan Brattlof <bb@ti.com>

The AM62Px is an extension of the existing Sitara AM62x low-cost family
of application processors built for Automotive and Linux Application
development. Scalable Arm Cortex-A53 performance and embedded features,
such as: multi high-definition display support, 3D-graphics
acceleration, 4K video acceleration, and extensive peripherals make the
AM62Px well-suited for a broad range of automation and industrial
application, including automotive digital instrumentation, automotive
displays, industrial HMI, and more.

Some highlights of AM62P SoC are:
* Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster.
  Dual/Single core variants are provided in the same package to allow HW
  compatible designs.
* One Device manager Cortext-R5F for system power and resource
  management, and one Cortex-R5F for Functional Safety or
  general-purpose usage.
* One 3D GPU up to 50 GLFOPS
* H.264/H.265 Video Encode/Decode.
* Display support: 3x display support over OLDI/LVDS (1x OLDI-DL, 1x or
  2x OLDI-SL), DSI, or DPI. Up to 3840x1080@60fps resolution
* Integrated Giga-bit Ethernet switch supporting up to a total of two
  external ports (TSN capable).
* 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3xMMC and SD, GPMC for
  NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio,
  1xCSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals.
* Dedicated Centralized Hardware Security Module with support for secure
  boot, debug security and crypto acceleration and trusted execution
  environment.
* One 32-bit DDR Subsystem that supports LPDDR4, DDR4 memory types.
* Multiple low power modes support, ex: Deep sleep, Standby, MCU-only,
  enabling battery powered system design.

For those interested, more details about this SoC can be found in the
Technical Reference Manual here:

    https://www.ti.com/lit/pdf/spruj83

Signed-off-by: Bryan Brattlof <bb@ti.com>
Acked-by: Andrew Davis <afd@ti.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am62p-main.dtsi   | 136 ++++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi    |  15 +++
 arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi |  32 +++++
 arch/arm64/boot/dts/ti/k3-am62p.dtsi        | 122 ++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-am62p5.dtsi       | 107 +++++++++++++++
 arch/arm64/boot/dts/ti/k3-pinctrl.h         |   3 +
 6 files changed, 415 insertions(+)
 create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
 create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi
 create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi
 create mode 100644 arch/arm64/boot/dts/ti/k3-am62p.dtsi
 create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5.dtsi

diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
new file mode 100644
index 000000000000..c24ff905437f
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
@@ -0,0 +1,136 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree file for the AM62P main domain peripherals
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&cbass_main {
+	oc_sram: sram@70000000 {
+		compatible = "mmio-sram";
+		reg = <0x00 0x70000000 0x00 0x10000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x00 0x00 0x70000000 0x10000>;
+	};
+
+	gic500: interrupt-controller@1800000 {
+		compatible = "arm,gic-v3";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		reg = <0x00 0x01800000 0x00 0x10000>,	/* GICD */
+		      <0x00 0x01880000 0x00 0xc0000>,	/* GICR */
+		      <0x01 0x00000000 0x00 0x2000>,    /* GICC */
+		      <0x01 0x00010000 0x00 0x1000>,    /* GICH */
+		      <0x01 0x00020000 0x00 0x2000>;    /* GICV */
+		/*
+		 * vcpumntirq:
+		 * virtual CPU interface maintenance interrupt
+		 */
+		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+		gic_its: msi-controller@1820000 {
+			compatible = "arm,gic-v3-its";
+			reg = <0x00 0x01820000 0x00 0x10000>;
+			socionext,synquacer-pre-its = <0x1000000 0x400000>;
+			msi-controller;
+			#msi-cells = <1>;
+		};
+	};
+
+	dmss: bus@48000000 {
+		bootph-all;
+		compatible = "simple-mfd";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		dma-ranges;
+		ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
+
+		ti,sci-dev-id = <25>;
+
+		secure_proxy_main: mailbox@4d000000 {
+			bootph-all;
+			compatible = "ti,am654-secure-proxy";
+			#mbox-cells = <1>;
+			reg-names = "target_data", "rt", "scfg";
+			reg = <0x00 0x4d000000 0x00 0x80000>,
+			      <0x00 0x4a600000 0x00 0x80000>,
+			      <0x00 0x4a400000 0x00 0x80000>;
+			interrupt-names = "rx_012";
+			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+		};
+	};
+
+	dmsc: system-controller@44043000 {
+		bootph-all;
+		compatible = "ti,k2g-sci";
+		ti,host-id = <12>;
+		mbox-names = "rx", "tx";
+		mboxes = <&secure_proxy_main 12>,
+			 <&secure_proxy_main 13>;
+		reg-names = "debug_messages";
+		reg = <0x00 0x44043000 0x00 0xfe0>;
+
+		k3_pds: power-controller {
+			bootph-all;
+			compatible = "ti,sci-pm-domain";
+			#power-domain-cells = <2>;
+		};
+
+		k3_clks: clock-controller {
+			bootph-all;
+			compatible = "ti,k2g-sci-clk";
+			#clock-cells = <2>;
+		};
+
+		k3_reset: reset-controller {
+			bootph-all;
+			compatible = "ti,sci-reset";
+			#reset-cells = <2>;
+		};
+	};
+
+	main_pmx0: pinctrl@f4000 {
+		bootph-all;
+		compatible = "pinctrl-single";
+		reg = <0x00 0xf4000 0x00 0x2ac>;
+		#pinctrl-cells = <1>;
+		pinctrl-single,register-width = <32>;
+		pinctrl-single,function-mask = <0xffffffff>;
+	};
+
+	main_timer0: timer@2400000 {
+		bootph-all;
+		compatible = "ti,am654-timer";
+		reg = <0x00 0x2400000 0x00 0x400>;
+		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 36 2>;
+		clock-names = "fck";
+		assigned-clocks = <&k3_clks 36 2>;
+		assigned-clock-parents = <&k3_clks 36 3>;
+		power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
+		ti,timer-pwm;
+	};
+
+	main_uart0: serial@2800000 {
+		compatible = "ti,am64-uart", "ti,am654-uart";
+		reg = <0x00 0x02800000 0x00 0x100>;
+		interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 146 0>;
+		clock-names = "fclk";
+		status = "disabled";
+	};
+
+	main_uart1: serial@2810000 {
+		compatible = "ti,am64-uart", "ti,am654-uart";
+		reg = <0x00 0x02810000 0x00 0x100>;
+		interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 152 0>;
+		clock-names = "fclk";
+		status = "disabled";
+	};
+};
diff --git a/arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi
new file mode 100644
index 000000000000..27ca1c9c6d13
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree file for the AM62P MCU domain peripherals
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&cbass_mcu {
+	mcu_pmx0: pinctrl@4084000 {
+		compatible = "pinctrl-single";
+		reg = <0x00 0x04084000 0x00 0x88>;
+		#pinctrl-cells = <1>;
+		pinctrl-single,register-width = <32>;
+		pinctrl-single,function-mask = <0xffffffff>;
+	};
+};
diff --git a/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi
new file mode 100644
index 000000000000..aaf4b793b58e
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree file for the AM62P wakeup domain peripherals
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&cbass_wakeup {
+	wkup_conf: bus@43000000 {
+		bootph-all;
+		compatible = "simple-bus";
+		reg = <0x00 0x43000000 0x00 0x20000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x00 0x00 0x43000000 0x20000>;
+
+		chipid: chipid@14 {
+			bootph-all;
+			compatible = "ti,am654-chipid";
+			reg = <0x14 0x4>;
+		};
+	};
+
+	wkup_uart0: serial@2b300000 {
+		compatible = "ti,am64-uart", "ti,am654-uart";
+		reg = <0x00 0x2b300000 0x00 0x100>;
+		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 114 0>;
+		clock-names = "fclk";
+		status = "disabled";
+	};
+};
diff --git a/arch/arm64/boot/dts/ti/k3-am62p.dtsi b/arch/arm64/boot/dts/ti/k3-am62p.dtsi
new file mode 100644
index 000000000000..294ab73ec98b
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am62p.dtsi
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM62P SoC Family
+ *
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+#include "k3-pinctrl.h"
+
+/ {
+	model = "Texas Instruments K3 AM62P5 SoC";
+	compatible = "ti,am62p5";
+	interrupt-parent = <&gic500>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	firmware {
+		optee {
+			compatible = "linaro,optee-tz";
+			method = "smc";
+		};
+
+		psci: psci {
+			compatible = "arm,psci-1.0";
+			method = "smc";
+		};
+	};
+
+	a53_timer0: timer-cl0-cpu0 {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
+	};
+
+	pmu: pmu {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	cbass_main: bus@f0000 {
+		bootph-all;
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
+			 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
+			 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
+			 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
+			 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
+			 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
+			 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
+			 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
+			 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
+			 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
+			 <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
+			 <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */
+			 <0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */
+			 <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
+			 <0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */
+			 <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */
+			 <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */
+			 <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */
+			 <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
+			 <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
+			 <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
+			 <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */
+			 <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
+			 <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */
+			 <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
+			 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
+
+			 /* MCU Domain Range */
+			 <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>,
+			 <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>,
+			 <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>,
+			 <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>,
+			 <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>,
+
+			 /* Wakeup Domain Range */
+			 <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>,
+			 <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>,
+			 <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>,
+			 <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>,
+			 <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>;
+
+		cbass_mcu: bus@4000000 {
+			compatible = "simple-bus";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, /* Peripheral window */
+				 <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */
+				 <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */
+				 <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU IRAM0 */
+				 <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>; /* MCU IRAM1 */
+		};
+
+		cbass_wakeup: bus@b00000 {
+			bootph-all;
+			compatible = "simple-bus";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
+				 <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
+				 <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* WKUP CTRL MMR */
+				 <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/
+				 <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/
+		};
+	};
+};
+
+/* Now include peripherals for each bus segment */
+#include "k3-am62p-main.dtsi"
+#include "k3-am62p-mcu.dtsi"
+#include "k3-am62p-wakeup.dtsi"
diff --git a/arch/arm64/boot/dts/ti/k3-am62p5.dtsi b/arch/arm64/boot/dts/ti/k3-am62p5.dtsi
new file mode 100644
index 000000000000..50147bb63e03
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am62p5.dtsi
@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree file for the AM62P5 SoC family (quad core)
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * TRM: https://www.ti.com/lit/pdf/spruj83
+ */
+
+/dts-v1/;
+
+#include "k3-am62p.dtsi"
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu-map {
+			cluster0: cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+
+				core1 {
+					cpu = <&cpu1>;
+				};
+
+				core2 {
+					cpu = <&cpu2>;
+				};
+
+				core3 {
+					cpu = <&cpu3>;
+				};
+			};
+		};
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-a53";
+			reg = <0x000>;
+			device_type = "cpu";
+			enable-method = "psci";
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2_0>;
+			clocks = <&k3_clks 135 0>;
+		};
+
+		cpu1: cpu@1 {
+			compatible = "arm,cortex-a53";
+			reg = <0x001>;
+			device_type = "cpu";
+			enable-method = "psci";
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2_0>;
+			clocks = <&k3_clks 136 0>;
+		};
+
+		cpu2: cpu@2 {
+			compatible = "arm,cortex-a53";
+			reg = <0x002>;
+			device_type = "cpu";
+			enable-method = "psci";
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2_0>;
+			clocks = <&k3_clks 137 0>;
+		};
+
+		cpu3: cpu@3 {
+			compatible = "arm,cortex-a53";
+			reg = <0x003>;
+			device_type = "cpu";
+			enable-method = "psci";
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2_0>;
+			clocks = <&k3_clks 138 0>;
+		};
+	};
+
+	l2_0: l2-cache0 {
+		compatible = "cache";
+		cache-unified;
+		cache-level = <2>;
+		cache-size = <0x80000>;
+		cache-line-size = <64>;
+		cache-sets = <512>;
+	};
+};
diff --git a/arch/arm64/boot/dts/ti/k3-pinctrl.h b/arch/arm64/boot/dts/ti/k3-pinctrl.h
index 6004e0967ec5..2a4e0e084d69 100644
--- a/arch/arm64/boot/dts/ti/k3-pinctrl.h
+++ b/arch/arm64/boot/dts/ti/k3-pinctrl.h
@@ -41,6 +41,9 @@
 #define AM62AX_IOPAD(pa, val, muxmode)		(((pa) & 0x1fff)) ((val) | (muxmode))
 #define AM62AX_MCU_IOPAD(pa, val, muxmode)	(((pa) & 0x1fff)) ((val) | (muxmode))
 
+#define AM62PX_IOPAD(pa, val, muxmode)		(((pa) & 0x1fff)) ((val) | (muxmode))
+#define AM62PX_MCU_IOPAD(pa, val, muxmode)	(((pa) & 0x1fff)) ((val) | (muxmode))
+
 #define AM62X_IOPAD(pa, val, muxmode)		(((pa) & 0x1fff)) ((val) | (muxmode))
 #define AM62X_MCU_IOPAD(pa, val, muxmode)	(((pa) & 0x1fff)) ((val) | (muxmode))
 
-- 
2.41.0

[PATCH v2 3/3] arm64: dts: ti: Add support for the AM62P5 Starter Kit

[Vignesh Raghavendra]

From: Bryan Brattlof <bb@ti.com>

Add basic support for the AM62P5 SK with UART console and
ramdisk as rootfs.

Schematics is at https://www.ti.com/lit/zip/sprr487

Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
 arch/arm64/boot/dts/ti/Makefile         |   3 +
 arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 117 ++++++++++++++++++++++++
 2 files changed, 120 insertions(+)
 create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-sk.dts

diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index 437a3d7e8e3a..5a09cad74c44 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -23,6 +23,9 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb
 # Boards with AM62Ax SoC
 dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk.dtb
 
+# Boards with AM62Px SoC
+dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk.dtb
+
 # Boards with AM64x SoC
 dtb-$(CONFIG_ARCH_K3) += k3-am642-evm.dtb
 dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-rdk.dtb
diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
new file mode 100644
index 000000000000..17edfb19e819
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree file for the AM62P5-SK
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * Schematics: https://www.ti.com/lit/zip/sprr487
+ */
+
+/dts-v1/;
+
+#include "k3-am62p5.dtsi"
+
+/ {
+	compatible = "ti,am62p5-sk", "ti,am62p5";
+	model = "Texas Instruments AM62P5 SK";
+
+	aliases {
+		serial0 = &wkup_uart0;
+		serial2 = &main_uart0;
+		serial3 = &main_uart1;
+	};
+
+	chosen {
+		stdout-path = &main_uart0;
+	};
+
+	memory@80000000 {
+		/* 8G RAM */
+		reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
+		      <0x00000008 0x80000000 0x00000001 0x80000000>;
+		device_type = "memory";
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		secure_tfa_ddr: tfa@9e780000 {
+			reg = <0x00 0x9e780000 0x00 0x80000>;
+			no-map;
+		};
+
+		secure_ddr: optee@9e800000 {
+			reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
+			no-map;
+		};
+
+		wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0x9c900000 0x00 0x01e00000>;
+			no-map;
+		};
+	};
+};
+
+&main_pmx0 {
+	main_uart0_pins_default: main-uart0-default-pins {
+		bootph-all;
+		pinctrl-single,pins = <
+			AM62PX_IOPAD(0x1c8, PIN_INPUT, 0)	/* (A22) UART0_RXD */
+			AM62PX_IOPAD(0x1cc, PIN_OUTPUT, 0)	/* (B22) UART0_TXD */
+			AM62PX_IOPAD(0x1d0, PIN_INPUT, 0)	/* (A23) UART0_CTSn */
+			AM62PX_IOPAD(0x1d4, PIN_OUTPUT, 0)	/* (C22) UART0_RTSn */
+		>;
+	};
+
+	main_uart1_pins_default: main-uart1-default-pins {
+		bootph-all;
+		pinctrl-single,pins = <
+			AM62PX_IOPAD(0x194, PIN_INPUT, 2)	/* (D25) MCASP0_AXR3 */
+			AM62PX_IOPAD(0x198, PIN_OUTPUT, 2)	/* (E25) MCASP0_AXR2 */
+			AM62PX_IOPAD(0x1ac, PIN_INPUT, 2)	/* (G23) MCASP0_AFSR */
+			AM62PX_IOPAD(0x1b0, PIN_OUTPUT, 2)	/* (G20) MCASP0_ACLKR */
+		>;
+	};
+};
+
+&main_uart0 {
+	bootph-all;
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_uart0_pins_default>;
+	status = "okay";
+};
+
+&main_uart1 {
+	/* Main UART1 is used by TIFS firmware */
+	bootph-all;
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_uart1_pins_default>;
+	status = "reserved";
+};
+
+&cbass_mcu {
+	bootph-all;
+};
+
+&mcu_pmx0 {
+	bootph-all;
+	wkup_uart0_pins_default: wkup-uart0-default-pins {
+		bootph-all;
+		pinctrl-single,pins = <
+			AM62PX_MCU_IOPAD(0x02c, PIN_INPUT, 0)	/* (C7) WKUP_UART0_CTSn */
+			AM62PX_MCU_IOPAD(0x030, PIN_OUTPUT, 0)	/* (C6) WKUP_UART0_RTSn */
+			AM62PX_MCU_IOPAD(0x024, PIN_INPUT, 0)	/* (D8) WKUP_UART0_RXD */
+			AM62PX_MCU_IOPAD(0x028, PIN_OUTPUT, 0)	/* (D7) WKUP_UART0_TXD */
+		>;
+	};
+};
+
+&wkup_uart0 {
+	/* WKUP UART0 is used by DM firmware */
+	bootph-all;
+	pinctrl-names = "default";
+	pinctrl-0 = <&wkup_uart0_pins_default>;
+	status = "reserved";
+};
-- 
2.41.0

Re: [PATCH v2 3/3] arm64: dts: ti: Add support for the AM62P5 Starter Kit

[Andrew Davis]

On 8/11/23 1:44 PM, Vignesh Raghavendra wrote:
> From: Bryan Brattlof <bb@ti.com>
> 
> Add basic support for the AM62P5 SK with UART console and
> ramdisk as rootfs.
> 
> Schematics is at https://www.ti.com/lit/zip/sprr487
> 
> Signed-off-by: Bryan Brattlof <bb@ti.com>
> Reviewed-by: Dhruva Gole <d-gole@ti.com>
> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
> ---
>   arch/arm64/boot/dts/ti/Makefile         |   3 +
>   arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 117 ++++++++++++++++++++++++
>   2 files changed, 120 insertions(+)
>   create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
> 
> diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
> index 437a3d7e8e3a..5a09cad74c44 100644
> --- a/arch/arm64/boot/dts/ti/Makefile
> +++ b/arch/arm64/boot/dts/ti/Makefile
> @@ -23,6 +23,9 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb
>   # Boards with AM62Ax SoC
>   dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk.dtb
>   
> +# Boards with AM62Px SoC
> +dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk.dtb
> +
>   # Boards with AM64x SoC
>   dtb-$(CONFIG_ARCH_K3) += k3-am642-evm.dtb
>   dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-rdk.dtb
> diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
> new file mode 100644
> index 000000000000..17edfb19e819
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
> @@ -0,0 +1,117 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree file for the AM62P5-SK
> + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
> + *
> + * Schematics: https://www.ti.com/lit/zip/sprr487
> + */
> +
> +/dts-v1/;
> +
> +#include "k3-am62p5.dtsi"
> +
> +/ {
> +	compatible = "ti,am62p5-sk", "ti,am62p5";
> +	model = "Texas Instruments AM62P5 SK";
> +
> +	aliases {
> +		serial0 = &wkup_uart0;
> +		serial2 = &main_uart0;
> +		serial3 = &main_uart1;
> +	};
> +
> +	chosen {
> +		stdout-path = &main_uart0;
> +	};
> +
> +	memory@80000000 {
> +		/* 8G RAM */
> +		reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
> +		      <0x00000008 0x80000000 0x00000001 0x80000000>;
> +		device_type = "memory";
> +	};
> +
> +	reserved-memory {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		secure_tfa_ddr: tfa@9e780000 {
> +			reg = <0x00 0x9e780000 0x00 0x80000>;
> +			no-map;
> +		};
> +
> +		secure_ddr: optee@9e800000 {
> +			reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
> +			no-map;
> +		};
> +
> +		wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 {
> +			compatible = "shared-dma-pool";
> +			reg = <0x00 0x9c900000 0x00 0x01e00000>;
> +			no-map;
> +		};
> +	};
> +};
> +
> +&main_pmx0 {
> +	main_uart0_pins_default: main-uart0-default-pins {
> +		bootph-all;
> +		pinctrl-single,pins = <
> +			AM62PX_IOPAD(0x1c8, PIN_INPUT, 0)	/* (A22) UART0_RXD */
> +			AM62PX_IOPAD(0x1cc, PIN_OUTPUT, 0)	/* (B22) UART0_TXD */
> +			AM62PX_IOPAD(0x1d0, PIN_INPUT, 0)	/* (A23) UART0_CTSn */
> +			AM62PX_IOPAD(0x1d4, PIN_OUTPUT, 0)	/* (C22) UART0_RTSn */
> +		>;
> +	};
> +
> +	main_uart1_pins_default: main-uart1-default-pins {
> +		bootph-all;
> +		pinctrl-single,pins = <
> +			AM62PX_IOPAD(0x194, PIN_INPUT, 2)	/* (D25) MCASP0_AXR3 */
> +			AM62PX_IOPAD(0x198, PIN_OUTPUT, 2)	/* (E25) MCASP0_AXR2 */
> +			AM62PX_IOPAD(0x1ac, PIN_INPUT, 2)	/* (G23) MCASP0_AFSR */
> +			AM62PX_IOPAD(0x1b0, PIN_OUTPUT, 2)	/* (G20) MCASP0_ACLKR */
> +		>;
> +	};
> +};
> +
> +&main_uart0 {
> +	bootph-all;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&main_uart0_pins_default>;
> +	status = "okay";
> +};
> +
> +&main_uart1 {
> +	/* Main UART1 is used by TIFS firmware */

These comments really belong right before the "status" line to
explain why we set it to "reserved".

Otherwise,

Acked-by: Andrew Davis <afd@ti.com>

> +	bootph-all;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&main_uart1_pins_default>;
> +	status = "reserved";
> +};
> +
> +&cbass_mcu {
> +	bootph-all;
> +};
> +
> +&mcu_pmx0 {
> +	bootph-all;
> +	wkup_uart0_pins_default: wkup-uart0-default-pins {
> +		bootph-all;
> +		pinctrl-single,pins = <
> +			AM62PX_MCU_IOPAD(0x02c, PIN_INPUT, 0)	/* (C7) WKUP_UART0_CTSn */
> +			AM62PX_MCU_IOPAD(0x030, PIN_OUTPUT, 0)	/* (C6) WKUP_UART0_RTSn */
> +			AM62PX_MCU_IOPAD(0x024, PIN_INPUT, 0)	/* (D8) WKUP_UART0_RXD */
> +			AM62PX_MCU_IOPAD(0x028, PIN_OUTPUT, 0)	/* (D7) WKUP_UART0_TXD */
> +		>;
> +	};
> +};
> +
> +&wkup_uart0 {
> +	/* WKUP UART0 is used by DM firmware */
> +	bootph-all;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&wkup_uart0_pins_default>;
> +	status = "reserved";
> +};

Re: [PATCH v2 0/3] arm64: dts: ti: Introduce AM62P5 SoC and board

[Nishanth Menon]

Hi Vignesh Raghavendra,

On Sat, 12 Aug 2023 00:14:29 +0530, Vignesh Raghavendra wrote:
> This series adds basic support for AM62P family of SoCs and specifically
> AM62P5 variant. Also adds AM62P5-SK support with basic peripheral
> like UART.
> 
> TRM at [0] and Schematics is at [1]
> 
> [0]: https://www.ti.com/lit/pdf/spruj83
> [1]: https://www.ti.com/lit/zip/sprr487
> 
> [...]

Note: since the changes were trivial, I incorporated the cosmetic
fixup suggested by Andrew locally when I applied. I have also dropped
bootph property from board's reserved nodes inline with what we did
for j721s2[2]. Thanks for the bootlog.

I have applied the following to branch ti-k3-dts-next on [1].
Thank you!

[1/3] dt-bindings: arm: ti: Add bindings for AM62P5 SoCs
      commit: b57fc5cbdbdfd04d44697800a9d59aeb3be2f273
[2/3] arm64: dts: ti: Introduce AM62P5 family of SoCs
      commit: 29075cc09f43a024d962da66d2e4f9eb577713d0
[3/3] arm64: dts: ti: Add support for the AM62P5 Starter Kit
      commit: 935c4047d42e53a06ec768ddc495a44f6869209c

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
[2] https://lore.kernel.org/all/20230811192030.3480616-1-a-nandan@ti.com/
-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

Re: [PATCH v2 2/3] arm64: dts: ti: Introduce AM62P5 family of SoCs

[Krzysztof Kozlowski]

On 11/08/2023 20:44, Vignesh Raghavendra wrote:
> From: Bryan Brattlof <bb@ti.com>
> 
> The AM62Px is an extension of the existing Sitara AM62x low-cost family
> of application processors built for Automotive and Linux Application
> development. Scalable Arm Cortex-A53 performance and embedded features,
> such as: multi high-definition display support, 3D-graphics
> acceleration, 4K video acceleration, and extensive peripherals make the
> AM62Px well-suited for a broad range of automation and industrial
> application, including automotive digital instrumentation, automotive
> displays, industrial HMI, and more.
> 
> Some highlights of AM62P SoC are:
> * Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster.
>   Dual/Single core variants are provided in the same package to allow HW
>   compatible designs.
> * One Device manager Cortext-R5F for system power and resource
>   management, and one Cortex-R5F for Functional Safety or
>   general-purpose usage.
> * One 3D GPU up to 50 GLFOPS
> * H.264/H.265 Video Encode/Decode.
> * Display support: 3x display support over OLDI/LVDS (1x OLDI-DL, 1x or
>   2x OLDI-SL), DSI, or DPI. Up to 3840x1080@60fps resolution
> * Integrated Giga-bit Ethernet switch supporting up to a total of two
>   external ports (TSN capable).
> * 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3xMMC and SD, GPMC for
>   NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio,
>   1xCSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals.
> * Dedicated Centralized Hardware Security Module with support for secure
>   boot, debug security and crypto acceleration and trusted execution
>   environment.
> * One 32-bit DDR Subsystem that supports LPDDR4, DDR4 memory types.
> * Multiple low power modes support, ex: Deep sleep, Standby, MCU-only,
>   enabling battery powered system design.
> 
> For those interested, more details about this SoC can be found in the
> Technical Reference Manual here:
> 
>     https://www.ti.com/lit/pdf/spruj83
> 
> Signed-off-by: Bryan Brattlof <bb@ti.com>
> Acked-by: Andrew Davis <afd@ti.com>
> Reviewed-by: Dhruva Gole <d-gole@ti.com>
> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
> ---
>  arch/arm64/boot/dts/ti/k3-am62p-main.dtsi   | 136 ++++++++++++++++++++
>  arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi    |  15 +++
>  arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi |  32 +++++
>  arch/arm64/boot/dts/ti/k3-am62p.dtsi        | 122 ++++++++++++++++++
>  arch/arm64/boot/dts/ti/k3-am62p5.dtsi       | 107 +++++++++++++++
>  arch/arm64/boot/dts/ti/k3-pinctrl.h         |   3 +
>  6 files changed, 415 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
>  create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi
>  create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi
>  create mode 100644 arch/arm64/boot/dts/ti/k3-am62p.dtsi
>  create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5.dtsi
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
> new file mode 100644
> index 000000000000..c24ff905437f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
> @@ -0,0 +1,136 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree file for the AM62P main domain peripherals
> + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +&cbass_main {
> +	oc_sram: sram@70000000 {
> +		compatible = "mmio-sram";
> +		reg = <0x00 0x70000000 0x00 0x10000>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges = <0x00 0x00 0x70000000 0x10000>;
> +	};
> +
> +	gic500: interrupt-controller@1800000 {
> +		compatible = "arm,gic-v3";
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +		#interrupt-cells = <3>;
> +		interrupt-controller;
> +		reg = <0x00 0x01800000 0x00 0x10000>,	/* GICD */
> +		      <0x00 0x01880000 0x00 0xc0000>,	/* GICR */
> +		      <0x01 0x00000000 0x00 0x2000>,    /* GICC */
> +		      <0x01 0x00010000 0x00 0x1000>,    /* GICH */
> +		      <0x01 0x00020000 0x00 0x2000>;    /* GICV */
> +		/*
> +		 * vcpumntirq:
> +		 * virtual CPU interface maintenance interrupt
> +		 */
> +		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +
> +		gic_its: msi-controller@1820000 {
> +			compatible = "arm,gic-v3-its";
> +			reg = <0x00 0x01820000 0x00 0x10000>;
> +			socionext,synquacer-pre-its = <0x1000000 0x400000>;
> +			msi-controller;
> +			#msi-cells = <1>;
> +		};
> +	};
> +
> +	dmss: bus@48000000 {
> +		bootph-all;
> +		compatible = "simple-mfd";
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		dma-ranges;
> +		ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
> +
> +		ti,sci-dev-id = <25>;

My v1 concerns are still valid.

> +
> +		secure_proxy_main: mailbox@4d000000 {
> +			bootph-all;
> +			compatible = "ti,am654-secure-proxy";
> +			#mbox-cells = <1>;
> +			reg-names = "target_data", "rt", "scfg";
> +			reg = <0x00 0x4d000000 0x00 0x80000>,
> +			      <0x00 0x4a600000 0x00 0x80000>,
> +			      <0x00 0x4a400000 0x00 0x80000>;
> +			interrupt-names = "rx_012";
> +			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +	};


Best regards,
Krzysztof

Re: [PATCH v2 0/3] arm64: dts: ti: Introduce AM62P5 SoC and board

[Krzysztof Kozlowski]

On 12/08/2023 00:49, Nishanth Menon wrote:
> Hi Vignesh Raghavendra,
> 
> On Sat, 12 Aug 2023 00:14:29 +0530, Vignesh Raghavendra wrote:
>> This series adds basic support for AM62P family of SoCs and specifically
>> AM62P5 variant. Also adds AM62P5-SK support with basic peripheral
>> like UART.
>>
>> TRM at [0] and Schematics is at [1]
>>
>> [0]: https://www.ti.com/lit/pdf/spruj83
>> [1]: https://www.ti.com/lit/zip/sprr487
>>
>> [...]
> 
> Note: since the changes were trivial, I incorporated the cosmetic
> fixup suggested by Andrew locally when I applied. I have also dropped
> bootph property from board's reserved nodes inline with what we did
> for j721s2[2]. Thanks for the bootlog.
> 
> I have applied the following to branch ti-k3-dts-next on [1].
> Thank you!
> 
> [1/3] dt-bindings: arm: ti: Add bindings for AM62P5 SoCs
>       commit: b57fc5cbdbdfd04d44697800a9d59aeb3be2f273
> [2/3] arm64: dts: ti: Introduce AM62P5 family of SoCs
>       commit: 29075cc09f43a024d962da66d2e4f9eb577713d0
> [3/3] arm64: dts: ti: Add support for the AM62P5 Starter Kit
>       commit: 935c4047d42e53a06ec768ddc495a44f6869209c
> 

A bit too fast. simple-mfd *is not allowed* on its own.

Best regards,
Krzysztof

Re: [PATCH v2 0/3] arm64: dts: ti: Introduce AM62P5 SoC and board

[Nishanth Menon]

On 21:26-20230814, Krzysztof Kozlowski wrote:
> On 12/08/2023 00:49, Nishanth Menon wrote:

Looping in Vinod

[...]

> 
> A bit too fast. simple-mfd *is not allowed* on its own.
> 

Actually dtbs_check comes up clean, but more I dug at it, looks like we
should probably cleanup.

(everything):
https://gist.github.com/nmenon/5f5f689333c66697969f5d80ad94cfca
(am62p alone):
https://gist.github.com/nmenon/9aaa2067a619b12af338647d19b4cf9b

$ git grep 'compatible = "simple-mfd";' arch/arm64/boot/dts/ti/
arch/arm64/boot/dts/ti/k3-am62-main.dtsi:               compatible = "simple-mfd";
arch/arm64/boot/dts/ti/k3-am62p-main.dtsi:              compatible = "simple-mfd";
arch/arm64/boot/dts/ti/k3-am64-main.dtsi:               compatible = "simple-mfd";
arch/arm64/boot/dts/ti/k3-am65-main.dtsi:               compatible = "simple-mfd";
arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi:                compatible = "simple-mfd";
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi:              compatible = "simple-mfd";
arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi:                compatible = "simple-mfd";
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi:              compatible = "simple-mfd";
arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi:                compatible = "simple-mfd";
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi:             compatible = "simple-mfd";
arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi:               compatible = "simple-mfd";

It is all over our k3 dts folder for dma. Digging further, it looks to
have been explicitly permitted by the bindings:

$ git grep 'compatible = "simple-mfd";'  Documentation/devicetree/bindings/
Documentation/devicetree/bindings/dma/ti/k3-bcdma.yaml:            compatible = "simple-mfd";
Documentation/devicetree/bindings/dma/ti/k3-pktdma.yaml:            compatible = "simple-mfd";
Documentation/devicetree/bindings/dma/ti/k3-udma.yaml:            compatible = "simple-mfd";

Looks like we will have to cleanup the yaml bindings and the dts nodes
in a manner that doesn't break the platforms.

I am not saying that simple-mfd usage is correct, but it was
explicitly permitted by schema in these instances, are you OK that we
clean that in the upcoming merge window as the very first thing we do
and let this series through?

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

Re: [PATCH v2 0/3] arm64: dts: ti: Introduce AM62P5 SoC and board

[Andrew Davis]

On 8/14/23 2:26 PM, Krzysztof Kozlowski wrote:
> On 12/08/2023 00:49, Nishanth Menon wrote:
>> Hi Vignesh Raghavendra,
>>
>> On Sat, 12 Aug 2023 00:14:29 +0530, Vignesh Raghavendra wrote:
>>> This series adds basic support for AM62P family of SoCs and specifically
>>> AM62P5 variant. Also adds AM62P5-SK support with basic peripheral
>>> like UART.
>>>
>>> TRM at [0] and Schematics is at [1]
>>>
>>> [0]: https://www.ti.com/lit/pdf/spruj83
>>> [1]: https://www.ti.com/lit/zip/sprr487
>>>
>>> [...]
>>
>> Note: since the changes were trivial, I incorporated the cosmetic
>> fixup suggested by Andrew locally when I applied. I have also dropped
>> bootph property from board's reserved nodes inline with what we did
>> for j721s2[2]. Thanks for the bootlog.
>>
>> I have applied the following to branch ti-k3-dts-next on [1].
>> Thank you!
>>
>> [1/3] dt-bindings: arm: ti: Add bindings for AM62P5 SoCs
>>        commit: b57fc5cbdbdfd04d44697800a9d59aeb3be2f273
>> [2/3] arm64: dts: ti: Introduce AM62P5 family of SoCs
>>        commit: 29075cc09f43a024d962da66d2e4f9eb577713d0
>> [3/3] arm64: dts: ti: Add support for the AM62P5 Starter Kit
>>        commit: 935c4047d42e53a06ec768ddc495a44f6869209c
>>
> 
> A bit too fast. simple-mfd *is not allowed* on its own.
> 
We have the rule against ['syscon', 'simple-mfd'], which requires a 3rd
specific compatible, but it seems 'simple-mfd' is allowed in the same way
as "simple-bus" (not sure how or why, I would expect a `failed to match any
schema with compatible`, but I'm not getting that either?).

We can add something like simple-mfd.yaml for this to explicitly check that
the compatible has minItems: 2.

But in this case these seem to be just a typo and we meant "simple-bus" here,
then it got copy/pasted over our k3 tree.

So as Nishanth suggested, we can clean this up first thing next cycle, then
add a rule to prevent it from happening for anyone else again while we are at it.

Andrew

> Best regards,
> Krzysztof
> 

Re: [PATCH v2 0/3] arm64: dts: ti: Introduce AM62P5 SoC and board

[Vignesh Raghavendra]

On 15/08/23 02:24, Andrew Davis wrote:
> On 8/14/23 2:26 PM, Krzysztof Kozlowski wrote:
>> On 12/08/2023 00:49, Nishanth Menon wrote:
>>> Hi Vignesh Raghavendra,
>>>
>>> On Sat, 12 Aug 2023 00:14:29 +0530, Vignesh Raghavendra wrote:
>>>> This series adds basic support for AM62P family of SoCs and
>>>> specifically
>>>> AM62P5 variant. Also adds AM62P5-SK support with basic peripheral
>>>> like UART.
>>>>
>>>> TRM at [0] and Schematics is at [1]
>>>>
>>>> [0]: https://www.ti.com/lit/pdf/spruj83
>>>> [1]: https://www.ti.com/lit/zip/sprr487
>>>>
>>>> [...]
>>>
>>> Note: since the changes were trivial, I incorporated the cosmetic
>>> fixup suggested by Andrew locally when I applied. I have also dropped
>>> bootph property from board's reserved nodes inline with what we did
>>> for j721s2[2]. Thanks for the bootlog.
>>>
>>> I have applied the following to branch ti-k3-dts-next on [1].
>>> Thank you!
>>>
>>> [1/3] dt-bindings: arm: ti: Add bindings for AM62P5 SoCs
>>>        commit: b57fc5cbdbdfd04d44697800a9d59aeb3be2f273
>>> [2/3] arm64: dts: ti: Introduce AM62P5 family of SoCs
>>>        commit: 29075cc09f43a024d962da66d2e4f9eb577713d0
>>> [3/3] arm64: dts: ti: Add support for the AM62P5 Starter Kit
>>>        commit: 935c4047d42e53a06ec768ddc495a44f6869209c
>>>
>>
>> A bit too fast. simple-mfd *is not allowed* on its own.
>>
> We have the rule against ['syscon', 'simple-mfd'], which requires a 3rd
> specific compatible, but it seems 'simple-mfd' is allowed in the same way
> as "simple-bus" (not sure how or why, I would expect a `failed to match any
> schema with compatible`, but I'm not getting that either?).
> 

Indeed, I didn't see any warnings from dtbs_check so far

> We can add something like simple-mfd.yaml for this to explicitly check that
> the compatible has minItems: 2.
> 
> But in this case these seem to be just a typo and we meant "simple-bus"
> here,
> then it got copy/pasted over our k3 tree.
> 

I dont think "simple-bus" is enough due to presence to TI specific
property (ti,sci-dev-id). So this will warrant a separate yaml bindings.
 I will work towards adding such a file.

> So as Nishanth suggested, we can clean this up first thing next cycle, then
> add a rule to prevent it from happening for anyone else again while we
> are at it.
> 
> Andrew
> 
>> Best regards,
>> Krzysztof
>>

-- 
Regards
Vignesh

Re: [PATCH v2 0/3] arm64: dts: ti: Introduce AM62P5 SoC and board

[Andrew Davis]

On 8/15/23 1:59 AM, Vignesh Raghavendra wrote:
> 
> 
> On 15/08/23 02:24, Andrew Davis wrote:
>> On 8/14/23 2:26 PM, Krzysztof Kozlowski wrote:
>>> On 12/08/2023 00:49, Nishanth Menon wrote:
>>>> Hi Vignesh Raghavendra,
>>>>
>>>> On Sat, 12 Aug 2023 00:14:29 +0530, Vignesh Raghavendra wrote:
>>>>> This series adds basic support for AM62P family of SoCs and
>>>>> specifically
>>>>> AM62P5 variant. Also adds AM62P5-SK support with basic peripheral
>>>>> like UART.
>>>>>
>>>>> TRM at [0] and Schematics is at [1]
>>>>>
>>>>> [0]: https://www.ti.com/lit/pdf/spruj83
>>>>> [1]: https://www.ti.com/lit/zip/sprr487
>>>>>
>>>>> [...]
>>>>
>>>> Note: since the changes were trivial, I incorporated the cosmetic
>>>> fixup suggested by Andrew locally when I applied. I have also dropped
>>>> bootph property from board's reserved nodes inline with what we did
>>>> for j721s2[2]. Thanks for the bootlog.
>>>>
>>>> I have applied the following to branch ti-k3-dts-next on [1].
>>>> Thank you!
>>>>
>>>> [1/3] dt-bindings: arm: ti: Add bindings for AM62P5 SoCs
>>>>         commit: b57fc5cbdbdfd04d44697800a9d59aeb3be2f273
>>>> [2/3] arm64: dts: ti: Introduce AM62P5 family of SoCs
>>>>         commit: 29075cc09f43a024d962da66d2e4f9eb577713d0
>>>> [3/3] arm64: dts: ti: Add support for the AM62P5 Starter Kit
>>>>         commit: 935c4047d42e53a06ec768ddc495a44f6869209c
>>>>
>>>
>>> A bit too fast. simple-mfd *is not allowed* on its own.
>>>
>> We have the rule against ['syscon', 'simple-mfd'], which requires a 3rd
>> specific compatible, but it seems 'simple-mfd' is allowed in the same way
>> as "simple-bus" (not sure how or why, I would expect a `failed to match any
>> schema with compatible`, but I'm not getting that either?).
>>
> 
> Indeed, I didn't see any warnings from dtbs_check so far
> 
>> We can add something like simple-mfd.yaml for this to explicitly check that
>> the compatible has minItems: 2.
>>
>> But in this case these seem to be just a typo and we meant "simple-bus"
>> here,
>> then it got copy/pasted over our k3 tree.
>>
> 
> I dont think "simple-bus" is enough due to presence to TI specific
> property (ti,sci-dev-id). So this will warrant a separate yaml bindings.

What does that property actually do for us? I know the DMASS has a device ID,
but many of the child devices have their own. Do we need the top level ID and
would it be easier to just drop that property here instead?

Andrew

>   I will work towards adding such a file.
> 
>> So as Nishanth suggested, we can clean this up first thing next cycle, then
>> add a rule to prevent it from happening for anyone else again while we
>> are at it.
>>
>> Andrew
>>
>>> Best regards,
>>> Krzysztof
>>>
> 

Re: [PATCH v2 0/3] arm64: dts: ti: Introduce AM62P5 SoC and board

[Vignesh Raghavendra]

On 15/08/23 12:29, Vignesh Raghavendra wrote:
> 
> 
> On 15/08/23 02:24, Andrew Davis wrote:
>> On 8/14/23 2:26 PM, Krzysztof Kozlowski wrote:
>>> On 12/08/2023 00:49, Nishanth Menon wrote:
>>>> Hi Vignesh Raghavendra,
>>>>
>>>> On Sat, 12 Aug 2023 00:14:29 +0530, Vignesh Raghavendra wrote:
>>>>> This series adds basic support for AM62P family of SoCs and
>>>>> specifically
>>>>> AM62P5 variant. Also adds AM62P5-SK support with basic peripheral
>>>>> like UART.
>>>>>
>>>>> TRM at [0] and Schematics is at [1]
>>>>>
>>>>> [0]: https://www.ti.com/lit/pdf/spruj83
>>>>> [1]: https://www.ti.com/lit/zip/sprr487
>>>>>
>>>>> [...]
>>>>
>>>> Note: since the changes were trivial, I incorporated the cosmetic
>>>> fixup suggested by Andrew locally when I applied. I have also dropped
>>>> bootph property from board's reserved nodes inline with what we did
>>>> for j721s2[2]. Thanks for the bootlog.
>>>>
>>>> I have applied the following to branch ti-k3-dts-next on [1].
>>>> Thank you!
>>>>
>>>> [1/3] dt-bindings: arm: ti: Add bindings for AM62P5 SoCs
>>>>        commit: b57fc5cbdbdfd04d44697800a9d59aeb3be2f273
>>>> [2/3] arm64: dts: ti: Introduce AM62P5 family of SoCs
>>>>        commit: 29075cc09f43a024d962da66d2e4f9eb577713d0
>>>> [3/3] arm64: dts: ti: Add support for the AM62P5 Starter Kit
>>>>        commit: 935c4047d42e53a06ec768ddc495a44f6869209c
>>>>
>>>
>>> A bit too fast. simple-mfd *is not allowed* on its own.
>>>
>> We have the rule against ['syscon', 'simple-mfd'], which requires a 3rd
>> specific compatible, but it seems 'simple-mfd' is allowed in the same way
>> as "simple-bus" (not sure how or why, I would expect a `failed to match any
>> schema with compatible`, but I'm not getting that either?).
>>
> 
> Indeed, I didn't see any warnings from dtbs_check so far
> 
>> We can add something like simple-mfd.yaml for this to explicitly check that
>> the compatible has minItems: 2.
>>
>> But in this case these seem to be just a typo and we meant "simple-bus"
>> here,
>> then it got copy/pasted over our k3 tree.
>>
> 
> I dont think "simple-bus" is enough due to presence to TI specific
> property (ti,sci-dev-id). So this will warrant a separate yaml bindings.
>  I will work towards adding such a file.


Unfortunately that cannot be dropped, it indicates the navss instance to 
be used during PSIL pairing [0] (PSIL proxy to use). 

Looking again at simple-bus.yaml in dt-schema repo, I do see arbitrary 
properties are accepted [1]. But I am not sure if its means device
specific properties are acceptable?

[0] https://software-dl.ti.com/tisci/esd/latest/2_tisci_msgs/rm/rm_psil.html
[1] https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/simple-bus.yaml#L60

> 

-- 
Regards
Vignesh