From: Jon Hunter <jonathanh@nvidia.com>
To: Akhil R <akhilrajeev@nvidia.com>,
dmaengine@vger.kernel.org, ldewangan@nvidia.com,
linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org,
p.zabel@pengutronix.de, thierry.reding@gmail.com,
vkoul@kernel.org, robh+dt@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v3 2/3] dmaengine: tegra: Add terminate() for Tegra234
Date: Wed, 13 Jul 2022 16:22:16 +0100 [thread overview]
Message-ID: <3d299b69-ed76-19bc-a7bb-038ad0d0df8c@nvidia.com> (raw)
In-Reply-To: <20220711154536.41736-3-akhilrajeev@nvidia.com>
On 11/07/2022 16:45, Akhil R wrote:
> In certain cases where the DMA client bus gets corrupted or if the
> end device ceases to send/receive data, DMA can wait indefinitely
> for the data to be received/sent. Attempting to terminate the transfer
> will put the DMA in pause flush mode and it remains there.
>
> The channel is irrecoverable once this pause times out in Tegra194 and
> earlier chips. Whereas, from Tegra234, it can be recovered by disabling
> the channel and reprograming it.
>
> Hence add a new terminate() function that ignores the outcome of
> dma_pause() so that terminate_all() can proceed to disable the channel.
>
> Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
> ---
> drivers/dma/tegra186-gpc-dma.c | 26 ++++++++++++++++++++++++--
> 1 file changed, 24 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c
> index 05cd451f541d..fa9bda4a2bc6 100644
> --- a/drivers/dma/tegra186-gpc-dma.c
> +++ b/drivers/dma/tegra186-gpc-dma.c
> @@ -157,8 +157,8 @@
> * If any burst is in flight and DMA paused then this is the time to complete
> * on-flight burst and update DMA status register.
> */
> -#define TEGRA_GPCDMA_BURST_COMPLETE_TIME 20
> -#define TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT 100
> +#define TEGRA_GPCDMA_BURST_COMPLETE_TIME 10
> +#define TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT 5000 /* 5 msec */
>
> /* Channel base address offset from GPCDMA base address */
> #define TEGRA_GPCDMA_CHANNEL_BASE_ADD_OFFSET 0x20000
> @@ -432,6 +432,17 @@ static int tegra_dma_device_resume(struct dma_chan *dc)
> return 0;
> }
>
> +static inline int tegra_dma_pause_noerr(struct tegra_dma_channel *tdc)
> +{
> + /* Return 0 irrespective of PAUSE status.
> + * This is useful to recover channels that can exit out of flush
> + * state when the channel is disabled.
> + */
> +
> + tegra_dma_pause(tdc);
> + return 0;
> +}
> +
> static void tegra_dma_disable(struct tegra_dma_channel *tdc)
> {
> u32 csr, status;
> @@ -1292,6 +1303,14 @@ static const struct tegra_dma_chip_data tegra194_dma_chip_data = {
> .terminate = tegra_dma_pause,
> };
>
> +static const struct tegra_dma_chip_data tegra234_dma_chip_data = {
> + .nr_channels = 31,
> + .channel_reg_size = SZ_64K,
> + .max_dma_count = SZ_1G,
> + .hw_support_pause = true,
> + .terminate = tegra_dma_pause_noerr,
> +};
> +
> static const struct of_device_id tegra_dma_of_match[] = {
> {
> .compatible = "nvidia,tegra186-gpcdma",
> @@ -1299,6 +1318,9 @@ static const struct of_device_id tegra_dma_of_match[] = {
> }, {
> .compatible = "nvidia,tegra194-gpcdma",
> .data = &tegra194_dma_chip_data,
> + }, {
> + .compatible = "nvidia,tegra234-gpcdma",
> + .data = &tegra234_dma_chip_data,
> }, {
> },
> };
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Cheers
Jon
--
nvpublic
next prev parent reply other threads:[~2022-07-13 15:22 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-11 15:45 [PATCH v3 0/3] Add compatible for Tegra234 GPCDMA Akhil R
2022-07-11 15:45 ` [PATCH v3 1/3] dt-bindings: dmaengine: Add compatible for Tegra234 Akhil R
2022-07-13 15:21 ` Jon Hunter
2022-07-18 19:16 ` Rob Herring
2022-07-19 7:41 ` Akhil R
2022-07-11 15:45 ` [PATCH v3 2/3] dmaengine: tegra: Add terminate() " Akhil R
2022-07-13 15:22 ` Jon Hunter [this message]
2022-07-11 15:45 ` [PATCH v3 3/3] arm64: tegra: Update compatible for Tegra234 GPCDMA Akhil R
2022-07-13 15:22 ` Jon Hunter
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