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From: Jim Lin <jilin@nvidia.com>
To: Rhyland Klein <rklein@nvidia.com>,
	Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Mike Turquette <mturquette@linaro.org>,
	Stephen Warren <swarren@wwwdotorg.org>,
	Stephen Boyd <sboyd@codeaurora.org>,
	Thierry Reding <thierry.reding@gmail.com>,
	Alexandre Courbot <gnurou@gmail.com>,
	"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
	"linux-tegra@vger.kernel.org" <linux-tegra@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: RE: [PATCH v3 12/20] clk: tegra: pll: Add specialized logic for T210
Date: Sat, 2 May 2015 03:12:27 +0000	[thread overview]
Message-ID: <3e078ce64eff4ac992900523b1b67f19@HKMAIL103.nvidia.com> (raw)
In-Reply-To: <1430506447-29074-13-git-send-email-rklein@nvidia.com>


> +static void clk_plle_tegra210_is_enabled(struct struct clk_hw *hw) {
Returned type is "int" instead of "void".
Also one "struct" only for "clk_hw *hw"?

> +	struct tegra_clk_pll *pll = to_clk_pll(hw);
> +	u32 val;
> +
> +	val = pll_readl_base(pll);
> +
> +	return val & PLLE_BASE_ENABLE ? 1 : 0; }
> +
--nvpublic

  reply	other threads:[~2015-05-02  3:12 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-05-01 18:53 [PATCH v3 00/20] Tegra210 Clock Support Rhyland Klein
2015-05-01 18:53 ` [PATCH v3 01/20] clk: tegra: Modify tegra_audio_clk_init to accept more plls Rhyland Klein
2015-05-01 18:53 ` [PATCH v3 02/20] clk: tegra: periph: add new periph clks and muxes for Tegra210 Rhyland Klein
2015-05-01 18:53 ` [PATCH v3 03/20] clk: tegra: pll: add tegra_pll_wait_for_lock to clk header Rhyland Klein
2015-05-01 18:53 ` [PATCH v3 04/20] clk: tegra: pll: simplify clk_enable_path Rhyland Klein
2015-05-01 18:53 ` [PATCH v3 05/20] clk: tegra: pll: update warning msg Rhyland Klein
2015-05-01 18:53 ` [PATCH v3 06/20] clk: tegra: pll-params: change misc_reg count from 3 -> 6 Rhyland Klein
2015-05-01 18:53 ` [PATCH v3 07/20] clk: tegra: pll: Don't unconditionally set LOCK flags Rhyland Klein
2015-05-01 18:53 ` [PATCH v3 08/20] clk: tegra: pll: Add logic for handling SDM data Rhyland Klein
2015-05-01 18:53 ` [PATCH v3 09/20] clk: tegra: pll: Add logic for SS Rhyland Klein
2015-05-01 18:53 ` [PATCH v3 10/20] clk: tegra: pll: Add logic for out-of-table rates for T210 Rhyland Klein
2015-05-01 18:53 ` [PATCH v3 11/20] clk: tegra: pll: Add code to handle if resets are supported by PLL Rhyland Klein
2015-05-01 18:53 ` [PATCH v3 12/20] clk: tegra: pll: Add specialized logic for T210 Rhyland Klein
2015-05-02  3:12   ` Jim Lin [this message]
2015-05-04 15:40     ` Rhyland Klein
2015-05-01 18:54 ` [PATCH v3 13/20] clk: tegra: pll: Add support for PLLMB " Rhyland Klein
2015-05-01 18:54 ` [PATCH v3 14/20] clk: tegra: pll: Adjust vco_min if SDM present Rhyland Klein
2015-05-01 18:54 ` [PATCH v3 15/20] clk: tegra: pll: Add dyn_ramp callback Rhyland Klein
2015-05-01 18:54 ` [PATCH v3 16/20] clk: tegra: pll: Add Set_default logic Rhyland Klein
2015-05-01 18:54 ` [PATCH v3 17/20] clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rate Rhyland Klein
2015-05-01 18:54 ` [PATCH v3 18/20] clk: tegra: Add Super Gen5 Logic Rhyland Klein
2015-05-01 18:54 ` [PATCH v3 19/20] clk: tegra210: add support for Tegra210 clocks Rhyland Klein
2015-05-01 18:54 ` [PATCH v3 20/20] clk: tegra: pll: Fix issues with rates for VCO PLLs Rhyland Klein
2015-05-04 14:13 ` [PATCH v3 00/20] Tegra210 Clock Support Thierry Reding
2015-05-04 15:39   ` Rhyland Klein

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