From: Dilip Kota <eswara.kota@linux.intel.com>
To: robh@kernel.org, p.zabel@pengutronix.de,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: cheol.yong.kim@intel.com, chuanhua.lei@linux.intel.com,
qi-ming.wu@intel.com, Dilip Kota <eswara.kota@linux.intel.com>
Subject: [PATCH v2 1/2] dt-bindings: reset: Add YAML schemas for the Intel Reset controller
Date: Fri, 23 Aug 2019 13:28:34 +0800 [thread overview]
Message-ID: <42039170811f798b8edc66bf85166aefe7dbc903.1566531960.git.eswara.kota@linux.intel.com> (raw)
Add YAML schemas for the reset controller on Intel
Lightening Mountain (LGM) SoC.
Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com>
---
Changes on v2:
Address review comments
Update the compatible property definition
Add description for reset-cells
Add 'additionalProperties: false' property
.../bindings/reset/intel,syscon-reset.yaml | 53 ++++++++++++++++++++++
1 file changed, 53 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/intel,syscon-reset.yaml
diff --git a/Documentation/devicetree/bindings/reset/intel,syscon-reset.yaml b/Documentation/devicetree/bindings/reset/intel,syscon-reset.yaml
new file mode 100644
index 000000000000..3403a967190a
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/intel,syscon-reset.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/intel,syscon-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel Lightening Mountain SoC System Reset Controller
+
+maintainers:
+ - Dilip Kota <eswara.kota@linux.intel.com>
+
+properties:
+ compatible:
+ items:
+ - const: intel,rcu-lgm
+ - const: syscon
+
+ reg:
+ description: Reset controller register base address and size
+
+ intel,global-reset:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: Global reset register offset and bit offset.
+
+ "#reset-cells":
+ const: 2
+ description: |
+ The 1st cell is the register offset.
+ The 2nd cell is the bit offset in the register.
+
+required:
+ - compatible
+ - reg
+ - intel,global-reset
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ rcu0: reset-controller@00000000 {
+ compatible = "intel,rcu-lgm", "syscon";
+ reg = <0x000000 0x80000>;
+ intel,global-reset = <0x10 30>;
+ #reset-cells = <2>;
+ };
+
+ pcie_phy0: pciephy@... {
+ ...
+ /* address offset: 0x10, bit offset: 12 */
+ resets = <&rcu0 0x10 12>;
+ ...
+ };
--
2.11.0
next reply other threads:[~2019-08-23 5:28 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-23 5:28 Dilip Kota [this message]
2019-08-23 5:28 ` [PATCH v2 2/2] reset: Reset controller driver for Intel LGM SoC Dilip Kota
2019-08-23 8:43 ` Philipp Zabel
2019-08-23 9:47 ` Dilip Kota
2019-08-23 10:09 ` Philipp Zabel
2019-08-26 7:01 ` Dilip Kota
2019-08-24 21:11 ` Martin Blumenstingl
2019-08-26 4:01 ` Chuan Hua, Lei
2019-08-26 21:49 ` Martin Blumenstingl
2019-08-27 2:23 ` Chuan Hua, Lei
2019-08-27 21:15 ` Martin Blumenstingl
2019-08-28 1:53 ` Chuan Hua, Lei
2019-08-28 20:01 ` Martin Blumenstingl
2019-08-29 2:50 ` Chuan Hua, Lei
2019-08-29 21:40 ` Martin Blumenstingl
2019-08-30 3:01 ` Chuan Hua, Lei
2019-09-01 21:38 ` Martin Blumenstingl
2019-09-02 9:45 ` Chuan Hua, Lei
2019-09-02 22:04 ` Martin Blumenstingl
2019-09-05 2:38 ` Chuan Hua, Lei
2019-09-05 20:53 ` Martin Blumenstingl
2019-09-12 6:38 ` Dilip Kota
2019-09-19 8:05 ` Dilip Kota
2019-09-19 8:36 ` Langer, Thomas
2019-09-19 9:12 ` Dilip Kota
2019-09-19 19:51 ` Martin Blumenstingl
2019-09-20 2:47 ` Dilip Kota
[not found] ` <29965a80-642b-8f11-b3d4-25c09c3d96cc@linux.intel.com>
2019-10-03 6:50 ` Dilip Kota
2019-10-03 14:19 ` Philipp Zabel
2019-10-07 19:53 ` Martin Blumenstingl
2019-10-08 2:47 ` Dilip Kota
2019-10-08 15:56 ` Philipp Zabel
2019-10-14 9:41 ` Dilip Kota
2019-08-23 12:25 ` [PATCH v2 1/2] dt-bindings: reset: Add YAML schemas for the Intel Reset controller Rob Herring
2019-08-26 9:52 ` Dilip Kota
2019-08-26 11:23 ` Rob Herring
2019-08-27 14:04 ` Dilip Kota
2019-08-28 2:59 ` Dilip Kota
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