* [PATCH RESEND(2) 0/1] Ensure that HiKey 970 won't hang during boot time
@ 2021-12-15 8:57 Mauro Carvalho Chehab
2021-12-15 8:57 ` [PATCH RESEND(2) 1/1] clk: clk-hi3670: mark some clocks as CLK_IS_CRITICAL Mauro Carvalho Chehab
0 siblings, 1 reply; 2+ messages in thread
From: Mauro Carvalho Chehab @ 2021-12-15 8:57 UTC (permalink / raw)
Cc: Mauro Carvalho Chehab, Michael Turquette, Stephen Boyd,
Arnd Bergmann, linux-clk, linux-kernel
Second resend attempt. Didn't get any feedback about this series yet.
During HiKey 970 boot, hundreds of clock lines are disabled, causing the device to
hang.
There are actually two issues here:
1. The clk core doesn't wait enough time for the device drivers to be probed
before agressively disabling "unused" clocks. This was noticed at the
drivers built as modules;
2. Several HiKey 970 gates are essencial for the device to work, but they're
not marked as such.
The first patch fixes the clk core issue, while second one marks the mandatory
clocks as such.
Mauro Carvalho Chehab (1):
clk: clk-hi3670: mark some clocks as CLK_IS_CRITICAL
drivers/clk/hisilicon/clk-hi3670.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
--
2.33.1
^ permalink raw reply [flat|nested] 2+ messages in thread
* [PATCH RESEND(2) 1/1] clk: clk-hi3670: mark some clocks as CLK_IS_CRITICAL
2021-12-15 8:57 [PATCH RESEND(2) 0/1] Ensure that HiKey 970 won't hang during boot time Mauro Carvalho Chehab
@ 2021-12-15 8:57 ` Mauro Carvalho Chehab
0 siblings, 0 replies; 2+ messages in thread
From: Mauro Carvalho Chehab @ 2021-12-15 8:57 UTC (permalink / raw)
Cc: Mauro Carvalho Chehab, Michael Turquette, Stephen Boyd,
linux-clk, linux-kernel
Some clocks can't be disabled or the device stops working.
Mark those with CLK_IS_CRITICAL.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
To avoid mailbombing on a large number of people, only mailing lists were C/C on the cover.
See [PATCH RESEND(2) 0/1] at: https://lore.kernel.org/all/cover.1639558556.git.mchehab+huawei@kernel.org/
drivers/clk/hisilicon/clk-hi3670.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/hisilicon/clk-hi3670.c b/drivers/clk/hisilicon/clk-hi3670.c
index 4d05a71683a5..d5813132df9c 100644
--- a/drivers/clk/hisilicon/clk-hi3670.c
+++ b/drivers/clk/hisilicon/clk-hi3670.c
@@ -82,13 +82,13 @@ static const struct hisi_gate_clock hi3670_crgctrl_gate_sep_clks[] = {
{ HI3670_PPLL2_EN_ACPU, "ppll2_en_acpu", "clk_ppll2",
CLK_SET_RATE_PARENT, 0x0, 3, 0, },
{ HI3670_PPLL3_EN_ACPU, "ppll3_en_acpu", "clk_ppll3",
- CLK_SET_RATE_PARENT, 0x0, 27, 0, },
+ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0x0, 27, 0, },
{ HI3670_PPLL1_GT_CPU, "ppll1_gt_cpu", "clk_ppll1",
CLK_SET_RATE_PARENT, 0x460, 16, 0, },
{ HI3670_PPLL2_GT_CPU, "ppll2_gt_cpu", "clk_ppll2",
CLK_SET_RATE_PARENT, 0x460, 18, 0, },
{ HI3670_PPLL3_GT_CPU, "ppll3_gt_cpu", "clk_ppll3",
- CLK_SET_RATE_PARENT, 0x460, 20, 0, },
+ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0x460, 20, 0, },
{ HI3670_CLK_GATE_PPLL2_MEDIA, "clk_gate_ppll2_media", "clk_ppll2",
CLK_SET_RATE_PARENT, 0x410, 27, 0, },
{ HI3670_CLK_GATE_PPLL3_MEDIA, "clk_gate_ppll3_media", "clk_ppll3",
@@ -166,7 +166,7 @@ static const struct hisi_gate_clock hi3670_crgctrl_gate_sep_clks[] = {
{ HI3670_CLK_CCI400_BYPASS, "clk_cci400_bypass", "clk_ddrc_freq",
CLK_SET_RATE_PARENT, 0x22C, 28, 0, },
{ HI3670_CLK_GATE_CCI400, "clk_gate_cci400", "clk_ddrc_freq",
- CLK_SET_RATE_PARENT, 0x50, 14, 0, },
+ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0x50, 14, 0, },
{ HI3670_CLK_GATE_SD, "clk_gate_sd", "clk_mux_sd_sys",
CLK_SET_RATE_PARENT, 0x40, 17, 0, },
{ HI3670_HCLK_GATE_SD, "hclk_gate_sd", "clk_div_sysbus",
@@ -248,15 +248,15 @@ static const struct hisi_gate_clock hi3670_crgctrl_gate_sep_clks[] = {
{ HI3670_CLK_GATE_AO_ASP, "clk_gate_ao_asp", "clk_div_ao_asp",
CLK_SET_RATE_PARENT, 0x0, 26, 0, },
{ HI3670_PCLK_GATE_PCTRL, "pclk_gate_pctrl", "clk_div_ptp",
- CLK_SET_RATE_PARENT, 0x20, 31, 0, },
+ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0x20, 31, 0, },
{ HI3670_CLK_CSI_TRANS_GT, "clk_csi_trans_gt", "clk_div_csi_trans",
- CLK_SET_RATE_PARENT, 0x30, 24, 0, },
+ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0x30, 24, 0, },
{ HI3670_CLK_DSI_TRANS_GT, "clk_dsi_trans_gt", "clk_div_dsi_trans",
CLK_SET_RATE_PARENT, 0x30, 25, 0, },
{ HI3670_CLK_GATE_PWM, "clk_gate_pwm", "clk_div_ptp",
CLK_SET_RATE_PARENT, 0x20, 0, 0, },
{ HI3670_ABB_AUDIO_EN0, "abb_audio_en0", "clk_gate_abb_192",
- CLK_SET_RATE_PARENT, 0x30, 8, 0, },
+ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0x30, 8, 0, },
{ HI3670_ABB_AUDIO_EN1, "abb_audio_en1", "clk_gate_abb_192",
CLK_SET_RATE_PARENT, 0x30, 9, 0, },
{ HI3670_ABB_AUDIO_GT_EN0, "abb_audio_gt_en0", "abb_audio_en0",
@@ -331,9 +331,9 @@ static const struct hisi_gate_clock hi3670_crgctrl_gate_clks[] = {
{ HI3670_CLK_GATE_DSI_TRANS, "clk_gate_dsi_trans", "clk_ppll2",
CLK_SET_RATE_PARENT, 0xF4, 1, CLK_GATE_HIWORD_MASK, },
{ HI3670_CLK_ANDGT_PTP, "clk_andgt_ptp", "clk_div_320m",
- CLK_SET_RATE_PARENT, 0xF8, 5, CLK_GATE_HIWORD_MASK, },
+ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0xF8, 5, CLK_GATE_HIWORD_MASK, },
{ HI3670_CLK_ANDGT_OUT0, "clk_andgt_out0", "clk_ppll0",
- CLK_SET_RATE_PARENT, 0xF0, 10, CLK_GATE_HIWORD_MASK, },
+ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0xF0, 10, CLK_GATE_HIWORD_MASK, },
{ HI3670_CLK_ANDGT_OUT1, "clk_andgt_out1", "clk_ppll0",
CLK_SET_RATE_PARENT, 0xF0, 11, CLK_GATE_HIWORD_MASK, },
{ HI3670_CLKGT_DP_AUDIO_PLL_AO, "clkgt_dp_audio_pll_ao", "clk_ppll6",
@@ -569,9 +569,9 @@ static const struct hisi_gate_clock hi3670_sctrl_gate_sep_clks[] = {
{ HI3670_PCLK_GATE_SPI, "pclk_gate_spi", "clk_div_ioperi",
CLK_SET_RATE_PARENT, 0x1B0, 10, 0, },
{ HI3670_CLK_GATE_UFS_SUBSYS, "clk_gate_ufs_subsys", "clk_div_ufs_subsys",
- CLK_SET_RATE_PARENT, 0x1B0, 14, 0, },
+ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0x1B0, 14, 0, },
{ HI3670_CLK_GATE_UFSIO_REF, "clk_gate_ufsio_ref", "clkin_sys",
- CLK_SET_RATE_PARENT, 0x1b0, 12, 0, },
+ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0x1b0, 12, 0, },
{ HI3670_PCLK_AO_GPIO0, "pclk_ao_gpio0", "clk_div_aobus",
CLK_SET_RATE_PARENT, 0x160, 11, 0, },
{ HI3670_PCLK_AO_GPIO1, "pclk_ao_gpio1", "clk_div_aobus",
@@ -593,7 +593,7 @@ static const struct hisi_gate_clock hi3670_sctrl_gate_sep_clks[] = {
{ HI3670_PCLK_GATE_SYSCNT, "pclk_gate_syscnt", "clk_div_aobus",
CLK_SET_RATE_PARENT, 0x160, 19, 0, },
{ HI3670_CLK_GATE_SYSCNT, "clk_gate_syscnt", "clkin_sys",
- CLK_SET_RATE_PARENT, 0x160, 20, 0, },
+ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0x160, 20, 0, },
{ HI3670_CLK_GATE_ASP_SUBSYS_PERI, "clk_gate_asp_subsys_peri",
"clk_mux_asp_subsys_peri",
CLK_SET_RATE_PARENT, 0x170, 6, 0, },
@@ -703,7 +703,7 @@ static const struct hisi_gate_clock hi3670_media1_gate_sep_clks[] = {
{ HI3670_PCLK_GATE_DISP_NOC_SUBSYS, "pclk_gate_disp_noc_subsys", "clk_div_sysbus",
CLK_SET_RATE_PARENT, 0x10, 18, 0, },
{ HI3670_ACLK_GATE_DISP_NOC_SUBSYS, "aclk_gate_disp_noc_subsys", "clk_gate_vivobusfreq",
- CLK_SET_RATE_PARENT, 0x10, 17, 0, },
+ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0x10, 17, 0, },
{ HI3670_PCLK_GATE_DSS, "pclk_gate_dss", "pclk_gate_disp_noc_subsys",
CLK_SET_RATE_PARENT, 0x00, 14, 0, },
{ HI3670_ACLK_GATE_DSS, "aclk_gate_dss", "aclk_gate_disp_noc_subsys",
--
2.33.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
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