* [PATCH 2/8] Move privileged processor operations to the subarch layer
@ 2005-08-06 7:13 Zachary Amsden
2005-08-07 1:06 ` Chris Wright
0 siblings, 1 reply; 3+ messages in thread
From: Zachary Amsden @ 2005-08-06 7:13 UTC (permalink / raw)
To: akpm, chrisw, linux-kernel, davej, hpa, Riley, pratap, zach, chrisl
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i386 Transparent Paravirtualization Subarch Patch #2
This change encapsulates CPUID and debug register accessors and moves
them into the sub-architecture layer.
Diffs against: linux-2.6.13-rc4-mm1
Signed-off-by: Zachary Amsden <zach@vmware.com>
Index: linux-2.6.13/include/asm-i386/processor.h
===================================================================
--- linux-2.6.13.orig/include/asm-i386/processor.h 2005-08-04 13:42:38.000000000 -0700
+++ linux-2.6.13/include/asm-i386/processor.h 2005-08-04 14:16:59.000000000 -0700
@@ -132,77 +132,6 @@
#define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
#define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
-/*
- * Generic CPUID function
- * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
- * resulting in stale register contents being returned.
- */
-static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx)
-{
- __asm__("cpuid"
- : "=a" (*eax),
- "=b" (*ebx),
- "=c" (*ecx),
- "=d" (*edx)
- : "0" (op), "c"(0));
-}
-
-/* Some CPUID calls want 'count' to be placed in ecx */
-static inline void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx,
- int *edx)
-{
- __asm__("cpuid"
- : "=a" (*eax),
- "=b" (*ebx),
- "=c" (*ecx),
- "=d" (*edx)
- : "0" (op), "c" (count));
-}
-
-/*
- * CPUID functions returning a single datum
- */
-static inline unsigned int cpuid_eax(unsigned int op)
-{
- unsigned int eax;
-
- __asm__("cpuid"
- : "=a" (eax)
- : "0" (op)
- : "bx", "cx", "dx");
- return eax;
-}
-static inline unsigned int cpuid_ebx(unsigned int op)
-{
- unsigned int eax, ebx;
-
- __asm__("cpuid"
- : "=a" (eax), "=b" (ebx)
- : "0" (op)
- : "cx", "dx" );
- return ebx;
-}
-static inline unsigned int cpuid_ecx(unsigned int op)
-{
- unsigned int eax, ecx;
-
- __asm__("cpuid"
- : "=a" (eax), "=c" (ecx)
- : "0" (op)
- : "bx", "dx" );
- return ecx;
-}
-static inline unsigned int cpuid_edx(unsigned int op)
-{
- unsigned int eax, edx;
-
- __asm__("cpuid"
- : "=a" (eax), "=d" (edx)
- : "0" (op)
- : "bx", "cx");
- return edx;
-}
-
#define load_cr3(pgdir) write_cr3(__pa(pgdir))
/*
@@ -221,32 +150,6 @@
#define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
/*
- * Save the cr4 feature set we're using (ie
- * Pentium 4MB enable and PPro Global page
- * enable), so that any CPU's that boot up
- * after us can get the correct flags.
- */
-extern unsigned long mmu_cr4_features;
-
-static inline void set_in_cr4 (unsigned long mask)
-{
- unsigned cr4;
- mmu_cr4_features |= mask;
- cr4 = read_cr4();
- cr4 |= mask;
- write_cr4(cr4);
-}
-
-static inline void clear_in_cr4 (unsigned long mask)
-{
- unsigned cr4;
- mmu_cr4_features &= ~mask;
- cr4 = read_cr4();
- cr4 &= ~mask;
- write_cr4(cr4);
-}
-
-/*
* NSC/Cyrix CPU configuration register indexes
*/
@@ -483,16 +386,6 @@
.io_bitmap = { [ 0 ... IO_BITMAP_LONGS] = ~0 }, \
}
-static inline void load_esp0(struct tss_struct *tss, struct thread_struct *thread)
-{
- tss->esp0 = thread->esp0;
- /* This can only happen when SEP is enabled, no need to test "SEP"arately */
- if (unlikely(tss->ss1 != thread->sysenter_cs)) {
- tss->ss1 = thread->sysenter_cs;
- wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
- }
-}
-
#define start_thread(regs, new_eip, new_esp) do { \
__asm__("movl %0,%%fs ; movl %0,%%gs": :"r" (0)); \
set_fs(USER_DS); \
@@ -504,33 +397,6 @@
regs->esp = new_esp; \
} while (0)
-/*
- * These special macros can be used to get or set a debugging register
- */
-#define get_debugreg(var, register) \
- __asm__("movl %%db" #register ", %0" \
- :"=r" (var))
-#define set_debugreg(value, register) \
- __asm__("movl %0,%%db" #register \
- : /* no output */ \
- :"r" (value))
-
-/*
- * Set IOPL bits in EFLAGS from given mask
- */
-static inline void set_iopl_mask(unsigned mask)
-{
- unsigned int reg;
- __asm__ __volatile__ ("pushfl;"
- "popl %0;"
- "andl %1, %0;"
- "orl %2, %0;"
- "pushl %0;"
- "popfl"
- : "=&r" (reg)
- : "i" (~X86_EFLAGS_IOPL), "r" (mask));
-}
-
/* Forward declaration, a strange C thing */
struct task_struct;
struct mm_struct;
@@ -606,6 +472,34 @@
/* '6' because it used to be for P6 only (but now covers Pentium 4 as well) */
#define MICROCODE_IOCFREE _IO('6',0)
+#include <mach_processor.h>
+
+/*
+ * Save the cr4 feature set we're using (ie
+ * Pentium 4MB enable and PPro Global page
+ * enable), so that any CPU's that boot up
+ * after us can get the correct flags.
+ */
+extern unsigned long mmu_cr4_features;
+
+static inline void set_in_cr4 (unsigned long mask)
+{
+ unsigned cr4;
+ mmu_cr4_features |= mask;
+ cr4 = read_cr4();
+ cr4 |= mask;
+ write_cr4(cr4);
+}
+
+static inline void clear_in_cr4 (unsigned long mask)
+{
+ unsigned cr4;
+ mmu_cr4_features &= ~mask;
+ cr4 = read_cr4();
+ cr4 &= ~mask;
+ write_cr4(cr4);
+}
+
/* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
static inline void rep_nop(void)
{
Index: linux-2.6.13/include/asm-i386/mach-default/mach_processor.h
===================================================================
--- linux-2.6.13.orig/include/asm-i386/mach-default/mach_processor.h 2005-08-04 14:02:01.000000000 -0700
+++ linux-2.6.13/include/asm-i386/mach-default/mach_processor.h 2005-08-04 14:08:15.000000000 -0700
@@ -0,0 +1,121 @@
+/*
+ * include/asm-i386/mach-default/mach_processor.h
+ *
+ * Copyright (C) 1994 Linus Torvalds
+ *
+ * Moved from include/asm-i386/processor.h 08/05
+ */
+
+#ifndef _MACH_PROCESSOR_H
+#define _MACH_PROCESSOR_H
+
+/*
+ * Generic CPUID function
+ * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
+ * resulting in stale register contents being returned.
+ */
+static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx)
+{
+ __asm__("cpuid"
+ : "=a" (*eax),
+ "=b" (*ebx),
+ "=c" (*ecx),
+ "=d" (*edx)
+ : "0" (op), "c"(0));
+}
+
+/* Some CPUID calls want 'count' to be placed in ecx */
+static inline void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx,
+ int *edx)
+{
+ __asm__("cpuid"
+ : "=a" (*eax),
+ "=b" (*ebx),
+ "=c" (*ecx),
+ "=d" (*edx)
+ : "0" (op), "c" (count));
+}
+
+/*
+ * CPUID functions returning a single datum
+ */
+static inline unsigned int cpuid_eax(unsigned int op)
+{
+ unsigned int eax;
+
+ __asm__("cpuid"
+ : "=a" (eax)
+ : "0" (op)
+ : "bx", "cx", "dx");
+ return eax;
+}
+static inline unsigned int cpuid_ebx(unsigned int op)
+{
+ unsigned int eax, ebx;
+
+ __asm__("cpuid"
+ : "=a" (eax), "=b" (ebx)
+ : "0" (op)
+ : "cx", "dx" );
+ return ebx;
+}
+
+static inline unsigned int cpuid_ecx(unsigned int op)
+{
+ unsigned int eax, ecx;
+
+ __asm__("cpuid"
+ : "=a" (eax), "=c" (ecx)
+ : "0" (op)
+ : "bx", "dx" );
+ return ecx;
+}
+static inline unsigned int cpuid_edx(unsigned int op)
+{
+ unsigned int eax, edx;
+
+ __asm__("cpuid"
+ : "=a" (eax), "=d" (edx)
+ : "0" (op)
+ : "bx", "cx");
+ return edx;
+}
+
+/*
+ * These special macros can be used to get or set a debugging register
+ */
+#define get_debugreg(var, register) \
+ __asm__("movl %%db" #register ", %0" \
+ :"=r" (var))
+#define set_debugreg(value, register) \
+ __asm__("movl %0,%%db" #register \
+ : /* no output */ \
+ :"r" (value))
+
+static inline void load_esp0(struct tss_struct *tss, struct thread_struct *thread)
+{
+ tss->esp0 = thread->esp0;
+ /* This can only happen when SEP is enabled, no need to test "SEP"arately */
+ if (unlikely(tss->ss1 != thread->sysenter_cs)) {
+ tss->ss1 = thread->sysenter_cs;
+ wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
+ }
+}
+
+/*
+ * Set IOPL bits in EFLAGS from given mask
+ */
+static inline void set_iopl_mask(unsigned mask)
+{
+ unsigned int reg;
+ __asm__ __volatile__ ("pushfl;"
+ "popl %0;"
+ "andl %1, %0;"
+ "orl %2, %0;"
+ "pushl %0;"
+ "popfl"
+ : "=&r" (reg)
+ : "i" (~X86_EFLAGS_IOPL), "r" (mask));
+}
+
+#endif
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH 2/8] Move privileged processor operations to the subarch layer
2005-08-06 7:13 [PATCH 2/8] Move privileged processor operations to the subarch layer Zachary Amsden
@ 2005-08-07 1:06 ` Chris Wright
2005-08-07 10:54 ` Zachary Amsden
0 siblings, 1 reply; 3+ messages in thread
From: Chris Wright @ 2005-08-07 1:06 UTC (permalink / raw)
To: Zachary Amsden
Cc: akpm, chrisw, linux-kernel, davej, hpa, Riley, pratap, chrisl
* Zachary Amsden (zach@vmware.com) wrote:
> i386 Transparent Paravirtualization Subarch Patch #2
>
> This change encapsulates CPUID and debug register accessors and moves
> them into the sub-architecture layer.
This one looks to be a superset of Xen version:
--- linux-2.6.12-xen0-arch.orig/include/asm-i386/processor.h
+++ linux-2.6.12-xen0-arch/include/asm-i386/processor.h
@@ -203,10 +203,6 @@ static inline unsigned int cpuid_edx(uns
return edx;
}
-#define load_cr3(pgdir) \
- asm volatile("movl %0,%%cr3": :"r" (__pa(pgdir)))
-
-
/*
* Intel CPU features in CR4
*/
@@ -230,15 +226,7 @@ static inline unsigned int cpuid_edx(uns
*/
extern unsigned long mmu_cr4_features;
-static inline void set_in_cr4 (unsigned long mask)
-{
- mmu_cr4_features |= mask;
- __asm__("movl %%cr4,%%eax\n\t"
- "orl %0,%%eax\n\t"
- "movl %%eax,%%cr4\n"
- : : "irg" (mask)
- :"ax");
-}
+#include <mach_processor.h>
static inline void clear_in_cr4 (unsigned long mask)
{
@@ -453,6 +441,7 @@ struct thread_struct {
unsigned long v86flags, v86mask, saved_esp0;
unsigned int saved_fs, saved_gs;
/* IO permissions */
+ unsigned long io_pl;
unsigned long *io_bitmap_ptr;
/* max allowed port in the bitmap, in bytes: */
unsigned long io_bitmap_max;
@@ -487,6 +476,7 @@ static inline void load_esp0(struct tss_
tss->ss1 = thread->sysenter_cs;
wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
}
+ mach_load_esp0(tss, thread);
}
#define start_thread(regs, new_eip, new_esp) do { \
@@ -500,14 +490,6 @@ static inline void load_esp0(struct tss_
regs->esp = new_esp; \
} while (0)
-/*
- * This special macro can be used to load a debugging register
- */
-#define loaddebug(thread,register) \
- __asm__("movl %0,%%db" #register \
- : /* no output */ \
- :"r" ((thread)->debugreg[register]))
-
/* Forward declaration, a strange C thing */
struct task_struct;
struct mm_struct;
--- /dev/null
+++ linux-2.6.12-xen0-arch/include/asm-i386/mach-default/mach_processor.h
@@ -0,0 +1,27 @@
+#ifndef __ASM_MACH_PROCESSOR_H
+#define __ASM_MACH_PROCESSOR_H
+
+#define load_cr3(pgdir) \
+ asm volatile("movl %0,%%cr3": :"r" (__pa(pgdir)))
+
+static inline void set_in_cr4 (unsigned long mask)
+{
+ mmu_cr4_features |= mask;
+ __asm__("movl %%cr4,%%eax\n\t"
+ "orl %0,%%eax\n\t"
+ "movl %%eax,%%cr4\n"
+ : : "irg" (mask)
+ :"ax");
+}
+
+#define mach_load_esp0(tss, thread) do {} while(0)
+
+/*
+ * This special macro can be used to load a debugging register
+ */
+#define loaddebug(thread,register) \
+ __asm__("movl %0,%%db" #register \
+ : /* no output */ \
+ :"r" ((thread)->debugreg[register]))
+
+#endif
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH 2/8] Move privileged processor operations to the subarch layer
2005-08-07 1:06 ` Chris Wright
@ 2005-08-07 10:54 ` Zachary Amsden
0 siblings, 0 replies; 3+ messages in thread
From: Zachary Amsden @ 2005-08-07 10:54 UTC (permalink / raw)
To: Chris Wright; +Cc: linux-kernel, pratap, chrisl
Chris Wright wrote:
>* Zachary Amsden (zach@vmware.com) wrote:
>
>
>>i386 Transparent Paravirtualization Subarch Patch #2
>>
>>This change encapsulates CPUID and debug register accessors and moves
>>them into the sub-architecture layer.
>>
>>
>
>This one looks to be a superset of Xen version:
>
>
>@@ -453,6 +441,7 @@ struct thread_struct {
> unsigned long v86flags, v86mask, saved_esp0;
> unsigned int saved_fs, saved_gs;
> /* IO permissions */
>+ unsigned long io_pl;
>
>
We also added an iopl field to the thread struct; this was committed to
-rc4-mm1:
The patch titled
x86: make IOPL explicit
has been added to the -mm tree. Its filename is
x86-make-iopl-explicit.patch
diff -puN include/asm-i386/processor.h~x86-make-iopl-explicit include/asm-i386/processor.h
--- devel/include/asm-i386/processor.h~x86-make-iopl-explicit 2005-08-03 23:11:31.000000000 -0700
+++ devel-akpm/include/asm-i386/processor.h 2005-08-03 23:12:06.000000000 -0700
@@ -420,6 +420,7 @@ struct tss_struct {
* Cache the current maximum and the last task that used the bitmap:
*/
unsigned long io_bitmap_max;
+ unsigned long iopl;
struct thread_struct *io_bitmap_owner;
/*
> unsigned long *io_bitmap_ptr;
> /* max allowed port in the bitmap, in bytes: */
> unsigned long io_bitmap_max;
>@@ -487,6 +476,7 @@ static inline void load_esp0(struct tss_
> tss->ss1 = thread->sysenter_cs;
> wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
> }
>+ mach_load_esp0(tss, thread);
>
>
I moved the entire load_esp0() function to the subarch layer. We used
to have a mach_load_esp0(tss, thread) type function. Either way is
acceptable - I sort of prefer your way, but I was concerned that Xen
would not want to support the stashing of the v8086 sysenter CS value in
ss1 (because Xen might not want to shadow the TSS, but use the real one,
which implies ss1 is the real kernel segment). I am sort of less
concerned with this now, because I think that shadowing the TSS is a
really good idea for many reasons, and I believe Xen does this anyway.
In general, a hypervisor must be aware of two things on kernel stack
updates = kernel ESP is essential, but kernel SS is also needed if the
kernel uses alternate stacks. The hypervisor need not know the TSS
pointer itself, since it is either implicit (through TR), or not
required at all (pure hypercall to update the shadow stack).
What to you think of :
include/asm-i386/mach-default/mach_processor.h:
#define mach_update_esp(ss, esp) /* nop */
include/asm-i386/processor.h, in load_esp0():
mach_update_esp0(KERNEL_SS, thread->esp0);
Zach
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2005-08-07 10:54 ` Zachary Amsden
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