Is the PCI clock within the spec?

Is the PCI clock within the spec?

[John Sigler]

Hello everyone,

I have an x86 system, running Linux 2.6.22.1-rt9, in which I plug one
or two PCI I/O boards. I had been experiencing complete system lock-ups
until I sent the system to the board manufacturer, and he fixed the
problem. However, he told me that the PCI clock seemed out of spec,
as far as voltage is concerned.

(Disclaimer: my knowledge of PCI is 0.)

The board manufacturer sent me the plot of (what appears to be) voltage
versus time for the PCI clock.

http://linux.kernel.free.fr/plot1.jpg

The system manufacturer sent me a similar plot.

http://linux.kernel.free.fr/plot2.jpg

As far as my understanding goes, the signal should alternate between
0 V and 3.3 V (??). In the second plot, it looks like Vmax ~ 4.6V
and Vmin ~ -1.4V (Pk-Pk(C1)=6.08V might mean peak-to-peak voltage?)

0) What is this C1 both plots mention?
1) Am I reading the plot correctly?
2) Is -1.4V in DC even possible?
3) 4.6V is 1.3V above 3.3V and -1.4V is -1.4V below 0. (Assuming I read 
the numbers correctly) Are these values within the PCI spec? Or are 
these voltages dangerous and / or might cause some problems with some 
PCI boards?

Regards.

Re: Is the PCI clock within the spec?

[Sébastien Dugué]

  Hi John,

On Tue, 04 Dec 2007 11:57:43 +0100 John Sigler <linux.kernel@free.fr> wrote:

> Hello everyone,
> 
> I have an x86 system, running Linux 2.6.22.1-rt9, in which I plug one
> or two PCI I/O boards. I had been experiencing complete system lock-ups
> until I sent the system to the board manufacturer, and he fixed the
> problem. However, he told me that the PCI clock seemed out of spec,
> as far as voltage is concerned.
> 
> (Disclaimer: my knowledge of PCI is 0.)
> 
> The board manufacturer sent me the plot of (what appears to be) voltage
> versus time for the PCI clock.
> 
> http://linux.kernel.free.fr/plot1.jpg
> 
> The system manufacturer sent me a similar plot.
> 
> http://linux.kernel.free.fr/plot2.jpg

  Why did they send you those plots? What was their point?

> 
> As far as my understanding goes, the signal should alternate between
> 0 V and 3.3 V (??).

  Yep, that's the idealized 3.3V signaling case. However, it looks like
the signal is overshooting a bit (-0.8V below 0 and +0.8V over 3.3V from looking
at the 1st plot) which may be due to incorrect impedance matching on the bus,
probes artifacts, ...

> In the second plot, it looks like Vmax ~ 4.6V
> and Vmin ~ -1.4V (Pk-Pk(C1)=6.08V might mean peak-to-peak voltage?)

  This one looks a bit high (if they measured the same voltages I wonder
where they got their scopes calibrated ;-) )

> 
> 0) What is this C1 both plots mention?

  Scope Channel 1

> 1) Am I reading the plot correctly?

  Yep

> 2) Is -1.4V in DC even possible?

  Why not!

> 3) 4.6V is 1.3V above 3.3V and -1.4V is -1.4V below 0. (Assuming I read 
> the numbers correctly) Are these values within the PCI spec? Or are 
> these voltages dangerous and / or might cause some problems with some 
> PCI boards?

  Well it depends on which of the plot is lying. Looking at the PCI spec
(4.2.2.1) the Vih max for a device is Vcc-max+0.5 = 3.6 + 0.5 = 4.1V
the Vil min is -0.5V so in this case it looks a bit high. But I would not
worry too much, those are only the overshoots, and the circuits have
clamping diodes on their inputs.

  The test waveform voltages for the maximum ratings (4.2.2.3) against which
every PCI device should be qualified are higher than what you have here: 7.1V
peak-to-peak.

  Hope this helps.

  Sebastien.

Re: Is the PCI clock within the spec?

[John Sigler]

Hello Sébastien,

Sébastien Dugué wrote:

> John Sigler wrote:
> 
>> I have an x86 system, running Linux 2.6.22.1-rt9, in which I plug one
>> or two PCI I/O boards. I had been experiencing complete system lock-ups
>> until I sent the system to the board manufacturer, and he fixed the
>> problem. However, he told me that the PCI clock seemed out of spec,
>> as far as voltage is concerned.
>>
>> (Disclaimer: my knowledge of PCI is 0.)
>>
>> The board manufacturer sent me the plot of (what appears to be) voltage
>> versus time for the PCI clock.
>>
>> http://linux.kernel.free.fr/plot1.jpg
>>
>> The system manufacturer sent me a similar plot.
>>
>> http://linux.kernel.free.fr/plot2.jpg
> 
> Why did they send you those plots? What was their point?

The board manufacturer originally thought that the voltage under-
and overshot might be responsible for the system lock-ups we were
experiencing. They sent us the first plot to document the problem.
(In the end, the lock-up was linked to a bug in their DMA engine.)
I asked the system manufacturer whether they could reproduce the
voltage issue, and they sent me the second plot.

>> As far as my understanding goes, the signal should alternate between
>> 0 V and 3.3 V (??).
> 
>   Yep, that's the idealized 3.3V signaling case. However, it looks like
> the signal is overshooting a bit (-0.8V below 0 and +0.8V over 3.3V from looking
> at the 1st plot) which may be due to incorrect impedance matching on the bus,
> probes artifacts, ...
> 
>> In the second plot, it looks like Vmax ~ 4.6V
>> and Vmin ~ -1.4V (Pk-Pk(C1)=6.08V might mean peak-to-peak voltage?)
> 
>   This one looks a bit high (if they measured the same voltages I wonder
> where they got their scopes calibrated ;-) )

The first plot was obtained on my system. The second plot was obtained
on a different system, presumably identical to mine, but I don't know
for sure.

>> 0) What is this C1 both plots mention?
> 
>   Scope Channel 1
> 
>> 1) Am I reading the plot correctly?
> 
>   Yep
> 
>> 2) Is -1.4V in DC even possible?
> 
>   Why not!

Errr... I need to think about it :-)

>> 3) 4.6V is 1.3V above 3.3V and -1.4V is -1.4V below 0. (Assuming I read 
>> the numbers correctly) Are these values within the PCI spec? Or are 
>> these voltages dangerous and / or might cause some problems with some 
>> PCI boards?
> 
>   Well it depends on which of the plot is lying. Looking at the PCI spec
> (4.2.2.1) the Vih max for a device is Vcc-max+0.5 = 3.6 + 0.5 = 4.1V
> the Vil min is -0.5V so in this case it looks a bit high. But I would not
> worry too much, those are only the overshoots, and the circuits have
> clamping diodes on their inputs.
> 
>   The test waveform voltages for the maximum ratings (4.2.2.3) against which
> every PCI device should be qualified are higher than what you have here: 7.1V
> peak-to-peak.

OK. I suppose I should not worry then :-)

>   Hope this helps.

Very much! Thanks.

Regards.

Re: Is the PCI clock within the spec?

[linux-os (Dick Johnson)]

On Tue, 4 Dec 2007, John Sigler wrote:

> Hello Sébastien,
>
> Sébastien Dugué wrote:
>
>> John Sigler wrote:
>>
>>> I have an x86 system, running Linux 2.6.22.1-rt9, in which I plug one
>>> or two PCI I/O boards. I had been experiencing complete system lock-ups
>>> until I sent the system to the board manufacturer, and he fixed the
>>> problem. However, he told me that the PCI clock seemed out of spec,
>>> as far as voltage is concerned.
>>>
>>> (Disclaimer: my knowledge of PCI is 0.)
>>>
>>> The board manufacturer sent me the plot of (what appears to be) voltage
>>> versus time for the PCI clock.
>>>
>>> http://linux.kernel.free.fr/plot1.jpg
>>>
>>> The system manufacturer sent me a similar plot.
>>>
>>> http://linux.kernel.free.fr/plot2.jpg
>>
>> Why did they send you those plots? What was their point?
>
> The board manufacturer originally thought that the voltage under-
> and overshot might be responsible for the system lock-ups we were
> experiencing. They sent us the first plot to document the problem.
> (In the end, the lock-up was linked to a bug in their DMA engine.)
> I asked the system manufacturer whether they could reproduce the
> voltage issue, and they sent me the second plot.
>
>>> As far as my understanding goes, the signal should alternate between
>>> 0 V and 3.3 V (??).
>>
>>   Yep, that's the idealized 3.3V signaling case. However, it looks like
>> the signal is overshooting a bit (-0.8V below 0 and +0.8V over 3.3V from looking
>> at the 1st plot) which may be due to incorrect impedance matching on the bus,
>> probes artifacts, ...
>>
>>> In the second plot, it looks like Vmax ~ 4.6V
>>> and Vmin ~ -1.4V (Pk-Pk(C1)=6.08V might mean peak-to-peak voltage?)
>>
>>   This one looks a bit high (if they measured the same voltages I wonder
>> where they got their scopes calibrated ;-) )
>
> The first plot was obtained on my system. The second plot was obtained
> on a different system, presumably identical to mine, but I don't know
> for sure.
>
>>> 0) What is this C1 both plots mention?
>>
>>   Scope Channel 1
>>
>>> 1) Am I reading the plot correctly?
>>
>>   Yep
>>
>>> 2) Is -1.4V in DC even possible?
>>
>>   Why not!
>
> Errr... I need to think about it :-)
>
>>> 3) 4.6V is 1.3V above 3.3V and -1.4V is -1.4V below 0. (Assuming I read
>>> the numbers correctly) Are these values within the PCI spec? Or are
>>> these voltages dangerous and / or might cause some problems with some
>>> PCI boards?
>>
>>   Well it depends on which of the plot is lying. Looking at the PCI spec
>> (4.2.2.1) the Vih max for a device is Vcc-max+0.5 = 3.6 + 0.5 = 4.1V
>> the Vil min is -0.5V so in this case it looks a bit high. But I would not
>> worry too much, those are only the overshoots, and the circuits have
>> clamping diodes on their inputs.
>>
>>   The test waveform voltages for the maximum ratings (4.2.2.3) against which
>> every PCI device should be qualified are higher than what you have here: 7.1V
>> peak-to-peak.
>
> OK. I suppose I should not worry then :-)
>
>>   Hope this helps.
>
> Very much! Thanks.
>
> Regards.
>

You can't just touch a scope-probe to the PCI
clock pin and clip the scope-probe grounding
lead to a convenient "ground" to make these
measurements! You need a special fixture that
will make a low-inductance connection to the
PCI bus in the same manner as the interface chip.

A scope probe will allow you to see if there is
a clock signal. That's all. You can't determine
its quality. A 4-inch ground lead on the scope
probe will result in 10-20% overshoot and undershoot
being observed.

Cheers,
Dick Johnson
Penguin : Linux version 2.6.22.1 on an i686 machine (5588.27 BogoMips).
My book : http://www.AbominableFirebug.com/
_

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Thank you.

Re: Is the PCI clock within the spec?

[John Sigler]

Dick Johnson wrote:

> You can't just touch a scope-probe to the PCI
> clock pin and clip the scope-probe grounding
> lead to a convenient "ground" to make these
> measurements! You need a special fixture that
> will make a low-inductance connection to the
> PCI bus in the same manner as the interface chip.

(This is waaay over my head.)

Why do you think the two plots (at least the second one)
were not obtained as you describe?

Why would the system manufacturer botch the measurements
when I asked them to show me evidence that their system
was compliant?

> A scope probe will allow you to see if there is
> a clock signal. That's all. You can't determine
> its quality. A 4-inch ground lead on the scope
> probe will result in 10-20% overshoot and undershoot
> being observed.

I don't understand this 10-20% figure.
(0V + 10-20% is still 0V.)

AFAIU, the nominal peak-to-peak voltage is 3.3V. The observed
peak-to-peak voltage is 6.08V (3.3V + 84%).

Regards.

Re: Is the PCI clock within the spec?

[linux-os (Dick Johnson)]

On Tue, 4 Dec 2007, John Sigler wrote:

> Dick Johnson wrote:
>
>> You can't just touch a scope-probe to the PCI
>> clock pin and clip the scope-probe grounding
>> lead to a convenient "ground" to make these
>> measurements! You need a special fixture that
>> will make a low-inductance connection to the
>> PCI bus in the same manner as the interface chip.
>
> (This is waaay over my head.)
>
> Why do you think the two plots (at least the second one)
> were not obtained as you describe?
>

They didn't describe the test setup, simply supplied a
"go away and don't bother me" picture of something
that means nothing.

>
> Why would the system manufacturer botch the measurements
> when I asked them to show me evidence that their system
> was compliant?
>

I think they just sent you a picture, thinking it would
make you go away. It is a common ploy.

>> A scope probe will allow you to see if there is
>> a clock signal. That's all. You can't determine
>> its quality. A 4-inch ground lead on the scope
>> probe will result in 10-20% overshoot and undershoot
>> being observed.
>
> I don't understand this 10-20% figure.
> (0V + 10-20% is still 0V.)
>

There is a definition of overshoot and undershoot. 10 percent
undershoot will show a 0->3.3 volt signal going 0.33 volts
below "ground," i.e., -0.33 V on peaks. 10 percent overshoot
will show a 0->3.3 volt signal going to 3.63 volts above ground
on peaks, i.e., +3.63 volts.

> AFAIU, the nominal peak-to-peak voltage is 3.3V. The observed
> peak-to-peak voltage is 6.08V (3.3V + 84%).
>

This may be a "5 volt" bus. 3.3 volt devices are supposedly
5 volt tolerant. For instance, the PLX, PCI 9656BA, probably
the most common PCI interface chip in use, will handle those
voltages fine. The actual logic-level switch occurs at about
1.5 volts. Since the PCI bus is clocked, it is unlikely
that a "lockup" you describe is caused by the bus, more
likely a hung DMA operation caused by a failure to handle
errors (hardware or software, cause unknown). With the
chip I describe, it can be programmed so that it will not
hold the bus "forever," with a hung DMA operation. However,
some cooperation with the stuff in your FPGA as well as
the software in the driver is necessary.

> Regards.
>

Cheers,
Dick Johnson
Penguin : Linux version 2.6.22.1 on an i686 machine (5588.27 BogoMips).
My book : http://www.AbominableFirebug.com/
_


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The information transmitted in this message is confidential and may be privileged.  Any review, retransmission, dissemination, or other use of this information by persons or entities other than the intended recipient is prohibited.  If you are not the intended recipient, please notify Analogic Corporation immediately - by replying to this message or by sending an email to DeliveryErrors@analogic.com - and destroy all copies of this information, including any attachments, without reading or disclosing them.

Thank you.

RE: Is the PCI clock within the spec?

[David Schwartz]

> > A scope probe will allow you to see if there is
> > a clock signal. That's all. You can't determine
> > its quality. A 4-inch ground lead on the scope
> > probe will result in 10-20% overshoot and undershoot
> > being observed.

> I don't understand this 10-20% figure.
> (0V + 10-20% is still 0V.)

If you're jumping from a 900 foot marker to a 910 foot marker, does a 10%
overshoot mean you jumped 1 foot too far or 90 feet too far? The percentage
is of the distance you were trying to go, not of where you started or where
you ended up.

> AFAIU, the nominal peak-to-peak voltage is 3.3V. The observed
> peak-to-peak voltage is 6.08V (3.3V + 84%).

So a 10% undershoot would mean that rather than going from 3.3V to 0V, you
overshot 0V by 10% or the distance you travelled. The voltages could just as
well be 100V and 103.3V, the transitions would still be the same. What you
call zero is, at least in principle, arbitrary.

DS