* [PATCH 1/4] dt-bindings: phy: convert phy-mtk-xsphy.txt to YAML schema
@ 2020-09-22 7:55 Chunfeng Yun
2020-09-22 7:55 ` [PATCH 2/4] dt-bindings: phy: convert phy-mtk-tphy.txt " Chunfeng Yun
` (3 more replies)
0 siblings, 4 replies; 8+ messages in thread
From: Chunfeng Yun @ 2020-09-22 7:55 UTC (permalink / raw)
To: Chun-Kuang Hu, Rob Herring, Kishon Vijay Abraham I, Stanley Chu
Cc: Philipp Zabel, David Airlie, Daniel Vetter, Vinod Koul,
Chunfeng Yun, Matthias Brugger, CK Hu, dri-devel, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek
Convert phy-mtk-xsphy.txt to YAML schema mediatek,xsphy.yaml
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
.../bindings/phy/mediatek,xsphy.yaml | 203 ++++++++++++++++++
.../devicetree/bindings/phy/phy-mtk-xsphy.txt | 109 ----------
2 files changed, 203 insertions(+), 109 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml
delete mode 100644 Documentation/devicetree/bindings/phy/phy-mtk-xsphy.txt
diff --git a/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml
new file mode 100644
index 000000000000..0aaa10640b5a
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml
@@ -0,0 +1,203 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2020 MediaTek
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/mediatek,xsphy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek XS-PHY Controller Device Tree Bindings
+
+maintainers:
+ - Chunfeng Yun <chunfeng.yun@mediatek.com>
+
+description: |
+ The XS-PHY controller supports physical layer functionality for USB3.1
+ GEN2 controller on MediaTek SoCs.
+
+properties:
+ $nodename:
+ pattern: "^xs-phy@[0-9a-f]+$"
+
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - mediatek,mt3611-xsphy
+ - enum:
+ - mediatek,xsphy
+ - items:
+ - const: mediatek,xsphy
+
+ reg:
+ description: |
+ Register shared by multiple U3 ports, exclude port's private register,
+ if only U2 ports provided, shouldn't use the property.
+ maxItems: 1
+
+ "#address-cells":
+ enum: [1, 2]
+
+ "#size-cells":
+ enum: [1, 2]
+
+ ranges: true
+
+ mediatek,src-ref-clk-mhz:
+ description:
+ Frequency of reference clock for slew rate calibrate
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 26
+
+ mediatek,src-coef:
+ description:
+ Coefficient for slew rate calibrate, depends on SoC process
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 17
+
+# Required child node:
+patternProperties:
+ "^usb-phy@[0-9a-f]+$":
+ type: object
+ description: |
+ A sub-node is required for each port the controller provides.
+ Address range information including the usual 'reg' property
+ is used inside these nodes to describe the controller's topology.
+
+ properties:
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz)
+
+ clock-names:
+ items:
+ - const: ref
+
+ "#phy-cells":
+ const: 1
+ description: |
+ The cells contain the following arguments.
+
+ - description: The PHY type
+ enum:
+ - PHY_TYPE_USB2
+ - PHY_TYPE_USB3
+
+ #The following optional vendor properties are only for debug or HQA test
+ mediatek,eye-src:
+ description:
+ The value of slew rate calibrate (U2 phy)
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 7
+
+ mediatek,eye-vrt:
+ description:
+ The selection of VRT reference voltage (U2 phy)
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 7
+
+ mediatek,eye-term:
+ description:
+ The selection of HS_TX TERM reference voltage (U2 phy)
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 7
+
+ mediatek,efuse-intr:
+ description:
+ The selection of Internal Resistor (U2/U3 phy)
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 63
+
+ mediatek,efuse-tx-imp:
+ description:
+ The selection of TX Impedance (U3 phy)
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 31
+
+ mediatek,efuse-rx-imp:
+ description:
+ The selection of RX Impedance (U3 phy)
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 31
+
+ required:
+ - reg
+ - clocks
+ - clock-names
+ - "#phy-cells"
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+
+additionalProperties: false
+
+#Banks layout of xsphy
+#-------------------------------------------------------------
+#port offset bank
+#u2 port0 0x0000 MISC
+# 0x0100 FMREG
+# 0x0300 U2PHY_COM
+#u2 port1 0x1000 MISC
+# 0x1100 FMREG
+# 0x1300 U2PHY_COM
+#u2 port2 0x2000 MISC
+# ...
+#u31 common 0x3000 DIG_GLB
+# 0x3100 PHYA_GLB
+#u31 port0 0x3400 DIG_LN_TOP
+# 0x3500 DIG_LN_TX0
+# 0x3600 DIG_LN_RX0
+# 0x3700 DIG_LN_DAIF
+# 0x3800 PHYA_LN
+#u31 port1 0x3a00 DIG_LN_TOP
+# 0x3b00 DIG_LN_TX0
+# 0x3c00 DIG_LN_RX0
+# 0x3d00 DIG_LN_DAIF
+# 0x3e00 PHYA_LN
+# ...
+#DIG_GLB & PHYA_GLB are shared by U31 ports.
+
+examples:
+ - |
+ #include <dt-bindings/phy/phy.h>
+
+ u3phy: xs-phy@11c40000 {
+ compatible = "mediatek,mt3611-xsphy", "mediatek,xsphy";
+ reg = <0x11c43000 0x0200>;
+ mediatek,src-ref-clk-mhz = <26>;
+ mediatek,src-coef = <17>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ u2port0: usb-phy@11c40000 {
+ reg = <0x11c40000 0x0400>;
+ clocks = <&clk48m>;
+ clock-names = "ref";
+ mediatek,eye-src = <4>;
+ #phy-cells = <1>;
+ };
+
+ u3port0: usb-phy@11c43000 {
+ reg = <0x11c43400 0x0500>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ mediatek,efuse-intr = <28>;
+ #phy-cells = <1>;
+ };
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-xsphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-xsphy.txt
deleted file mode 100644
index e7caefa0b9c2..000000000000
--- a/Documentation/devicetree/bindings/phy/phy-mtk-xsphy.txt
+++ /dev/null
@@ -1,109 +0,0 @@
-MediaTek XS-PHY binding
---------------------------
-
-The XS-PHY controller supports physical layer functionality for USB3.1
-GEN2 controller on MediaTek SoCs.
-
-Required properties (controller (parent) node):
- - compatible : should be "mediatek,<soc-model>-xsphy", "mediatek,xsphy",
- soc-model is the name of SoC, such as mt3611 etc;
- when using "mediatek,xsphy" compatible string, you need SoC specific
- ones in addition, one of:
- - "mediatek,mt3611-xsphy"
-
- - #address-cells, #size-cells : should use the same values as the root node
- - ranges: must be present
-
-Optional properties (controller (parent) node):
- - reg : offset and length of register shared by multiple U3 ports,
- exclude port's private register, if only U2 ports provided,
- shouldn't use the property.
- - mediatek,src-ref-clk-mhz : u32, frequency of reference clock for slew rate
- calibrate
- - mediatek,src-coef : u32, coefficient for slew rate calibrate, depends on
- SoC process
-
-Required nodes : a sub-node is required for each port the controller
- provides. Address range information including the usual
- 'reg' property is used inside these nodes to describe
- the controller's topology.
-
-Required properties (port (child) node):
-- reg : address and length of the register set for the port.
-- clocks : a list of phandle + clock-specifier pairs, one for each
- entry in clock-names
-- clock-names : must contain
- "ref": 48M reference clock for HighSpeed analog phy; and 26M
- reference clock for SuperSpeedPlus analog phy, sometimes is
- 24M, 25M or 27M, depended on platform.
-- #phy-cells : should be 1
- cell after port phandle is phy type from:
- - PHY_TYPE_USB2
- - PHY_TYPE_USB3
-
-The following optional properties are only for debug or HQA test
-Optional properties (PHY_TYPE_USB2 port (child) node):
-- mediatek,eye-src : u32, the value of slew rate calibrate
-- mediatek,eye-vrt : u32, the selection of VRT reference voltage
-- mediatek,eye-term : u32, the selection of HS_TX TERM reference voltage
-- mediatek,efuse-intr : u32, the selection of Internal Resistor
-
-Optional properties (PHY_TYPE_USB3 port (child) node):
-- mediatek,efuse-intr : u32, the selection of Internal Resistor
-- mediatek,efuse-tx-imp : u32, the selection of TX Impedance
-- mediatek,efuse-rx-imp : u32, the selection of RX Impedance
-
-Banks layout of xsphy
--------------------------------------------------------------
-port offset bank
-u2 port0 0x0000 MISC
- 0x0100 FMREG
- 0x0300 U2PHY_COM
-u2 port1 0x1000 MISC
- 0x1100 FMREG
- 0x1300 U2PHY_COM
-u2 port2 0x2000 MISC
- ...
-u31 common 0x3000 DIG_GLB
- 0x3100 PHYA_GLB
-u31 port0 0x3400 DIG_LN_TOP
- 0x3500 DIG_LN_TX0
- 0x3600 DIG_LN_RX0
- 0x3700 DIG_LN_DAIF
- 0x3800 PHYA_LN
-u31 port1 0x3a00 DIG_LN_TOP
- 0x3b00 DIG_LN_TX0
- 0x3c00 DIG_LN_RX0
- 0x3d00 DIG_LN_DAIF
- 0x3e00 PHYA_LN
- ...
-
-DIG_GLB & PHYA_GLB are shared by U31 ports.
-
-Example:
-
-u3phy: usb-phy@11c40000 {
- compatible = "mediatek,mt3611-xsphy", "mediatek,xsphy";
- reg = <0 0x11c43000 0 0x0200>;
- mediatek,src-ref-clk-mhz = <26>;
- mediatek,src-coef = <17>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- u2port0: usb-phy@11c40000 {
- reg = <0 0x11c40000 0 0x0400>;
- clocks = <&clk48m>;
- clock-names = "ref";
- mediatek,eye-src = <4>;
- #phy-cells = <1>;
- };
-
- u3port0: usb-phy@11c43000 {
- reg = <0 0x11c43400 0 0x0500>;
- clocks = <&clk26m>;
- clock-names = "ref";
- mediatek,efuse-intr = <28>;
- #phy-cells = <1>;
- };
-};
--
2.18.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/4] dt-bindings: phy: convert phy-mtk-tphy.txt to YAML schema
2020-09-22 7:55 [PATCH 1/4] dt-bindings: phy: convert phy-mtk-xsphy.txt to YAML schema Chunfeng Yun
@ 2020-09-22 7:55 ` Chunfeng Yun
2020-09-22 16:04 ` Rob Herring
2020-09-22 7:55 ` [PATCH 3/4] dt-bindings: phy: convert phy-mtk-ufs.txt " Chunfeng Yun
` (2 subsequent siblings)
3 siblings, 1 reply; 8+ messages in thread
From: Chunfeng Yun @ 2020-09-22 7:55 UTC (permalink / raw)
To: Chun-Kuang Hu, Rob Herring, Kishon Vijay Abraham I, Stanley Chu
Cc: Philipp Zabel, David Airlie, Daniel Vetter, Vinod Koul,
Chunfeng Yun, Matthias Brugger, CK Hu, dri-devel, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek
Convert phy-mtk-tphy.txt to YAML schema mediatek,tphy.yaml
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
.../bindings/phy/mediatek,tphy.yaml | 260 ++++++++++++++++++
.../devicetree/bindings/phy/phy-mtk-tphy.txt | 162 -----------
2 files changed, 260 insertions(+), 162 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
delete mode 100644 Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
diff --git a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
new file mode 100644
index 000000000000..eec75d13ca42
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
@@ -0,0 +1,260 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2020 MediaTek
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/mediatek,tphy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek T-PHY Controller Device Tree Bindings
+
+maintainers:
+ - Chunfeng Yun <chunfeng.yun@mediatek.com>
+
+description: |
+ The T-phy controller supports physical layer functionality for a number of
+ controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
+
+properties:
+ $nodename:
+ pattern: "^t-phy@[0-9a-f]+$"
+
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - mediatek,mt2701-tphy
+ - enum:
+ - mediatek,generic-tphy-v1
+ - items:
+ - enum:
+ - mediatek,mt2712-tphy
+ - enum:
+ - mediatek,generic-tphy-v2
+ - items:
+ - enum:
+ - mediatek,mt8173-u3phy
+ - items:
+ - const: mediatek,generic-tphy-v1
+ - const: mediatek,generic-tphy-v2
+ - const: mediatek,mt8173-u3phy
+
+ reg:
+ description: |
+ Register shared by multiple ports, exclude port's private register.
+ It is needed for T-PHY V1, such as mt2701 and mt8173, but not for
+ T-PHY V2, such as mt2712.
+ maxItems: 1
+
+ "#address-cells":
+ enum: [1, 2]
+
+ "#size-cells":
+ enum: [1, 2]
+
+ # Used with non-empty value if optional 'reg' is not provided.
+ # The format of the value is an arbitrary number of triplets of
+ # (child-bus-address, parent-bus-address, length).
+ ranges: true
+
+ mediatek,src-ref-clk-mhz:
+ description:
+ Frequency of reference clock for slew rate calibrate
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 26
+
+ mediatek,src-coef:
+ description:
+ Coefficient for slew rate calibrate, depends on SoC process
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 28
+
+# Required child node:
+patternProperties:
+ "^usb-phy@[0-9a-f]+$":
+ type: object
+ description: |
+ A sub-node is required for each port the controller provides.
+ Address range information including the usual 'reg' property
+ is used inside these nodes to describe the controller's topology.
+
+ properties:
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz)
+ - description: Reference clock of analog phy, used if the clocks
+ of analog and digital phys are separated, otherwise uses
+ "ref" clock only if needed.
+
+ clock-names:
+ items:
+ - const: ref
+ - const: da_ref
+
+ "#phy-cells":
+ const: 1
+ description: |
+ The cells contain the following arguments.
+
+ - description: The PHY type
+ enum:
+ - PHY_TYPE_USB2
+ - PHY_TYPE_USB3
+ - PHY_TYPE_PCIE
+ - PHY_TYPE_SATA
+
+ #The following optional vendor properties are only for debug or HQA test
+ mediatek,eye-src:
+ description:
+ The value of slew rate calibrate (U2 phy)
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 7
+
+ mediatek,eye-vrt:
+ description:
+ The selection of VRT reference voltage (U2 phy)
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 7
+
+ mediatek,eye-term:
+ description:
+ The selection of HS_TX TERM reference voltage (U2 phy)
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 7
+
+ mediatek,intr:
+ description:
+ The selection of internal resistor (U2 phy)
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 31
+
+ mediatek,discth:
+ description:
+ The selection of disconnect threshold (U2 phy)
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 15
+
+ mediatek,bc12:
+ description:
+ Specify the flag to enable BC1.2 if support it
+ type: boolean
+
+ required:
+ - reg
+ - clocks
+ - clock-names
+ - "#phy-cells"
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8173-clk.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/phy/phy.h>
+ susb: usb@11271000 {
+ compatible = "mediatek,mt8173-mtu3";
+ reg = <0x11271000 0x3000>, <0x11280700 0x0100>;
+ reg-names = "mac", "ippc";
+ phys = <&u2port0 PHY_TYPE_USB2>,
+ <&u3port0 PHY_TYPE_USB3>,
+ <&u2port1 PHY_TYPE_USB2>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ u3phy: t-phy@11290000 {
+ compatible = "mediatek,mt8173-u3phy";
+ reg = <0x11290000 0x800>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ status = "okay";
+
+ u2port0: usb-phy@11290800 {
+ reg = <0x11290800 0x100>;
+ clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+
+ u3port0: usb-phy@11290900 {
+ reg = <0x11290900 0x700>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+
+ u2port1: usb-phy@11291000 {
+ reg = <0x11291000 0x100>;
+ clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+ };
+
+#Layout differences of banks between mt8173/mt2701 and mt2712
+#-------------------------------------------------------------
+#mt8173 and mt2701:
+#port offset bank
+#shared 0x0000 SPLLC
+# 0x0100 FMREG
+#u2 port0 0x0800 U2PHY_COM
+#u3 port0 0x0900 U3PHYD
+# 0x0a00 U3PHYD_BANK2
+# 0x0b00 U3PHYA
+# 0x0c00 U3PHYA_DA
+#u2 port1 0x1000 U2PHY_COM
+#u3 port1 0x1100 U3PHYD
+# 0x1200 U3PHYD_BANK2
+# 0x1300 U3PHYA
+# 0x1400 U3PHYA_DA
+#u2 port2 0x1800 U2PHY_COM
+# ...
+#
+#mt2712:
+#port offset bank
+#u2 port0 0x0000 MISC
+# 0x0100 FMREG
+# 0x0300 U2PHY_COM
+#u3 port0 0x0700 SPLLC
+# 0x0800 CHIP
+# 0x0900 U3PHYD
+# 0x0a00 U3PHYD_BANK2
+# 0x0b00 U3PHYA
+# 0x0c00 U3PHYA_DA
+#u2 port1 0x1000 MISC
+# 0x1100 FMREG
+# 0x1300 U2PHY_COM
+#u3 port1 0x1700 SPLLC
+# 0x1800 CHIP
+# 0x1900 U3PHYD
+# 0x1a00 U3PHYD_BANK2
+# 0x1b00 U3PHYA
+# 0x1c00 U3PHYA_DA
+#u2 port2 0x2000 MISC
+# ...
+#
+#SPLLC shared by u3 ports and FMREG shared by u2 ports on
+#mt8173/mt2701 are put back into each port; a new bank MISC for
+#u2 ports and CHIP for u3 ports are added on mt2712.
+
+...
diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
deleted file mode 100644
index dd75b676b71d..000000000000
--- a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
+++ /dev/null
@@ -1,162 +0,0 @@
-MediaTek T-PHY binding
---------------------------
-
-T-phy controller supports physical layer functionality for a number of
-controllers on MediaTek SoCs, such as, USB2.0, USB3.0, PCIe, and SATA.
-
-Required properties (controller (parent) node):
- - compatible : should be one of
- "mediatek,generic-tphy-v1"
- "mediatek,generic-tphy-v2"
- "mediatek,mt2701-u3phy" (deprecated)
- "mediatek,mt2712-u3phy" (deprecated)
- "mediatek,mt8173-u3phy";
- make use of "mediatek,generic-tphy-v1" on mt2701 instead and
- "mediatek,generic-tphy-v2" on mt2712 instead.
-
-- #address-cells: the number of cells used to represent physical
- base addresses.
-- #size-cells: the number of cells used to represent the size of an address.
-- ranges: the address mapping relationship to the parent, defined with
- - empty value: if optional 'reg' is used.
- - non-empty value: if optional 'reg' is not used. should set
- the child's base address to 0, the physical address
- within parent's address space, and the length of
- the address map.
-
-Required nodes : a sub-node is required for each port the controller
- provides. Address range information including the usual
- 'reg' property is used inside these nodes to describe
- the controller's topology.
-
-Optional properties (controller (parent) node):
- - reg : offset and length of register shared by multiple ports,
- exclude port's private register. It is needed on mt2701
- and mt8173, but not on mt2712.
- - mediatek,src-ref-clk-mhz : frequency of reference clock for slew rate
- calibrate
- - mediatek,src-coef : coefficient for slew rate calibrate, depends on
- SoC process
-
-Required properties (port (child) node):
-- reg : address and length of the register set for the port.
-- #phy-cells : should be 1 (See second example)
- cell after port phandle is phy type from:
- - PHY_TYPE_USB2
- - PHY_TYPE_USB3
- - PHY_TYPE_PCIE
- - PHY_TYPE_SATA
-
-Optional properties (PHY_TYPE_USB2 port (child) node):
-- clocks : a list of phandle + clock-specifier pairs, one for each
- entry in clock-names
-- clock-names : may contain
- "ref": 48M reference clock for HighSpeed (digital) phy; and 26M
- reference clock for SuperSpeed (digital) phy, sometimes is
- 24M, 25M or 27M, depended on platform.
- "da_ref": the reference clock of analog phy, used if the clocks
- of analog and digital phys are separated, otherwise uses
- "ref" clock only if needed.
-
-- mediatek,eye-src : u32, the value of slew rate calibrate
-- mediatek,eye-vrt : u32, the selection of VRT reference voltage
-- mediatek,eye-term : u32, the selection of HS_TX TERM reference voltage
-- mediatek,bc12 : bool, enable BC12 of u2phy if support it
-- mediatek,discth : u32, the selection of disconnect threshold
-- mediatek,intr : u32, the selection of internal R (resistance)
-
-Example:
-
-u3phy: usb-phy@11290000 {
- compatible = "mediatek,mt8173-u3phy";
- reg = <0 0x11290000 0 0x800>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- u2port0: usb-phy@11290800 {
- reg = <0 0x11290800 0 0x100>;
- clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
- clock-names = "ref";
- #phy-cells = <1>;
- };
-
- u3port0: usb-phy@11290900 {
- reg = <0 0x11290800 0 0x700>;
- clocks = <&clk26m>;
- clock-names = "ref";
- #phy-cells = <1>;
- };
-
- u2port1: usb-phy@11291000 {
- reg = <0 0x11291000 0 0x100>;
- clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
- clock-names = "ref";
- #phy-cells = <1>;
- };
-};
-
-Specifying phy control of devices
----------------------------------
-
-Device nodes should specify the configuration required in their "phys"
-property, containing a phandle to the phy port node and a device type;
-phy-names for each port are optional.
-
-Example:
-
-#include <dt-bindings/phy/phy.h>
-
-usb30: usb@11270000 {
- ...
- phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
- phy-names = "usb2-0", "usb3-0";
- ...
-};
-
-
-Layout differences of banks between mt8173/mt2701 and mt2712
--------------------------------------------------------------
-mt8173 and mt2701:
-port offset bank
-shared 0x0000 SPLLC
- 0x0100 FMREG
-u2 port0 0x0800 U2PHY_COM
-u3 port0 0x0900 U3PHYD
- 0x0a00 U3PHYD_BANK2
- 0x0b00 U3PHYA
- 0x0c00 U3PHYA_DA
-u2 port1 0x1000 U2PHY_COM
-u3 port1 0x1100 U3PHYD
- 0x1200 U3PHYD_BANK2
- 0x1300 U3PHYA
- 0x1400 U3PHYA_DA
-u2 port2 0x1800 U2PHY_COM
- ...
-
-mt2712:
-port offset bank
-u2 port0 0x0000 MISC
- 0x0100 FMREG
- 0x0300 U2PHY_COM
-u3 port0 0x0700 SPLLC
- 0x0800 CHIP
- 0x0900 U3PHYD
- 0x0a00 U3PHYD_BANK2
- 0x0b00 U3PHYA
- 0x0c00 U3PHYA_DA
-u2 port1 0x1000 MISC
- 0x1100 FMREG
- 0x1300 U2PHY_COM
-u3 port1 0x1700 SPLLC
- 0x1800 CHIP
- 0x1900 U3PHYD
- 0x1a00 U3PHYD_BANK2
- 0x1b00 U3PHYA
- 0x1c00 U3PHYA_DA
-u2 port2 0x2000 MISC
- ...
-
- SPLLC shared by u3 ports and FMREG shared by u2 ports on
-mt8173/mt2701 are put back into each port; a new bank MISC for
-u2 ports and CHIP for u3 ports are added on mt2712.
--
2.18.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 3/4] dt-bindings: phy: convert phy-mtk-ufs.txt to YAML schema
2020-09-22 7:55 [PATCH 1/4] dt-bindings: phy: convert phy-mtk-xsphy.txt to YAML schema Chunfeng Yun
2020-09-22 7:55 ` [PATCH 2/4] dt-bindings: phy: convert phy-mtk-tphy.txt " Chunfeng Yun
@ 2020-09-22 7:55 ` Chunfeng Yun
2020-09-22 16:07 ` Rob Herring
2020-09-22 7:55 ` [PATCH 4/4] dt-bindings: phy: convert HDMI PHY binding " Chunfeng Yun
2020-09-29 18:08 ` [PATCH 1/4] dt-bindings: phy: convert phy-mtk-xsphy.txt " Rob Herring
3 siblings, 1 reply; 8+ messages in thread
From: Chunfeng Yun @ 2020-09-22 7:55 UTC (permalink / raw)
To: Chun-Kuang Hu, Rob Herring, Kishon Vijay Abraham I, Stanley Chu
Cc: Philipp Zabel, David Airlie, Daniel Vetter, Vinod Koul,
Chunfeng Yun, Matthias Brugger, CK Hu, dri-devel, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek
Convert phy-mtk-ufs.txt to YAML schema mediatek,ufs-phy.yaml
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
.../bindings/phy/mediatek,ufs-phy.yaml | 64 +++++++++++++++++++
.../devicetree/bindings/phy/phy-mtk-ufs.txt | 38 -----------
2 files changed, 64 insertions(+), 38 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml
delete mode 100644 Documentation/devicetree/bindings/phy/phy-mtk-ufs.txt
diff --git a/Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml
new file mode 100644
index 000000000000..629819d7f1c8
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2020 MediaTek
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/mediatek,ufs-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Universal Flash Storage (UFS) M-PHY binding
+
+maintainers:
+ - Stanley Chu <stanley.chu@mediatek.com>
+ - Chunfeng Yun <chunfeng.yun@mediatek.com>
+
+description: |
+ UFS M-PHY nodes are defined to describe on-chip UFS M-PHY hardware macro.
+ Each UFS M-PHY node should have its own node.
+ To bind UFS M-PHY with UFS host controller, the controller node should
+ contain a phandle reference to UFS M-PHY node.
+
+properties:
+ $nodename:
+ pattern: "^ufs-phy@[0-9a-f]+$"
+
+ compatible:
+ const: mediatek,mt8183-ufsphy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Unipro core control clock.
+ - description: M-PHY core control clock.
+
+ clock-names:
+ items:
+ - const: unipro
+ - const: mp
+
+ "#phy-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - "#phy-cells"
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8183-clk.h>
+ ufsphy: ufs-phy@11fa0000 {
+ compatible = "mediatek,mt8183-ufsphy";
+ reg = <0 0x11fa0000 0 0xc000>;
+ clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
+ <&infracfg CLK_INFRA_UFS_MP_SAP_BCLK>;
+ clock-names = "unipro", "mp";
+ #phy-cells = <0>;
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-ufs.txt b/Documentation/devicetree/bindings/phy/phy-mtk-ufs.txt
deleted file mode 100644
index 5789029a1d42..000000000000
--- a/Documentation/devicetree/bindings/phy/phy-mtk-ufs.txt
+++ /dev/null
@@ -1,38 +0,0 @@
-MediaTek Universal Flash Storage (UFS) M-PHY binding
---------------------------------------------------------
-
-UFS M-PHY nodes are defined to describe on-chip UFS M-PHY hardware macro.
-Each UFS M-PHY node should have its own node.
-
-To bind UFS M-PHY with UFS host controller, the controller node should
-contain a phandle reference to UFS M-PHY node.
-
-Required properties for UFS M-PHY nodes:
-- compatible : Compatible list, contains the following controller:
- "mediatek,mt8183-ufsphy" for ufs phy
- persent on MT81xx chipsets.
-- reg : Address and length of the UFS M-PHY register set.
-- #phy-cells : This property shall be set to 0.
-- clocks : List of phandle and clock specifier pairs.
-- clock-names : List of clock input name strings sorted in the same
- order as the clocks property. Following clocks are
- mandatory.
- "unipro": Unipro core control clock.
- "mp": M-PHY core control clock.
-
-Example:
-
- ufsphy: phy@11fa0000 {
- compatible = "mediatek,mt8183-ufsphy";
- reg = <0 0x11fa0000 0 0xc000>;
- #phy-cells = <0>;
-
- clocks = <&infracfg_ao INFRACFG_AO_UNIPRO_SCK_CG>,
- <&infracfg_ao INFRACFG_AO_UFS_MP_SAP_BCLK_CG>;
- clock-names = "unipro", "mp";
- };
-
- ufshci@11270000 {
- ...
- phys = <&ufsphy>;
- };
--
2.18.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 4/4] dt-bindings: phy: convert HDMI PHY binding to YAML schema
2020-09-22 7:55 [PATCH 1/4] dt-bindings: phy: convert phy-mtk-xsphy.txt to YAML schema Chunfeng Yun
2020-09-22 7:55 ` [PATCH 2/4] dt-bindings: phy: convert phy-mtk-tphy.txt " Chunfeng Yun
2020-09-22 7:55 ` [PATCH 3/4] dt-bindings: phy: convert phy-mtk-ufs.txt " Chunfeng Yun
@ 2020-09-22 7:55 ` Chunfeng Yun
2020-09-22 16:07 ` Rob Herring
2020-09-29 18:08 ` [PATCH 1/4] dt-bindings: phy: convert phy-mtk-xsphy.txt " Rob Herring
3 siblings, 1 reply; 8+ messages in thread
From: Chunfeng Yun @ 2020-09-22 7:55 UTC (permalink / raw)
To: Chun-Kuang Hu, Rob Herring, Kishon Vijay Abraham I, Stanley Chu
Cc: Philipp Zabel, David Airlie, Daniel Vetter, Vinod Koul,
Chunfeng Yun, Matthias Brugger, CK Hu, dri-devel, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek
Convert HDMI PHY binding to YAML schema mediatek,ufs-phy.yaml
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
.../display/mediatek/mediatek,hdmi.txt | 17 +---
.../bindings/phy/mediatek,hdmi-phy.yaml | 90 +++++++++++++++++++
2 files changed, 91 insertions(+), 16 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
index 7b124242b0c5..edac18951a75 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
@@ -50,22 +50,7 @@ Required properties:
HDMI PHY
========
-
-The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
-output and drives the HDMI pads.
-
-Required properties:
-- compatible: "mediatek,<chip>-hdmi-phy"
-- reg: Physical base address and length of the module's registers
-- clocks: PLL reference clock
-- clock-names: must contain "pll_ref"
-- clock-output-names: must be "hdmitx_dig_cts" on mt8173
-- #phy-cells: must be <0>
-- #clock-cells: must be <0>
-
-Optional properties:
-- mediatek,ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa
-- mediatek,ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c
+See phy/mediatek,hdmi-phy.yaml
Example:
diff --git a/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml
new file mode 100644
index 000000000000..679b4005ee62
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml
@@ -0,0 +1,90 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2020 MediaTek
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek High Definition Multimedia Interface (HDMI) PHY binding
+
+maintainers:
+ - CK Hu <ck.hu@mediatek.com>
+ - Chunfeng Yun <chunfeng.yun@mediatek.com>
+
+description: |
+ The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
+ output and drives the HDMI pads.
+
+properties:
+ $nodename:
+ pattern: "^hdmi-phy@[0-9a-f]+$"
+
+ compatible:
+ enum:
+ - mediatek,mt2701-hdmi-phy
+ - mediatek,mt8173-hdmi-phy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: PLL reference clock
+
+ clock-names:
+ items:
+ - const: pll_ref
+
+ clock-output-names:
+ items:
+ - const: hdmitx_dig_cts
+
+ "#phy-cells":
+ const: 0
+
+ "#clock-cells":
+ const: 0
+
+ mediatek,ibias:
+ description:
+ TX DRV bias current for < 1.65Gbps
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 63
+ default: 0xa
+
+ mediatek,ibias_up:
+ description:
+ TX DRV bias current for >= 1.65Gbps
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 63
+ default: 0x1c
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - clock-output-names
+ - "#phy-cells"
+ - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8173-clk.h>
+ hdmi_phy: hdmi-phy@10209100 {
+ compatible = "mediatek,mt8173-hdmi-phy";
+ reg = <0 0x10209100 0 0x24>;
+ clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
+ clock-names = "pll_ref";
+ clock-output-names = "hdmitx_dig_cts";
+ mediatek,ibias = <0xa>;
+ mediatek,ibias_up = <0x1c>;
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ };
+
+...
--
2.18.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 2/4] dt-bindings: phy: convert phy-mtk-tphy.txt to YAML schema
2020-09-22 7:55 ` [PATCH 2/4] dt-bindings: phy: convert phy-mtk-tphy.txt " Chunfeng Yun
@ 2020-09-22 16:04 ` Rob Herring
0 siblings, 0 replies; 8+ messages in thread
From: Rob Herring @ 2020-09-22 16:04 UTC (permalink / raw)
To: Chunfeng Yun
Cc: linux-kernel, Philipp Zabel, linux-arm-kernel, Stanley Chu,
David Airlie, Matthias Brugger, CK Hu, linux-mediatek,
Kishon Vijay Abraham I, Daniel Vetter, Vinod Koul, dri-devel,
Chun-Kuang Hu, devicetree, Rob Herring
On Tue, 22 Sep 2020 15:55:06 +0800, Chunfeng Yun wrote:
> Convert phy-mtk-tphy.txt to YAML schema mediatek,tphy.yaml
>
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
> .../bindings/phy/mediatek,tphy.yaml | 260 ++++++++++++++++++
> .../devicetree/bindings/phy/phy-mtk-tphy.txt | 162 -----------
> 2 files changed, 260 insertions(+), 162 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
> delete mode 100644 Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
>
My bot found errors running 'make dt_binding_check' on your patch:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/mediatek,tphy.example.dt.yaml: t-phy@11290000: usb-phy@11290800:clocks: [[4294967295, 15]] is too short
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/mediatek,tphy.example.dt.yaml: t-phy@11290000: usb-phy@11290800:clock-names: ['ref'] is too short
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/mediatek,tphy.example.dt.yaml: t-phy@11290000: usb-phy@11290900:clocks: [[4294967295]] is too short
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/mediatek,tphy.example.dt.yaml: t-phy@11290000: usb-phy@11290900:clock-names: ['ref'] is too short
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/mediatek,tphy.example.dt.yaml: t-phy@11290000: usb-phy@11291000:clocks: [[4294967295, 15]] is too short
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/mediatek,tphy.example.dt.yaml: t-phy@11290000: usb-phy@11291000:clock-names: ['ref'] is too short
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
See https://patchwork.ozlabs.org/patch/1368817
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure dt-schema is up to date:
pip3 install git+https://github.com/devicetree-org/dt-schema.git@master --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 3/4] dt-bindings: phy: convert phy-mtk-ufs.txt to YAML schema
2020-09-22 7:55 ` [PATCH 3/4] dt-bindings: phy: convert phy-mtk-ufs.txt " Chunfeng Yun
@ 2020-09-22 16:07 ` Rob Herring
0 siblings, 0 replies; 8+ messages in thread
From: Rob Herring @ 2020-09-22 16:07 UTC (permalink / raw)
To: Chunfeng Yun
Cc: linux-mediatek, Kishon Vijay Abraham I, Chun-Kuang Hu,
Vinod Koul, Stanley Chu, Matthias Brugger, CK Hu,
linux-arm-kernel, Rob Herring, devicetree, David Airlie,
Philipp Zabel, Daniel Vetter, linux-kernel, dri-devel
On Tue, 22 Sep 2020 15:55:07 +0800, Chunfeng Yun wrote:
> Convert phy-mtk-ufs.txt to YAML schema mediatek,ufs-phy.yaml
>
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
> .../bindings/phy/mediatek,ufs-phy.yaml | 64 +++++++++++++++++++
> .../devicetree/bindings/phy/phy-mtk-ufs.txt | 38 -----------
> 2 files changed, 64 insertions(+), 38 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml
> delete mode 100644 Documentation/devicetree/bindings/phy/phy-mtk-ufs.txt
>
My bot found errors running 'make dt_binding_check' on your patch:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/mediatek,ufs-phy.example.dt.yaml: example-0: ufs-phy@11fa0000:reg:0: [0, 301596672, 0, 49152] is too long
From schema: /usr/local/lib/python3.8/dist-packages/dtschema/schemas/reg.yaml
See https://patchwork.ozlabs.org/patch/1368813
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure dt-schema is up to date:
pip3 install git+https://github.com/devicetree-org/dt-schema.git@master --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 4/4] dt-bindings: phy: convert HDMI PHY binding to YAML schema
2020-09-22 7:55 ` [PATCH 4/4] dt-bindings: phy: convert HDMI PHY binding " Chunfeng Yun
@ 2020-09-22 16:07 ` Rob Herring
0 siblings, 0 replies; 8+ messages in thread
From: Rob Herring @ 2020-09-22 16:07 UTC (permalink / raw)
To: Chunfeng Yun
Cc: linux-kernel, David Airlie, Daniel Vetter, linux-mediatek,
Rob Herring, Matthias Brugger, linux-arm-kernel, devicetree,
Kishon Vijay Abraham I, Vinod Koul, Chun-Kuang Hu, dri-devel,
Philipp Zabel, CK Hu, Stanley Chu
On Tue, 22 Sep 2020 15:55:08 +0800, Chunfeng Yun wrote:
> Convert HDMI PHY binding to YAML schema mediatek,ufs-phy.yaml
>
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
> .../display/mediatek/mediatek,hdmi.txt | 17 +---
> .../bindings/phy/mediatek,hdmi-phy.yaml | 90 +++++++++++++++++++
> 2 files changed, 91 insertions(+), 16 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml
>
My bot found errors running 'make dt_binding_check' on your patch:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.example.dt.yaml: example-0: hdmi-phy@10209100:reg:0: [0, 270569728, 0, 36] is too long
From schema: /usr/local/lib/python3.8/dist-packages/dtschema/schemas/reg.yaml
See https://patchwork.ozlabs.org/patch/1368816
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure dt-schema is up to date:
pip3 install git+https://github.com/devicetree-org/dt-schema.git@master --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/4] dt-bindings: phy: convert phy-mtk-xsphy.txt to YAML schema
2020-09-22 7:55 [PATCH 1/4] dt-bindings: phy: convert phy-mtk-xsphy.txt to YAML schema Chunfeng Yun
` (2 preceding siblings ...)
2020-09-22 7:55 ` [PATCH 4/4] dt-bindings: phy: convert HDMI PHY binding " Chunfeng Yun
@ 2020-09-29 18:08 ` Rob Herring
3 siblings, 0 replies; 8+ messages in thread
From: Rob Herring @ 2020-09-29 18:08 UTC (permalink / raw)
To: Chunfeng Yun
Cc: Chun-Kuang Hu, Kishon Vijay Abraham I, Stanley Chu,
Philipp Zabel, David Airlie, Daniel Vetter, Vinod Koul,
Matthias Brugger, CK Hu, dri-devel, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek
On Tue, Sep 22, 2020 at 03:55:05PM +0800, Chunfeng Yun wrote:
> Convert phy-mtk-xsphy.txt to YAML schema mediatek,xsphy.yaml
>
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
> .../bindings/phy/mediatek,xsphy.yaml | 203 ++++++++++++++++++
> .../devicetree/bindings/phy/phy-mtk-xsphy.txt | 109 ----------
> 2 files changed, 203 insertions(+), 109 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml
> delete mode 100644 Documentation/devicetree/bindings/phy/phy-mtk-xsphy.txt
>
> diff --git a/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml
> new file mode 100644
> index 000000000000..0aaa10640b5a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml
> @@ -0,0 +1,203 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (c) 2020 MediaTek
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/mediatek,xsphy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek XS-PHY Controller Device Tree Bindings
> +
> +maintainers:
> + - Chunfeng Yun <chunfeng.yun@mediatek.com>
> +
> +description: |
> + The XS-PHY controller supports physical layer functionality for USB3.1
> + GEN2 controller on MediaTek SoCs.
> +
> +properties:
> + $nodename:
> + pattern: "^xs-phy@[0-9a-f]+$"
> +
> + compatible:
> + oneOf:
> + - items:
> + - enum:
> + - mediatek,mt3611-xsphy
> + - enum:
> + - mediatek,xsphy
> + - items:
> + - const: mediatek,xsphy
mediatek,xsphy alone should not be valid.
> +
> + reg:
> + description: |
> + Register shared by multiple U3 ports, exclude port's private register,
> + if only U2 ports provided, shouldn't use the property.
> + maxItems: 1
> +
> + "#address-cells":
> + enum: [1, 2]
> +
> + "#size-cells":
> + enum: [1, 2]
> +
> + ranges: true
> +
> + mediatek,src-ref-clk-mhz:
> + description:
> + Frequency of reference clock for slew rate calibrate
> + $ref: /schemas/types.yaml#/definitions/uint32
> + default: 26
> +
> + mediatek,src-coef:
> + description:
> + Coefficient for slew rate calibrate, depends on SoC process
> + $ref: /schemas/types.yaml#/definitions/uint32
> + default: 17
> +
> +# Required child node:
> +patternProperties:
> + "^usb-phy@[0-9a-f]+$":
> + type: object
> + description: |
> + A sub-node is required for each port the controller provides.
> + Address range information including the usual 'reg' property
> + is used inside these nodes to describe the controller's topology.
> +
> + properties:
> + reg:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz)
> +
> + clock-names:
> + items:
> + - const: ref
> +
> + "#phy-cells":
> + const: 1
> + description: |
> + The cells contain the following arguments.
> +
> + - description: The PHY type
> + enum:
> + - PHY_TYPE_USB2
> + - PHY_TYPE_USB3
> +
> + #The following optional vendor properties are only for debug or HQA test
> + mediatek,eye-src:
> + description:
> + The value of slew rate calibrate (U2 phy)
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 1
> + maximum: 7
> +
> + mediatek,eye-vrt:
> + description:
> + The selection of VRT reference voltage (U2 phy)
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 1
> + maximum: 7
> +
> + mediatek,eye-term:
> + description:
> + The selection of HS_TX TERM reference voltage (U2 phy)
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 1
> + maximum: 7
> +
> + mediatek,efuse-intr:
> + description:
> + The selection of Internal Resistor (U2/U3 phy)
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 1
> + maximum: 63
> +
> + mediatek,efuse-tx-imp:
> + description:
> + The selection of TX Impedance (U3 phy)
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 1
> + maximum: 31
> +
> + mediatek,efuse-rx-imp:
> + description:
> + The selection of RX Impedance (U3 phy)
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 1
> + maximum: 31
> +
> + required:
> + - reg
> + - clocks
> + - clock-names
> + - "#phy-cells"
> +
> + additionalProperties: false
> +
> +required:
> + - compatible
> + - "#address-cells"
> + - "#size-cells"
> + - ranges
> +
> +additionalProperties: false
> +
> +#Banks layout of xsphy
> +#-------------------------------------------------------------
Move this to top-level 'description'.
> +#port offset bank
> +#u2 port0 0x0000 MISC
> +# 0x0100 FMREG
> +# 0x0300 U2PHY_COM
> +#u2 port1 0x1000 MISC
> +# 0x1100 FMREG
> +# 0x1300 U2PHY_COM
> +#u2 port2 0x2000 MISC
> +# ...
> +#u31 common 0x3000 DIG_GLB
> +# 0x3100 PHYA_GLB
> +#u31 port0 0x3400 DIG_LN_TOP
> +# 0x3500 DIG_LN_TX0
> +# 0x3600 DIG_LN_RX0
> +# 0x3700 DIG_LN_DAIF
> +# 0x3800 PHYA_LN
> +#u31 port1 0x3a00 DIG_LN_TOP
> +# 0x3b00 DIG_LN_TX0
> +# 0x3c00 DIG_LN_RX0
> +# 0x3d00 DIG_LN_DAIF
> +# 0x3e00 PHYA_LN
> +# ...
> +#DIG_GLB & PHYA_GLB are shared by U31 ports.
> +
> +examples:
> + - |
> + #include <dt-bindings/phy/phy.h>
> +
> + u3phy: xs-phy@11c40000 {
> + compatible = "mediatek,mt3611-xsphy", "mediatek,xsphy";
> + reg = <0x11c43000 0x0200>;
> + mediatek,src-ref-clk-mhz = <26>;
> + mediatek,src-coef = <17>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + u2port0: usb-phy@11c40000 {
> + reg = <0x11c40000 0x0400>;
> + clocks = <&clk48m>;
> + clock-names = "ref";
> + mediatek,eye-src = <4>;
> + #phy-cells = <1>;
> + };
> +
> + u3port0: usb-phy@11c43000 {
> + reg = <0x11c43400 0x0500>;
> + clocks = <&clk26m>;
> + clock-names = "ref";
> + mediatek,efuse-intr = <28>;
> + #phy-cells = <1>;
> + };
> + };
> +
> +...
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2020-09-29 18:08 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-09-22 7:55 [PATCH 1/4] dt-bindings: phy: convert phy-mtk-xsphy.txt to YAML schema Chunfeng Yun
2020-09-22 7:55 ` [PATCH 2/4] dt-bindings: phy: convert phy-mtk-tphy.txt " Chunfeng Yun
2020-09-22 16:04 ` Rob Herring
2020-09-22 7:55 ` [PATCH 3/4] dt-bindings: phy: convert phy-mtk-ufs.txt " Chunfeng Yun
2020-09-22 16:07 ` Rob Herring
2020-09-22 7:55 ` [PATCH 4/4] dt-bindings: phy: convert HDMI PHY binding " Chunfeng Yun
2020-09-22 16:07 ` Rob Herring
2020-09-29 18:08 ` [PATCH 1/4] dt-bindings: phy: convert phy-mtk-xsphy.txt " Rob Herring
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