From: David Laight <David.Laight@ACULAB.COM>
To: 'Akira Tsukamoto' <akira.tsukamoto@gmail.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>
Subject: RE: [PATCH 5/5] riscv: __asm_to/copy_from_user: Bulk copy when both src, dst are aligned
Date: Mon, 21 Jun 2021 11:55:37 +0000 [thread overview]
Message-ID: <4a847070ad494e839de1d3fc5b39ba57@AcuMS.aculab.com> (raw)
In-Reply-To: <4637f0f2-2da9-1056-37bf-17c0861b6bff@gmail.com>
From: Akira Tsukamoto
> Sent: 19 June 2021 12:43
>
> In the lucky situation that the both source and destination address are on
> the aligned boundary, perform load and store with register size to copy the
> data.
>
> Without the unrolling, it will reduce the speed since the next store
> instruction for the same register using from the load will stall the
> pipeline.
...
> diff --git a/arch/riscv/lib/uaccess.S b/arch/riscv/lib/uaccess.S
> index e2e57551fc76..bceb0629e440 100644
> --- a/arch/riscv/lib/uaccess.S
> +++ b/arch/riscv/lib/uaccess.S
> @@ -67,6 +67,39 @@ ENTRY(__asm_copy_from_user)
> bnez a3, .Lshift_copy
>
> .Lword_copy:
> + /*
> + * Both src and dst are aligned, unrolled word copy
> + *
> + * a0 - start of aligned dst
> + * a1 - start of aligned src
> + * a3 - a1 & mask:(SZREG-1)
> + * t0 - end of aligned dst
> + */
> + addi t0, t0, -(8*SZREG-1) /* not to over run */
> +2:
> + fixup REG_L a4, 0(a1), 10f
> + fixup REG_L a5, SZREG(a1), 10f
> + fixup REG_L a6, 2*SZREG(a1), 10f
> + fixup REG_L a7, 3*SZREG(a1), 10f
> + fixup REG_L t1, 4*SZREG(a1), 10f
> + fixup REG_L t2, 5*SZREG(a1), 10f
> + fixup REG_L t3, 6*SZREG(a1), 10f
> + fixup REG_L t4, 7*SZREG(a1), 10f
> + fixup REG_S a4, 0(a0), 10f
> + fixup REG_S a5, SZREG(a0), 10f
> + fixup REG_S a6, 2*SZREG(a0), 10f
> + fixup REG_S a7, 3*SZREG(a0), 10f
> + fixup REG_S t1, 4*SZREG(a0), 10f
> + fixup REG_S t2, 5*SZREG(a0), 10f
> + fixup REG_S t3, 6*SZREG(a0), 10f
> + fixup REG_S t4, 7*SZREG(a0), 10f
> + addi a0, a0, 8*SZREG
> + addi a1, a1, 8*SZREG
> + bltu a0, t0, 2b
> +
> + addi t0, t0, 8*SZREG-1 /* revert to original value */
> + j .Lbyte_copy_tail
> +
Are there any riscv chips than can do a memory read and a
memory write int the same cycle but don't have significant
'out of order' execution?
Such chips will execute that code very badly.
Or, rather, there are loops that allow concurrent read+write
that will be a lot faster.
Also on a cpu that can execute a memory read/write
at the same time as an add (probably anything supercaler)
you want to move the two 'addi' further up so they get
executed 'for free'.
David
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Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK
Registration No: 1397386 (Wales)
next prev parent reply other threads:[~2021-06-21 11:55 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-19 11:21 [PATCH v2 0/5] riscv: improving uaccess with logs from network bench Akira Tsukamoto
2021-06-19 11:34 ` [PATCH 1/5] riscv: __asm_to/copy_from_user: delete existing code Akira Tsukamoto
2021-06-21 11:45 ` David Laight
2021-06-21 13:55 ` Akira Tsukamoto
2021-06-19 11:35 ` [PATCH 2/5] riscv: __asm_to/copy_from_user: Adding byte copy first Akira Tsukamoto
2021-06-19 11:36 ` [PATCH 3/5] riscv: __asm_to/copy_from_user: Copy until dst is aligned Akira Tsukamoto
2021-06-19 11:37 ` [PATCH 4/5] riscv: __asm_to/copy_from_user: Bulk copy while shifting Akira Tsukamoto
2021-06-19 11:43 ` [PATCH 5/5] riscv: __asm_to/copy_from_user: Bulk copy when both src, dst are aligned Akira Tsukamoto
2021-06-21 11:55 ` David Laight [this message]
2021-06-21 14:13 ` Akira Tsukamoto
2021-06-20 10:02 ` [PATCH v2 0/5] riscv: improving uaccess with logs from network bench Ben Dooks
2021-06-20 16:36 ` Akira Tsukamoto
2021-06-22 8:30 ` Ben Dooks
2021-06-22 12:05 ` Akira Tsukamoto
2021-06-22 17:45 ` Ben Dooks
2021-07-12 21:24 ` Ben Dooks
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