* [PATCH bpf-next] arm64: bpf: optimize modulo operation
@ 2019-09-02 6:14 jerinj
2019-09-03 14:05 ` Daniel Borkmann
0 siblings, 1 reply; 2+ messages in thread
From: jerinj @ 2019-09-02 6:14 UTC (permalink / raw)
To: netdev, Daniel Borkmann, Alexei Starovoitov, Zi Shen Lim,
Catalin Marinas, Will Deacon, Martin KaFai Lau, Song Liu,
Yonghong Song, open list:BPF JIT for ARM64,
moderated list:ARM64 PORT (AARCH64 ARCHITECTURE),
open list
Cc: Jerin Jacob
From: Jerin Jacob <jerinj@marvell.com>
Optimize modulo operation instruction generation by
using single MSUB instruction vs MUL followed by SUB
instruction scheme.
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
---
arch/arm64/net/bpf_jit.h | 3 +++
arch/arm64/net/bpf_jit_comp.c | 6 ++----
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/net/bpf_jit.h b/arch/arm64/net/bpf_jit.h
index cb7ab50b7657..eb73f9f72c46 100644
--- a/arch/arm64/net/bpf_jit.h
+++ b/arch/arm64/net/bpf_jit.h
@@ -171,6 +171,9 @@
/* Rd = Ra + Rn * Rm */
#define A64_MADD(sf, Rd, Ra, Rn, Rm) aarch64_insn_gen_data3(Rd, Ra, Rn, Rm, \
A64_VARIANT(sf), AARCH64_INSN_DATA3_MADD)
+/* Rd = Ra - Rn * Rm */
+#define A64_MSUB(sf, Rd, Ra, Rn, Rm) aarch64_insn_gen_data3(Rd, Ra, Rn, Rm, \
+ A64_VARIANT(sf), AARCH64_INSN_DATA3_MSUB)
/* Rd = Rn * Rm */
#define A64_MUL(sf, Rd, Rn, Rm) A64_MADD(sf, Rd, A64_ZR, Rn, Rm)
diff --git a/arch/arm64/net/bpf_jit_comp.c b/arch/arm64/net/bpf_jit_comp.c
index f5b437f8a22b..cdc79de0c794 100644
--- a/arch/arm64/net/bpf_jit_comp.c
+++ b/arch/arm64/net/bpf_jit_comp.c
@@ -409,8 +409,7 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx,
break;
case BPF_MOD:
emit(A64_UDIV(is64, tmp, dst, src), ctx);
- emit(A64_MUL(is64, tmp, tmp, src), ctx);
- emit(A64_SUB(is64, dst, dst, tmp), ctx);
+ emit(A64_MSUB(is64, dst, dst, tmp, src), ctx);
break;
}
break;
@@ -516,8 +515,7 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx,
case BPF_ALU64 | BPF_MOD | BPF_K:
emit_a64_mov_i(is64, tmp2, imm, ctx);
emit(A64_UDIV(is64, tmp, dst, tmp2), ctx);
- emit(A64_MUL(is64, tmp, tmp, tmp2), ctx);
- emit(A64_SUB(is64, dst, dst, tmp), ctx);
+ emit(A64_MSUB(is64, dst, dst, tmp, tmp2), ctx);
break;
case BPF_ALU | BPF_LSH | BPF_K:
case BPF_ALU64 | BPF_LSH | BPF_K:
--
2.23.0
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH bpf-next] arm64: bpf: optimize modulo operation
2019-09-02 6:14 [PATCH bpf-next] arm64: bpf: optimize modulo operation jerinj
@ 2019-09-03 14:05 ` Daniel Borkmann
0 siblings, 0 replies; 2+ messages in thread
From: Daniel Borkmann @ 2019-09-03 14:05 UTC (permalink / raw)
To: jerinj, netdev, Alexei Starovoitov, Zi Shen Lim, Catalin Marinas,
Will Deacon, Martin KaFai Lau, Song Liu, Yonghong Song,
open list:BPF JIT for ARM64,
moderated list:ARM64 PORT (AARCH64 ARCHITECTURE),
open list
On 9/2/19 8:14 AM, jerinj@marvell.com wrote:
> From: Jerin Jacob <jerinj@marvell.com>
>
> Optimize modulo operation instruction generation by
> using single MSUB instruction vs MUL followed by SUB
> instruction scheme.
>
> Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Applied, thanks!
^ permalink raw reply [flat|nested] 2+ messages in thread
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