Re: [RFC] x86: mtrr: Constrain WB MTRR to max phys mem prior to cleanup

["H. Peter Anvin" <hpa@zytor.com>]

On 09/07/2012 10:44 AM, Peter Hurley wrote:
\>
> diff --git a/arch/x86/kernel/cpu/mtrr/cleanup.c b/arch/x86/kernel/cpu/mtrr/cleanup.c
> index bdda2e6..ee399c3 100644
> --- a/arch/x86/kernel/cpu/mtrr/cleanup.c
> +++ b/arch/x86/kernel/cpu/mtrr/cleanup.c
> @@ -714,6 +714,16 @@ int __init mtrr_cleanup(unsigned address_bits)
>   	if (mtrr_tom2)
>   		x_remove_size = (mtrr_tom2 >> PAGE_SHIFT) - x_remove_base;
>
> +	/* Constrain a WB entry that maps entire phys addr space to max mem */
> +	for (i = 0; i < num_var_ranges; i++) {
> +		if (range_state[i].type == MTRR_TYPE_WRBACK &&
> +		    range_state[i].base_pfn == 0 &&
> +		    range_state[i].size_pfn > max_pfn) {
> +			range_state[i].size_pfn = roundup_pow_of_two(max_pfn);
> +			break;
> +		}
> +	}
> +

I really don't like it as it introduces yet another user of max_pfn, 
which should be going away.  Furthermore, the better question is what 
remaining needs there are for MTRR cleanup; historically the reason was 
that it prevented the display from being mapped WC via MTRR due to the 
MTRR conflict resolution rules favoring UC.

However, the right way to fix that is to use the PAT interfaces, which 
doesn't have this drawback -- then MTRR cleanup becomes entirely 
superfluous and the problem goes away.

	-hpa

-- 
H. Peter Anvin, Intel Open Source Technology Center
I work for Intel.  I don't speak on their behalf.