From: Laxman Dewangan <ldewangan@nvidia.com>
To: Prashant Gaikwad <pgaikwad@nvidia.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>,
"linux-tegra@vger.kernel.org" <linux-tegra@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 3/4] ARM: tegra: Add OF_DEV_AUXDATA for uart driver in board dt
Date: Tue, 18 Dec 2012 12:30:41 +0530 [thread overview]
Message-ID: <50D01499.1010004@nvidia.com> (raw)
In-Reply-To: <50D00AB9.8090800@nvidia.com>
On Tuesday 18 December 2012 11:48 AM, Prashant Gaikwad wrote:
> On Tuesday 18 December 2012 03:17 AM, Stephen Warren wrote:
>> On 12/17/2012 05:08 AM, Laxman Dewangan wrote:
>>> Add OF_DEV_AUXDATA for high speed uart controller driver for
>>> Tegra20/Tegra30 board dt files.
>>> Set the parent clock of uart controller to PLLP.
>>> diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
>>> @@ -94,6 +94,11 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
>>> + OF_DEV_AUXDATA("nvidia,tegra20-hsuart", 0x70006000, "tegra-uart.0", NULL),
>>> + OF_DEV_AUXDATA("nvidia,tegra20-hsuart", 0x70006040, "tegra-uart.1", NULL),
>>> + OF_DEV_AUXDATA("nvidia,tegra20-hsuart", 0x70006200, "tegra-uart.2", NULL),
>>> + OF_DEV_AUXDATA("nvidia,tegra20-hsuart", 0x70006300, "tegra-uart.3", NULL),
>>> + OF_DEV_AUXDATA("nvidia,tegra20-hsuart", 0x70006400, "tegra-uart.4", NULL),
>> Instead, can we simply get the clocks from device tree? Prashant, how
>> much effort will that be once your clock patches are checked in, or is
>> it already part of those patches?
> It is not part of rework patches, but I will send a patch for it
> immediately after those patches are accepted upstream.
>
>>> @@ -106,7 +111,10 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
>>> static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
>>> /* name parent rate enabled */
>>> { "uarta", "pll_p", 216000000, true },
>>> + { "uartb", "pll_p", 216000000, false },
>>> + { "uartc", "pll_p", 216000000, false },
>>> { "uartd", "pll_p", 216000000, true },
>>> + { "uarte", "pll_p", 216000000, false },
>> Prashant's clock patches remove this table. Please work with him to work
>> out how to deal with that.
> Laxman,
>
> If you want I can include these entries in current tables.
No issue, you can add this in your change.
next prev parent reply other threads:[~2012-12-18 7:00 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-12-17 12:08 [PATCH 0/4] ARM: tegra: add support for highspeed serial driver Laxman Dewangan
2012-12-17 12:08 ` [PATCH 1/4] ARM: tegra30: Add support for Uart clock source divider as 15.1 Laxman Dewangan
2012-12-17 21:43 ` Stephen Warren
2012-12-18 6:14 ` Prashant Gaikwad
2012-12-18 6:24 ` Laxman Dewangan
2012-12-18 7:07 ` Prashant Gaikwad
2012-12-18 13:05 ` Laxman Dewangan
2012-12-17 12:08 ` [PATCH 2/4] ARM: tegra: add connection name for uart clock table Laxman Dewangan
2012-12-17 21:44 ` Stephen Warren
2012-12-18 7:05 ` Laxman Dewangan
2012-12-18 16:55 ` Stephen Warren
2012-12-17 12:08 ` [PATCH 3/4] ARM: tegra: Add OF_DEV_AUXDATA for uart driver in board dt Laxman Dewangan
2012-12-17 21:47 ` Stephen Warren
2012-12-18 6:18 ` Prashant Gaikwad
2012-12-18 7:00 ` Laxman Dewangan [this message]
2012-12-17 12:08 ` [PATCH 4/4] ARM: tegra: dts: add dma requestor and port numbers for serial controller Laxman Dewangan
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