[PATCH v4 00/13] ARM LPAE Fixes - Part 1

[PATCH v4 00/13] ARM LPAE Fixes - Part 1

[Cyril Chemparathy]

This series is a repost of the LPAE related changes in preparation for the
introduction of the Keystone sub-architecture.  The original series has now
been split, and this particular series excludes the earlier changes to the
runtime code patching implementation.  Earlier versions of this series can be
found at [1], [2], [3] and [4].

These patches are also available in git:
git://git.kernel.org/pub/scm/linux/kernel/git/cchemparathy/linux-keystone.git upstream/keystone-lpae-v4

[1] http://comments.gmane.org/gmane.linux.kernel/1341497
[2] http://comments.gmane.org/gmane.linux.kernel/1332069
[3] http://comments.gmane.org/gmane.linux.kernel/1356716
[4] http://comments.gmane.org/gmane.linux.kernel/1362529

Series changelog:

[01/13] ARM: LPAE: use signed arithmetic for mask
[02/13] ARM: LPAE: use phys_addr_t in alloc_init_pud()
[03/13] ARM: LPAE: use phys_addr_t in free_memmap()
  (v4)	unchanged from v3
  (v3)	unchanged from v2
  (v2)	unchanged from v1

[04/13] ARM: LPAE: use phys_addr_t for initrd location
  (v4)	unchanged from v3
  (v3)	unchanged from v2
  (v2)	revert to unsigned long for initrd size

[05/13] ARM: LPAE: use phys_addr_t in switch_mm()
  (v4)  collapse shift and or into a single instruction
  (v3)	remove unnecessary handling for !LPAE in proc-v7-3level
  (v2)	use phys_addr_t instead of u64 in switch_mm()
  (v2)	revert on changes to v6 and v7-2level
  (v2)	fix register mapping for big-endian in v7-3level

[06/13] ARM: LPAE: use 64-bit accessors for TTBR registers
  (v4)  remove unnecessary condition code clobber
  (v3)	remove unnecessary condition code clobber
  (v2)	restore comment in cpu_set_reserved_ttbr0()

[07/13] ARM: LPAE: define ARCH_LOW_ADDRESS_LIMIT for
  (v4)	unchanged from v3
  (v3)	unchanged from v2
  (v2)	unchanged from v1

[08/13] ARM: LPAE: factor out T1SZ and TTBR1 computations
  (v4)  cleanup and move code comments
  (v3)	unchanged from v2
  (v2)	unchanged from v1

[09/13] ARM: LPAE: accomodate >32-bit addresses for page
  (v4)	unchanged from v3
  (v3)	unchanged from v2
  (v2)	apply arch_pgd_shift only on lpae
  (v2)	move arch_pgd_shift definition to asm/memory.h
  (v2)	revert on changes to non-lpae procs
  (v2)	add check to ensure that the pgd physical address is aligned at an
	ARCH_PGD_SHIFT boundary

[10/13] ARM: mm: use physical addresses in highmem sanity
[11/13] ARM: mm: cleanup checks for membank overlap with
[12/13] ARM: mm: clean up membank size limit checks
  (v4)	unchanged from v3
  (v3)	unchanged from v2
  (v2)	unchanged from v1

[13/13] ARM: fix type of PHYS_PFN_OFFSET to unsigned long
  (v4)	introduced here


Cyril Chemparathy (10):
  ARM: LPAE: use signed arithmetic for mask definitions
  ARM: LPAE: use phys_addr_t in switch_mm()
  ARM: LPAE: use 64-bit accessors for TTBR registers
  ARM: LPAE: define ARCH_LOW_ADDRESS_LIMIT for bootmem
  ARM: LPAE: factor out T1SZ and TTBR1 computations
  ARM: LPAE: accomodate >32-bit addresses for page table base
  ARM: mm: use physical addresses in highmem sanity checks
  ARM: mm: cleanup checks for membank overlap with vmalloc area
  ARM: mm: clean up membank size limit checks
  ARM: fix type of PHYS_PFN_OFFSET to unsigned long

Vitaly Andrianov (3):
  ARM: LPAE: use phys_addr_t in alloc_init_pud()
  ARM: LPAE: use phys_addr_t in free_memmap()
  ARM: LPAE: use phys_addr_t for initrd location

 arch/arm/include/asm/memory.h               |   20 +++++++++-
 arch/arm/include/asm/page.h                 |    2 +-
 arch/arm/include/asm/pgtable-3level-hwdef.h |   20 ++++++++++
 arch/arm/include/asm/pgtable-3level.h       |    6 +--
 arch/arm/include/asm/proc-fns.h             |   26 +++++++++----
 arch/arm/kernel/head.S                      |   10 ++---
 arch/arm/kernel/smp.c                       |   11 +++++-
 arch/arm/mm/context.c                       |    9 +----
 arch/arm/mm/init.c                          |   19 +++++-----
 arch/arm/mm/mmu.c                           |   49 +++++++++----------------
 arch/arm/mm/proc-v7-3level.S                |   53 ++++++++++++++-------------
 11 files changed, 132 insertions(+), 93 deletions(-)

-- 
1.7.9.5

[PATCH v4 01/13] ARM: LPAE: use signed arithmetic for mask definitions

[Cyril Chemparathy]

This patch applies to PAGE_MASK, PMD_MASK, and PGDIR_MASK, where forcing
unsigned long math truncates the mask at the 32-bits.  This clearly does bad
things on PAE systems.

This patch fixes this problem by defining these masks as signed quantities.
We then rely on sign extension to do the right thing.

Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Reviewed-by: Nicolas Pitre <nico@linaro.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
---
 arch/arm/include/asm/page.h           |    2 +-
 arch/arm/include/asm/pgtable-3level.h |    6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h
index 812a494..6363f3d 100644
--- a/arch/arm/include/asm/page.h
+++ b/arch/arm/include/asm/page.h
@@ -13,7 +13,7 @@
 /* PAGE_SHIFT determines the page size */
 #define PAGE_SHIFT		12
 #define PAGE_SIZE		(_AC(1,UL) << PAGE_SHIFT)
-#define PAGE_MASK		(~(PAGE_SIZE-1))
+#define PAGE_MASK		(~((1 << PAGE_SHIFT) - 1))
 
 #ifndef __ASSEMBLY__
 
diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h
index a3f3792..554f6d3 100644
--- a/arch/arm/include/asm/pgtable-3level.h
+++ b/arch/arm/include/asm/pgtable-3level.h
@@ -48,16 +48,16 @@
 #define PMD_SHIFT		21
 
 #define PMD_SIZE		(1UL << PMD_SHIFT)
-#define PMD_MASK		(~(PMD_SIZE-1))
+#define PMD_MASK		(~((1 << PMD_SHIFT) - 1))
 #define PGDIR_SIZE		(1UL << PGDIR_SHIFT)
-#define PGDIR_MASK		(~(PGDIR_SIZE-1))
+#define PGDIR_MASK		(~((1 << PGDIR_SHIFT) - 1))
 
 /*
  * section address mask and size definitions.
  */
 #define SECTION_SHIFT		21
 #define SECTION_SIZE		(1UL << SECTION_SHIFT)
-#define SECTION_MASK		(~(SECTION_SIZE-1))
+#define SECTION_MASK		(~((1 << SECTION_SHIFT) - 1))
 
 #define USER_PTRS_PER_PGD	(PAGE_OFFSET / PGDIR_SIZE)
 
-- 
1.7.9.5

[PATCH v4 02/13] ARM: LPAE: use phys_addr_t in alloc_init_pud()

[Cyril Chemparathy]

From: Vitaly Andrianov <vitalya@ti.com>

This patch fixes the alloc_init_pud() function to use phys_addr_t instead of
unsigned long when passing in the phys argument.

This is an extension to commit 97092e0c56830457af0639f6bd904537a150ea4a (ARM:
pgtable: use phys_addr_t for physical addresses), which applied similar changes
elsewhere in the ARM memory management code.

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
---
 arch/arm/mm/mmu.c |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 9f06102..ef43689 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -612,7 +612,8 @@ static void __init alloc_init_section(pud_t *pud, unsigned long addr,
 }
 
 static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
-	unsigned long end, unsigned long phys, const struct mem_type *type)
+				  unsigned long end, phys_addr_t phys,
+				  const struct mem_type *type)
 {
 	pud_t *pud = pud_offset(pgd, addr);
 	unsigned long next;
-- 
1.7.9.5

[PATCH v4 03/13] ARM: LPAE: use phys_addr_t in free_memmap()

[Cyril Chemparathy]

From: Vitaly Andrianov <vitalya@ti.com>

The free_memmap() was mistakenly using unsigned long type to represent
physical addresses.  This breaks on PAE systems where memory could be placed
above the 32-bit addressible limit.

This patch fixes this function to properly use phys_addr_t instead.

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
---
 arch/arm/mm/init.c |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index ad722f1..1c5151a 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -457,7 +457,7 @@ static inline void
 free_memmap(unsigned long start_pfn, unsigned long end_pfn)
 {
 	struct page *start_pg, *end_pg;
-	unsigned long pg, pgend;
+	phys_addr_t pg, pgend;
 
 	/*
 	 * Convert start_pfn/end_pfn to a struct page pointer.
@@ -469,8 +469,8 @@ free_memmap(unsigned long start_pfn, unsigned long end_pfn)
 	 * Convert to physical addresses, and
 	 * round start upwards and end downwards.
 	 */
-	pg = (unsigned long)PAGE_ALIGN(__pa(start_pg));
-	pgend = (unsigned long)__pa(end_pg) & PAGE_MASK;
+	pg = PAGE_ALIGN(__pa(start_pg));
+	pgend = __pa(end_pg) & PAGE_MASK;
 
 	/*
 	 * If there are free pages between these,
-- 
1.7.9.5

[PATCH v4 04/13] ARM: LPAE: use phys_addr_t for initrd location

[Cyril Chemparathy]

From: Vitaly Andrianov <vitalya@ti.com>

This patch fixes the initrd setup code to use phys_addr_t instead of assuming
32-bit addressing.  Without this we cannot boot on systems where initrd is
located above the 4G physical address limit.

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
---
 arch/arm/mm/init.c |   13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 1c5151a..87ee0ec 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -36,12 +36,13 @@
 
 #include "mm.h"
 
-static unsigned long phys_initrd_start __initdata = 0;
+static phys_addr_t phys_initrd_start __initdata = 0;
 static unsigned long phys_initrd_size __initdata = 0;
 
 static int __init early_initrd(char *p)
 {
-	unsigned long start, size;
+	phys_addr_t start;
+	unsigned long size;
 	char *endp;
 
 	start = memparse(p, &endp);
@@ -347,14 +348,14 @@ void __init arm_memblock_init(struct meminfo *mi, struct machine_desc *mdesc)
 #ifdef CONFIG_BLK_DEV_INITRD
 	if (phys_initrd_size &&
 	    !memblock_is_region_memory(phys_initrd_start, phys_initrd_size)) {
-		pr_err("INITRD: 0x%08lx+0x%08lx is not a memory region - disabling initrd\n",
-		       phys_initrd_start, phys_initrd_size);
+		pr_err("INITRD: 0x%08llx+0x%08lx is not a memory region - disabling initrd\n",
+		       (u64)phys_initrd_start, phys_initrd_size);
 		phys_initrd_start = phys_initrd_size = 0;
 	}
 	if (phys_initrd_size &&
 	    memblock_is_region_reserved(phys_initrd_start, phys_initrd_size)) {
-		pr_err("INITRD: 0x%08lx+0x%08lx overlaps in-use memory region - disabling initrd\n",
-		       phys_initrd_start, phys_initrd_size);
+		pr_err("INITRD: 0x%08llx+0x%08lx overlaps in-use memory region - disabling initrd\n",
+		       (u64)phys_initrd_start, phys_initrd_size);
 		phys_initrd_start = phys_initrd_size = 0;
 	}
 	if (phys_initrd_size) {
-- 
1.7.9.5

[PATCH v4 05/13] ARM: LPAE: use phys_addr_t in switch_mm()

[Cyril Chemparathy]

This patch modifies the switch_mm() processor functions to use phys_addr_t.
On LPAE systems, we now honor the upper 32-bits of the physical address that
is being passed in, and program these into TTBR as expected.

Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Reviewed-by: Nicolas Pitre <nico@linaro.org>
---
 arch/arm/include/asm/proc-fns.h |    4 ++--
 arch/arm/mm/proc-v7-3level.S    |   16 ++++++++++++----
 2 files changed, 14 insertions(+), 6 deletions(-)

diff --git a/arch/arm/include/asm/proc-fns.h b/arch/arm/include/asm/proc-fns.h
index f3628fb..75b5f14 100644
--- a/arch/arm/include/asm/proc-fns.h
+++ b/arch/arm/include/asm/proc-fns.h
@@ -60,7 +60,7 @@ extern struct processor {
 	/*
 	 * Set the page table
 	 */
-	void (*switch_mm)(unsigned long pgd_phys, struct mm_struct *mm);
+	void (*switch_mm)(phys_addr_t pgd_phys, struct mm_struct *mm);
 	/*
 	 * Set a possibly extended PTE.  Non-extended PTEs should
 	 * ignore 'ext'.
@@ -82,7 +82,7 @@ extern void cpu_proc_init(void);
 extern void cpu_proc_fin(void);
 extern int cpu_do_idle(void);
 extern void cpu_dcache_clean_area(void *, int);
-extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm);
+extern void cpu_do_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm);
 #ifdef CONFIG_ARM_LPAE
 extern void cpu_set_pte_ext(pte_t *ptep, pte_t pte);
 #else
diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
index 7b56386..e64be21 100644
--- a/arch/arm/mm/proc-v7-3level.S
+++ b/arch/arm/mm/proc-v7-3level.S
@@ -39,6 +39,14 @@
 #define TTB_FLAGS_SMP	(TTB_IRGN_WBWA|TTB_S|TTB_RGN_OC_WBWA)
 #define PMD_FLAGS_SMP	(PMD_SECT_WBWA|PMD_SECT_S)
 
+#ifndef __ARMEB__
+#  define rpgdl	r0
+#  define rpgdh	r1
+#else
+#  define rpgdl	r1
+#  define rpgdh	r0
+#endif
+
 /*
  * cpu_v7_switch_mm(pgd_phys, tsk)
  *
@@ -47,10 +55,10 @@
  */
 ENTRY(cpu_v7_switch_mm)
 #ifdef CONFIG_MMU
-	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
-	and	r3, r1, #0xff
-	mov	r3, r3, lsl #(48 - 32)		@ ASID
-	mcrr	p15, 0, r0, r3, c2		@ set TTB 0
+	ldr	r2, [r2, #MM_CONTEXT_ID]		@ get mm->context.id
+	and	r2, r2, #0xff				@ ASID
+	orr	rpgdh, rpgdh, r2, lsl #(48 - 32)	@ upper 32-bits of pgd
+	mcrr	p15, 0, rpgdl, rpgdh, c2		@ set TTB 0
 	isb
 #endif
 	mov	pc, lr
-- 
1.7.9.5

[PATCH v4 06/13] ARM: LPAE: use 64-bit accessors for TTBR registers

[Cyril Chemparathy]

This patch adds TTBR accessor macros, and modifies cpu_get_pgd() and
the LPAE version of cpu_set_reserved_ttbr0() to use these instead.

In the process, we also fix these functions to correctly handle cases
where the physical address lies beyond the 4G limit of 32-bit addressing.

Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
---
 arch/arm/include/asm/proc-fns.h |   22 +++++++++++++++++-----
 arch/arm/mm/context.c           |    9 ++-------
 2 files changed, 19 insertions(+), 12 deletions(-)

diff --git a/arch/arm/include/asm/proc-fns.h b/arch/arm/include/asm/proc-fns.h
index 75b5f14..1c3cf94 100644
--- a/arch/arm/include/asm/proc-fns.h
+++ b/arch/arm/include/asm/proc-fns.h
@@ -116,13 +116,25 @@ extern void cpu_resume(void);
 #define cpu_switch_mm(pgd,mm) cpu_do_switch_mm(virt_to_phys(pgd),mm)
 
 #ifdef CONFIG_ARM_LPAE
+
+#define cpu_get_ttbr(nr)					\
+	({							\
+		u64 ttbr;					\
+		__asm__("mrrc	p15, " #nr ", %Q0, %R0, c2"	\
+			: "=r" (ttbr));				\
+		ttbr;						\
+	})
+
+#define cpu_set_ttbr(nr, val)					\
+	do {							\
+		u64 ttbr = val;					\
+		__asm__("mcrr	p15, " #nr ", %Q0, %R0, c2"	\
+			: : "r" (ttbr));			\
+	} while (0)
+
 #define cpu_get_pgd()	\
 	({						\
-		unsigned long pg, pg2;			\
-		__asm__("mrrc	p15, 0, %0, %1, c2"	\
-			: "=r" (pg), "=r" (pg2)		\
-			:				\
-			: "cc");			\
+		u64 pg = cpu_get_ttbr(0);		\
 		pg &= ~(PTRS_PER_PGD*sizeof(pgd_t)-1);	\
 		(pgd_t *)phys_to_virt(pg);		\
 	})
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index bc4a5e9..7c17ff8 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -20,6 +20,7 @@
 #include <asm/smp_plat.h>
 #include <asm/thread_notify.h>
 #include <asm/tlbflush.h>
+#include <asm/proc-fns.h>
 
 /*
  * On ARMv6, we have the following structure in the Context ID:
@@ -52,17 +53,11 @@ static cpumask_t tlb_flush_pending;
 #ifdef CONFIG_ARM_LPAE
 static void cpu_set_reserved_ttbr0(void)
 {
-	unsigned long ttbl = __pa(swapper_pg_dir);
-	unsigned long ttbh = 0;
-
 	/*
 	 * Set TTBR0 to swapper_pg_dir which contains only global entries. The
 	 * ASID is set to 0.
 	 */
-	asm volatile(
-	"	mcrr	p15, 0, %0, %1, c2		@ set TTBR0\n"
-	:
-	: "r" (ttbl), "r" (ttbh));
+	cpu_set_ttbr(0, __pa(swapper_pg_dir));
 	isb();
 }
 #else
-- 
1.7.9.5

[PATCH v4 07/13] ARM: LPAE: define ARCH_LOW_ADDRESS_LIMIT for bootmem

[Cyril Chemparathy]

This patch adds an architecture defined override for ARCH_LOW_ADDRESS_LIMIT.
On PAE systems, the absence of this override causes bootmem to incorrectly
limit itself to 32-bit addressable physical memory.

Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
---
 arch/arm/include/asm/memory.h |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 73cf03a..8825abb 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -275,6 +275,8 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
 #define virt_to_page(kaddr)	pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
 #define virt_addr_valid(kaddr)	((unsigned long)(kaddr) >= PAGE_OFFSET && (unsigned long)(kaddr) < (unsigned long)high_memory)
 
+#define ARCH_LOW_ADDRESS_LIMIT		PHYS_MASK
+
 #endif
 
 #include <asm-generic/memory_model.h>
-- 
1.7.9.5

[PATCH v4 08/13] ARM: LPAE: factor out T1SZ and TTBR1 computations

[Cyril Chemparathy]

This patch moves the TTBR1 offset calculation and the T1SZ calculation out
of the TTB setup assembly code.  This should not affect functionality in
any way, but improves code readability as well as readability of subsequent
patches in this series.

Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
---
 arch/arm/include/asm/pgtable-3level-hwdef.h |   20 ++++++++++++++++++
 arch/arm/mm/proc-v7-3level.S                |   29 ++++++++-------------------
 2 files changed, 28 insertions(+), 21 deletions(-)

diff --git a/arch/arm/include/asm/pgtable-3level-hwdef.h b/arch/arm/include/asm/pgtable-3level-hwdef.h
index d795282..e9d70a3 100644
--- a/arch/arm/include/asm/pgtable-3level-hwdef.h
+++ b/arch/arm/include/asm/pgtable-3level-hwdef.h
@@ -74,4 +74,24 @@
 #define PHYS_MASK_SHIFT		(40)
 #define PHYS_MASK		((1ULL << PHYS_MASK_SHIFT) - 1)
 
+/*
+ * TTBR0/TTBR1 split (PAGE_OFFSET):
+ *   0x40000000: T0SZ = 2, T1SZ = 0 (not used)
+ *   0x80000000: T0SZ = 0, T1SZ = 1
+ *   0xc0000000: T0SZ = 0, T1SZ = 2
+ *
+ * Only use this feature if PHYS_OFFSET <= PAGE_OFFSET, otherwise
+ * booting secondary CPUs would end up using TTBR1 for the identity
+ * mapping set up in TTBR0.
+ */
+#if defined CONFIG_VMSPLIT_2G
+#define TTBR1_OFFSET	16			/* skip two L1 entries */
+#elif defined CONFIG_VMSPLIT_3G
+#define TTBR1_OFFSET	(4096 * (1 + 3))	/* only L2, skip pgd + 3*pmd */
+#else
+#define TTBR1_OFFSET	0
+#endif
+
+#define TTBR1_SIZE	(((PAGE_OFFSET >> 30) - 1) << 16)
+
 #endif
diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
index e64be21..e6576f5 100644
--- a/arch/arm/mm/proc-v7-3level.S
+++ b/arch/arm/mm/proc-v7-3level.S
@@ -113,7 +113,7 @@ ENDPROC(cpu_v7_set_pte_ext)
 	 */
 	.macro	v7_ttb_setup, zero, ttbr0, ttbr1, tmp
 	ldr	\tmp, =swapper_pg_dir		@ swapper_pg_dir virtual address
-	cmp	\ttbr1, \tmp			@ PHYS_OFFSET > PAGE_OFFSET? (branch below)
+	cmp	\ttbr1, \tmp			@ PHYS_OFFSET > PAGE_OFFSET?
 	mrc	p15, 0, \tmp, c2, c0, 2		@ TTB control register
 	orr	\tmp, \tmp, #TTB_EAE
 	ALT_SMP(orr	\tmp, \tmp, #TTB_FLAGS_SMP)
@@ -121,27 +121,14 @@ ENDPROC(cpu_v7_set_pte_ext)
 	ALT_SMP(orr	\tmp, \tmp, #TTB_FLAGS_SMP << 16)
 	ALT_UP(orr	\tmp, \tmp, #TTB_FLAGS_UP << 16)
 	/*
-	 * TTBR0/TTBR1 split (PAGE_OFFSET):
-	 *   0x40000000: T0SZ = 2, T1SZ = 0 (not used)
-	 *   0x80000000: T0SZ = 0, T1SZ = 1
-	 *   0xc0000000: T0SZ = 0, T1SZ = 2
-	 *
-	 * Only use this feature if PHYS_OFFSET <= PAGE_OFFSET, otherwise
-	 * booting secondary CPUs would end up using TTBR1 for the identity
-	 * mapping set up in TTBR0.
+	 * Only use split TTBRs if PHYS_OFFSET <= PAGE_OFFSET (cmp above),
+	 * otherwise booting secondary CPUs would end up using TTBR1 for the
+	 * identity mapping set up in TTBR0.
 	 */
-	bhi	9001f				@ PHYS_OFFSET > PAGE_OFFSET?
-	orr	\tmp, \tmp, #(((PAGE_OFFSET >> 30) - 1) << 16) @ TTBCR.T1SZ
-#if defined CONFIG_VMSPLIT_2G
-	/* PAGE_OFFSET == 0x80000000, T1SZ == 1 */
-	add	\ttbr1, \ttbr1, #1 << 4		@ skip two L1 entries
-#elif defined CONFIG_VMSPLIT_3G
-	/* PAGE_OFFSET == 0xc0000000, T1SZ == 2 */
-	add	\ttbr1, \ttbr1, #4096 * (1 + 3)	@ only L2 used, skip pgd+3*pmd
-#endif
-	/* CONFIG_VMSPLIT_1G does not need TTBR1 adjustment */
-9001:	mcr	p15, 0, \tmp, c2, c0, 2		@ TTB control register
-	mcrr	p15, 1, \ttbr1, \zero, c2	@ load TTBR1
+	orrls	\tmp, \tmp, #TTBR1_SIZE				@ TTBCR.T1SZ
+	mcr	p15, 0, \tmp, c2, c0, 2				@ TTBCR
+	addls	\ttbr1, \ttbr1, #TTBR1_OFFSET
+	mcrr	p15, 1, \ttbr1, \zero, c2			@ load TTBR1
 	.endm
 
 	__CPUINIT
-- 
1.7.9.5

[PATCH v4 09/13] ARM: LPAE: accomodate >32-bit addresses for page table base

[Cyril Chemparathy]

This patch redefines the early boot time use of the R4 register to steal a few
low order bits (ARCH_PGD_SHIFT bits) on LPAE systems.  This allows for up to
38-bit physical addresses.

Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
---
 arch/arm/include/asm/memory.h |   16 ++++++++++++++++
 arch/arm/kernel/head.S        |   10 ++++------
 arch/arm/kernel/smp.c         |   11 +++++++++--
 arch/arm/mm/proc-v7-3level.S  |    8 ++++++++
 4 files changed, 37 insertions(+), 8 deletions(-)

diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 8825abb..f3a7f76 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -18,6 +18,8 @@
 #include <linux/types.h>
 #include <linux/sizes.h>
 
+#include <asm/cache.h>
+
 #ifdef CONFIG_NEED_MACH_MEMORY_H
 #include <mach/memory.h>
 #endif
@@ -141,6 +143,20 @@
 #define page_to_phys(page)	(__pfn_to_phys(page_to_pfn(page)))
 #define phys_to_page(phys)	(pfn_to_page(__phys_to_pfn(phys)))
 
+/*
+ * Minimum guaranted alignment in pgd_alloc().  The page table pointers passed
+ * around in head.S and proc-*.S are shifted by this amount, in order to
+ * leave spare high bits for systems with physical address extension.  This
+ * does not fully accomodate the 40-bit addressing capability of ARM LPAE, but
+ * gives us about 38-bits or so.
+ */
+#ifdef CONFIG_ARM_LPAE
+#define ARCH_PGD_SHIFT		L1_CACHE_SHIFT
+#else
+#define ARCH_PGD_SHIFT		0
+#endif
+#define ARCH_PGD_MASK		((1 << ARCH_PGD_SHIFT) - 1)
+
 #ifndef __ASSEMBLY__
 
 /*
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 4eee351..916af3e 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -156,7 +156,7 @@ ENDPROC(stext)
  *
  * Returns:
  *  r0, r3, r5-r7 corrupted
- *  r4 = physical page table address
+ *  r4 = page table (see ARCH_PGD_SHIFT in asm/memory.h)
  */
 __create_page_tables:
 	pgtbl	r4, r8				@ page table address
@@ -310,6 +310,7 @@ __create_page_tables:
 #endif
 #ifdef CONFIG_ARM_LPAE
 	sub	r4, r4, #0x1000		@ point to the PGD table
+	mov	r4, r4, lsr #ARCH_PGD_SHIFT
 #endif
 	mov	pc, lr
 ENDPROC(__create_page_tables)
@@ -387,7 +388,7 @@ __secondary_data:
  *  r0  = cp#15 control register
  *  r1  = machine ID
  *  r2  = atags or dtb pointer
- *  r4  = page table pointer
+ *  r4  = page table (see ARCH_PGD_SHIFT in asm/memory.h)
  *  r9  = processor ID
  *  r13 = *virtual* address to jump to upon completion
  */
@@ -406,10 +407,7 @@ __enable_mmu:
 #ifdef CONFIG_CPU_ICACHE_DISABLE
 	bic	r0, r0, #CR_I
 #endif
-#ifdef CONFIG_ARM_LPAE
-	mov	r5, #0
-	mcrr	p15, 0, r4, r5, c2		@ load TTBR0
-#else
+#ifndef CONFIG_ARM_LPAE
 	mov	r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
 		      domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
 		      domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 84f4cbf..042e12d 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -78,6 +78,13 @@ void __init smp_set_ops(struct smp_operations *ops)
 		smp_ops = *ops;
 };
 
+static unsigned long get_arch_pgd(pgd_t *pgd)
+{
+	phys_addr_t pgdir = virt_to_phys(pgd);
+	BUG_ON(pgdir & ARCH_PGD_MASK);
+	return pgdir >> ARCH_PGD_SHIFT;
+}
+
 int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
 {
 	int ret;
@@ -87,8 +94,8 @@ int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
 	 * its stack and the page tables.
 	 */
 	secondary_data.stack = task_stack_page(idle) + THREAD_START_SP;
-	secondary_data.pgdir = virt_to_phys(idmap_pgd);
-	secondary_data.swapper_pg_dir = virt_to_phys(swapper_pg_dir);
+	secondary_data.pgdir = get_arch_pgd(idmap_pgd);
+	secondary_data.swapper_pg_dir = get_arch_pgd(swapper_pg_dir);
 	__cpuc_flush_dcache_area(&secondary_data, sizeof(secondary_data));
 	outer_clean_range(__pa(&secondary_data), __pa(&secondary_data + 1));
 
diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
index e6576f5..c02c1cc 100644
--- a/arch/arm/mm/proc-v7-3level.S
+++ b/arch/arm/mm/proc-v7-3level.S
@@ -113,6 +113,7 @@ ENDPROC(cpu_v7_set_pte_ext)
 	 */
 	.macro	v7_ttb_setup, zero, ttbr0, ttbr1, tmp
 	ldr	\tmp, =swapper_pg_dir		@ swapper_pg_dir virtual address
+	mov	\tmp, \tmp, lsr #ARCH_PGD_SHIFT
 	cmp	\ttbr1, \tmp			@ PHYS_OFFSET > PAGE_OFFSET?
 	mrc	p15, 0, \tmp, c2, c0, 2		@ TTB control register
 	orr	\tmp, \tmp, #TTB_EAE
@@ -127,8 +128,15 @@ ENDPROC(cpu_v7_set_pte_ext)
 	 */
 	orrls	\tmp, \tmp, #TTBR1_SIZE				@ TTBCR.T1SZ
 	mcr	p15, 0, \tmp, c2, c0, 2				@ TTBCR
+	mov	\tmp, \ttbr1, lsr #(32 - ARCH_PGD_SHIFT)	@ upper bits
+	mov	\ttbr1, \ttbr1, lsl #ARCH_PGD_SHIFT		@ lower bits
 	addls	\ttbr1, \ttbr1, #TTBR1_OFFSET
 	mcrr	p15, 1, \ttbr1, \zero, c2			@ load TTBR1
+	mov	\tmp, \ttbr0, lsr #(32 - ARCH_PGD_SHIFT)	@ upper bits
+	mov	\ttbr0, \ttbr0, lsl #ARCH_PGD_SHIFT		@ lower bits
+	mcrr	p15, 0, \ttbr0, \zero, c2			@ load TTBR0
+	mcrr	p15, 1, \ttbr1, \zero, c2			@ load TTBR1
+	mcrr	p15, 0, \ttbr0, \zero, c2			@ load TTBR0
 	.endm
 
 	__CPUINIT
-- 
1.7.9.5

[PATCH v4 10/13] ARM: mm: use physical addresses in highmem sanity checks

[Cyril Chemparathy]

This patch modifies the highmem sanity checking code to use physical addresses
instead.  This change eliminates the wrap-around problems associated with the
original virtual address based checks, and this simplifies the code a bit.

The one constraint imposed here is that low physical memory must be mapped in
a monotonically increasing fashion if there are multiple banks of memory,
i.e., x < y must => pa(x) < pa(y).

Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
---
 arch/arm/mm/mmu.c |   22 ++++++++++------------
 1 file changed, 10 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index ef43689..e8875cb 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -929,6 +929,7 @@ phys_addr_t arm_lowmem_limit __initdata = 0;
 void __init sanity_check_meminfo(void)
 {
 	int i, j, highmem = 0;
+	phys_addr_t vmalloc_limit = __pa(vmalloc_min - 1) + 1;
 
 	for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
 		struct membank *bank = &meminfo.bank[j];
@@ -938,8 +939,7 @@ void __init sanity_check_meminfo(void)
 			highmem = 1;
 
 #ifdef CONFIG_HIGHMEM
-		if (__va(bank->start) >= vmalloc_min ||
-		    __va(bank->start) < (void *)PAGE_OFFSET)
+		if (bank->start >= vmalloc_limit)
 			highmem = 1;
 
 		bank->highmem = highmem;
@@ -948,8 +948,8 @@ void __init sanity_check_meminfo(void)
 		 * Split those memory banks which are partially overlapping
 		 * the vmalloc area greatly simplifying things later.
 		 */
-		if (!highmem && __va(bank->start) < vmalloc_min &&
-		    bank->size > vmalloc_min - __va(bank->start)) {
+		if (!highmem && bank->start < vmalloc_limit &&
+		    bank->size > vmalloc_limit - bank->start) {
 			if (meminfo.nr_banks >= NR_BANKS) {
 				printk(KERN_CRIT "NR_BANKS too low, "
 						 "ignoring high memory\n");
@@ -958,12 +958,12 @@ void __init sanity_check_meminfo(void)
 					(meminfo.nr_banks - i) * sizeof(*bank));
 				meminfo.nr_banks++;
 				i++;
-				bank[1].size -= vmalloc_min - __va(bank->start);
-				bank[1].start = __pa(vmalloc_min - 1) + 1;
+				bank[1].size -= vmalloc_limit - bank->start;
+				bank[1].start = vmalloc_limit;
 				bank[1].highmem = highmem = 1;
 				j++;
 			}
-			bank->size = vmalloc_min - __va(bank->start);
+			bank->size = vmalloc_limit - bank->start;
 		}
 #else
 		bank->highmem = highmem;
@@ -983,8 +983,7 @@ void __init sanity_check_meminfo(void)
 		 * Check whether this memory bank would entirely overlap
 		 * the vmalloc area.
 		 */
-		if (__va(bank->start) >= vmalloc_min ||
-		    __va(bank->start) < (void *)PAGE_OFFSET) {
+		if (bank->start >= vmalloc_limit) {
 			printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
 			       "(vmalloc region overlap).\n",
 			       (unsigned long long)bank->start,
@@ -996,9 +995,8 @@ void __init sanity_check_meminfo(void)
 		 * Check whether this memory bank would partially overlap
 		 * the vmalloc area.
 		 */
-		if (__va(bank->start + bank->size - 1) >= vmalloc_min ||
-		    __va(bank->start + bank->size - 1) <= __va(bank->start)) {
-			unsigned long newsize = vmalloc_min - __va(bank->start);
+		if (bank->start + bank->size > vmalloc_limit)
+			unsigned long newsize = vmalloc_limit - bank->start;
 			printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
 			       "to -%.8llx (vmalloc region overlap).\n",
 			       (unsigned long long)bank->start,
-- 
1.7.9.5

[PATCH v4 11/13] ARM: mm: cleanup checks for membank overlap with vmalloc area

[Cyril Chemparathy]

On Keystone platforms, physical memory is entirely outside the 32-bit
addressible range.  Therefore, the (bank->start > ULONG_MAX) check below marks
the entire system memory as highmem, and this causes unpleasentness all over.

This patch eliminates the extra bank start check (against ULONG_MAX) by
checking bank->start against the physical address corresponding to vmalloc_min
instead.

In the process, this patch also cleans up parts of the highmem sanity check
code by removing what has now become a redundant check for banks that entirely
overlap with the vmalloc range.

Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
---
 arch/arm/mm/mmu.c |   19 +------------------
 1 file changed, 1 insertion(+), 18 deletions(-)

diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index e8875cb..85ed732 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -935,15 +935,12 @@ void __init sanity_check_meminfo(void)
 		struct membank *bank = &meminfo.bank[j];
 		*bank = meminfo.bank[i];
 
-		if (bank->start > ULONG_MAX)
-			highmem = 1;
-
-#ifdef CONFIG_HIGHMEM
 		if (bank->start >= vmalloc_limit)
 			highmem = 1;
 
 		bank->highmem = highmem;
 
+#ifdef CONFIG_HIGHMEM
 		/*
 		 * Split those memory banks which are partially overlapping
 		 * the vmalloc area greatly simplifying things later.
@@ -966,8 +963,6 @@ void __init sanity_check_meminfo(void)
 			bank->size = vmalloc_limit - bank->start;
 		}
 #else
-		bank->highmem = highmem;
-
 		/*
 		 * Highmem banks not allowed with !CONFIG_HIGHMEM.
 		 */
@@ -980,18 +975,6 @@ void __init sanity_check_meminfo(void)
 		}
 
 		/*
-		 * Check whether this memory bank would entirely overlap
-		 * the vmalloc area.
-		 */
-		if (bank->start >= vmalloc_limit) {
-			printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
-			       "(vmalloc region overlap).\n",
-			       (unsigned long long)bank->start,
-			       (unsigned long long)bank->start + bank->size - 1);
-			continue;
-		}
-
-		/*
 		 * Check whether this memory bank would partially overlap
 		 * the vmalloc area.
 		 */
-- 
1.7.9.5

[PATCH v4 12/13] ARM: mm: clean up membank size limit checks

[Cyril Chemparathy]

This patch cleans up the highmem sanity check code by simplifying the range
checks with a pre-calculated size_limit.  This patch should otherwise have no
functional impact on behavior.

This patch also removes a redundant (bank->start < vmalloc_limit) check, since
this is already covered by the !highmem condition.

Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
---
 arch/arm/mm/mmu.c |   19 +++++++++++--------
 1 file changed, 11 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 85ed732..2a02ff0 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -933,10 +933,15 @@ void __init sanity_check_meminfo(void)
 
 	for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
 		struct membank *bank = &meminfo.bank[j];
+		phys_addr_t size_limit;
+
 		*bank = meminfo.bank[i];
+		size_limit = bank->size;
 
 		if (bank->start >= vmalloc_limit)
 			highmem = 1;
+		else
+			size_limit = vmalloc_limit - bank->start;
 
 		bank->highmem = highmem;
 
@@ -945,8 +950,7 @@ void __init sanity_check_meminfo(void)
 		 * Split those memory banks which are partially overlapping
 		 * the vmalloc area greatly simplifying things later.
 		 */
-		if (!highmem && bank->start < vmalloc_limit &&
-		    bank->size > vmalloc_limit - bank->start) {
+		if (!highmem && bank->size > size_limit) {
 			if (meminfo.nr_banks >= NR_BANKS) {
 				printk(KERN_CRIT "NR_BANKS too low, "
 						 "ignoring high memory\n");
@@ -955,12 +959,12 @@ void __init sanity_check_meminfo(void)
 					(meminfo.nr_banks - i) * sizeof(*bank));
 				meminfo.nr_banks++;
 				i++;
-				bank[1].size -= vmalloc_limit - bank->start;
+				bank[1].size -= size_limit;
 				bank[1].start = vmalloc_limit;
 				bank[1].highmem = highmem = 1;
 				j++;
 			}
-			bank->size = vmalloc_limit - bank->start;
+			bank->size = size_limit;
 		}
 #else
 		/*
@@ -978,14 +982,13 @@ void __init sanity_check_meminfo(void)
 		 * Check whether this memory bank would partially overlap
 		 * the vmalloc area.
 		 */
-		if (bank->start + bank->size > vmalloc_limit)
-			unsigned long newsize = vmalloc_limit - bank->start;
+		if (bank->size > size_limit) {
 			printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
 			       "to -%.8llx (vmalloc region overlap).\n",
 			       (unsigned long long)bank->start,
 			       (unsigned long long)bank->start + bank->size - 1,
-			       (unsigned long long)bank->start + newsize - 1);
-			bank->size = newsize;
+			       (unsigned long long)bank->start + size_limit - 1);
+			bank->size = size_limit;
 		}
 #endif
 		if (!bank->highmem && bank->start + bank->size > arm_lowmem_limit)
-- 
1.7.9.5

[PATCH v4 13/13] ARM: fix type of PHYS_PFN_OFFSET to unsigned long

[Cyril Chemparathy]

On LPAE machines, PHYS_OFFSET evaluates to a phys_addr_t and this type is
inherited by the PHYS_PFN_OFFSET definition as well.  Consequently, the kernel
build emits warnings of the form:

init/main.c: In function 'start_kernel':
init/main.c:588:7: warning: format '%lx' expects argument of type 'long unsigned int', but argument 2 has type 'phys_addr_t' [-Wformat]

This patch fixes this warning by pinning down the PFN type to unsigned long.

Signed-off-by: Cyril Chemparathy <cyril@ti.com>
---
 arch/arm/include/asm/memory.h |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index f3a7f76..32e9e5a 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -223,7 +223,7 @@ static inline unsigned long __phys_to_virt(unsigned long x)
  * direct-mapped view.  We assume this is the first page
  * of RAM in the mem_map as well.
  */
-#define PHYS_PFN_OFFSET	(PHYS_OFFSET >> PAGE_SHIFT)
+#define PHYS_PFN_OFFSET	((unsigned long)(PHYS_OFFSET >> PAGE_SHIFT))
 
 /*
  * These are *only* valid on the kernel direct mapped RAM memory.
-- 
1.7.9.5

Re: [PATCH v4 02/13] ARM: LPAE: use phys_addr_t in alloc_init_pud()

[Hui Wang]

Cyril Chemparathy wrote:
> From: Vitaly Andrianov <vitalya@ti.com>
>
> This patch fixes the alloc_init_pud() function to use phys_addr_t instead of
> unsigned long when passing in the phys argument.
>
> This is an extension to commit 97092e0c56830457af0639f6bd904537a150ea4a (ARM:
> pgtable: use phys_addr_t for physical addresses), which applied similar changes
> elsewhere in the ARM memory management code.
>
> Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
> Signed-off-by: Cyril Chemparathy <cyril@ti.com>
> Acked-by: Nicolas Pitre <nico@linaro.org>
> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
> ---
>  arch/arm/mm/mmu.c |    3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
> index 9f06102..ef43689 100644
> --- a/arch/arm/mm/mmu.c
> +++ b/arch/arm/mm/mmu.c
> @@ -612,7 +612,8 @@ static void __init alloc_init_section(pud_t *pud, unsigned long addr,
>  }
>  
>  static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
> -	unsigned long end, unsigned long phys, const struct mem_type *type)
> +				  unsigned long end, phys_addr_t phys,
> +				  const struct mem_type *type)
>   
The change is correct but seems useless so far. This function only be 
called from map_lowmem and devicemaps_init, from i know neither lowmem 
nor device io registers of existing platforms exceed 32bit address.

regards,
Hui.
>  {
>  	pud_t *pud = pud_offset(pgd, addr);
>  	unsigned long next;
>   

Re: [PATCH v4 02/13] ARM: LPAE: use phys_addr_t in alloc_init_pud()

[Nicolas Pitre]

On Fri, 1 Feb 2013, Hui Wang wrote:

> Cyril Chemparathy wrote:
> > From: Vitaly Andrianov <vitalya@ti.com>
> > 
> > This patch fixes the alloc_init_pud() function to use phys_addr_t instead of
> > unsigned long when passing in the phys argument.
> > 
> > This is an extension to commit 97092e0c56830457af0639f6bd904537a150ea4a
> > (ARM:
> > pgtable: use phys_addr_t for physical addresses), which applied similar
> > changes
> > elsewhere in the ARM memory management code.
> > 
> > Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
> > Signed-off-by: Cyril Chemparathy <cyril@ti.com>
> > Acked-by: Nicolas Pitre <nico@linaro.org>
> > Acked-by: Catalin Marinas <catalin.marinas@arm.com>
> > ---
> >  arch/arm/mm/mmu.c |    3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> > 
> > diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
> > index 9f06102..ef43689 100644
> > --- a/arch/arm/mm/mmu.c
> > +++ b/arch/arm/mm/mmu.c
> > @@ -612,7 +612,8 @@ static void __init alloc_init_section(pud_t *pud,
> > unsigned long addr,
> >  }
> >   static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
> > -	unsigned long end, unsigned long phys, const struct mem_type *type)
> > +				  unsigned long end, phys_addr_t phys,
> > +				  const struct mem_type *type)
> >   
> The change is correct but seems useless so far. This function only be called
> from map_lowmem and devicemaps_init, from i know neither lowmem nor device io
> registers of existing platforms exceed 32bit address.

It is not because you are not aware of any existing platforms with RAM 
or device IO above the 4GB mark that they don't exist.

For example, some LPAE systems have all their RAM located above the 4G 
physical address mark. A simple (potentially non DMA capable) alias 
exists in the low 32-bit address space to allow the system to boot and 
switch to the real physical RAM addresses once the MMU is turned on.  
Some of that RAM is still qualified as "low mem" i.e. the portion of RAM 
that the kernel keeps permanently mapped in the 32-bit virtual space 
even if all of it is above the 4G mark in physical space.


Nicolas

Re: [PATCH v4 07/13] ARM: LPAE: define ARCH_LOW_ADDRESS_LIMIT for bootmem

[Nicolas Pitre]

On Thu, 31 Jan 2013, Cyril Chemparathy wrote:

> This patch adds an architecture defined override for ARCH_LOW_ADDRESS_LIMIT.
> On PAE systems, the absence of this override causes bootmem to incorrectly
> limit itself to 32-bit addressable physical memory.
> 
> Signed-off-by: Cyril Chemparathy <cyril@ti.com>
> Signed-off-by: Vitaly Andrianov <vitalya@ti.com>

Acked-by: Nicolas Pitre <nico@linaro.org>


> ---
>  arch/arm/include/asm/memory.h |    2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
> index 73cf03a..8825abb 100644
> --- a/arch/arm/include/asm/memory.h
> +++ b/arch/arm/include/asm/memory.h
> @@ -275,6 +275,8 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
>  #define virt_to_page(kaddr)	pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
>  #define virt_addr_valid(kaddr)	((unsigned long)(kaddr) >= PAGE_OFFSET && (unsigned long)(kaddr) < (unsigned long)high_memory)
>  
> +#define ARCH_LOW_ADDRESS_LIMIT		PHYS_MASK
> +
>  #endif
>  
>  #include <asm-generic/memory_model.h>
> -- 
> 1.7.9.5
> 

Re: [PATCH v4 09/13] ARM: LPAE: accomodate >32-bit addresses for page table base

[Nicolas Pitre]

On Thu, 31 Jan 2013, Cyril Chemparathy wrote:

> This patch redefines the early boot time use of the R4 register to steal a few
> low order bits (ARCH_PGD_SHIFT bits) on LPAE systems.  This allows for up to
> 38-bit physical addresses.
> 
> Signed-off-by: Cyril Chemparathy <cyril@ti.com>
> Signed-off-by: Vitaly Andrianov <vitalya@ti.com>

Acked-by: Nicolas Pitre <nico@linaro.org>

> ---
>  arch/arm/include/asm/memory.h |   16 ++++++++++++++++
>  arch/arm/kernel/head.S        |   10 ++++------
>  arch/arm/kernel/smp.c         |   11 +++++++++--
>  arch/arm/mm/proc-v7-3level.S  |    8 ++++++++
>  4 files changed, 37 insertions(+), 8 deletions(-)
> 
> diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
> index 8825abb..f3a7f76 100644
> --- a/arch/arm/include/asm/memory.h
> +++ b/arch/arm/include/asm/memory.h
> @@ -18,6 +18,8 @@
>  #include <linux/types.h>
>  #include <linux/sizes.h>
>  
> +#include <asm/cache.h>
> +
>  #ifdef CONFIG_NEED_MACH_MEMORY_H
>  #include <mach/memory.h>
>  #endif
> @@ -141,6 +143,20 @@
>  #define page_to_phys(page)	(__pfn_to_phys(page_to_pfn(page)))
>  #define phys_to_page(phys)	(pfn_to_page(__phys_to_pfn(phys)))
>  
> +/*
> + * Minimum guaranted alignment in pgd_alloc().  The page table pointers passed
> + * around in head.S and proc-*.S are shifted by this amount, in order to
> + * leave spare high bits for systems with physical address extension.  This
> + * does not fully accomodate the 40-bit addressing capability of ARM LPAE, but
> + * gives us about 38-bits or so.
> + */
> +#ifdef CONFIG_ARM_LPAE
> +#define ARCH_PGD_SHIFT		L1_CACHE_SHIFT
> +#else
> +#define ARCH_PGD_SHIFT		0
> +#endif
> +#define ARCH_PGD_MASK		((1 << ARCH_PGD_SHIFT) - 1)
> +
>  #ifndef __ASSEMBLY__
>  
>  /*
> diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
> index 4eee351..916af3e 100644
> --- a/arch/arm/kernel/head.S
> +++ b/arch/arm/kernel/head.S
> @@ -156,7 +156,7 @@ ENDPROC(stext)
>   *
>   * Returns:
>   *  r0, r3, r5-r7 corrupted
> - *  r4 = physical page table address
> + *  r4 = page table (see ARCH_PGD_SHIFT in asm/memory.h)
>   */
>  __create_page_tables:
>  	pgtbl	r4, r8				@ page table address
> @@ -310,6 +310,7 @@ __create_page_tables:
>  #endif
>  #ifdef CONFIG_ARM_LPAE
>  	sub	r4, r4, #0x1000		@ point to the PGD table
> +	mov	r4, r4, lsr #ARCH_PGD_SHIFT
>  #endif
>  	mov	pc, lr
>  ENDPROC(__create_page_tables)
> @@ -387,7 +388,7 @@ __secondary_data:
>   *  r0  = cp#15 control register
>   *  r1  = machine ID
>   *  r2  = atags or dtb pointer
> - *  r4  = page table pointer
> + *  r4  = page table (see ARCH_PGD_SHIFT in asm/memory.h)
>   *  r9  = processor ID
>   *  r13 = *virtual* address to jump to upon completion
>   */
> @@ -406,10 +407,7 @@ __enable_mmu:
>  #ifdef CONFIG_CPU_ICACHE_DISABLE
>  	bic	r0, r0, #CR_I
>  #endif
> -#ifdef CONFIG_ARM_LPAE
> -	mov	r5, #0
> -	mcrr	p15, 0, r4, r5, c2		@ load TTBR0
> -#else
> +#ifndef CONFIG_ARM_LPAE
>  	mov	r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
>  		      domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
>  		      domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
> diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
> index 84f4cbf..042e12d 100644
> --- a/arch/arm/kernel/smp.c
> +++ b/arch/arm/kernel/smp.c
> @@ -78,6 +78,13 @@ void __init smp_set_ops(struct smp_operations *ops)
>  		smp_ops = *ops;
>  };
>  
> +static unsigned long get_arch_pgd(pgd_t *pgd)
> +{
> +	phys_addr_t pgdir = virt_to_phys(pgd);
> +	BUG_ON(pgdir & ARCH_PGD_MASK);
> +	return pgdir >> ARCH_PGD_SHIFT;
> +}
> +
>  int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
>  {
>  	int ret;
> @@ -87,8 +94,8 @@ int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
>  	 * its stack and the page tables.
>  	 */
>  	secondary_data.stack = task_stack_page(idle) + THREAD_START_SP;
> -	secondary_data.pgdir = virt_to_phys(idmap_pgd);
> -	secondary_data.swapper_pg_dir = virt_to_phys(swapper_pg_dir);
> +	secondary_data.pgdir = get_arch_pgd(idmap_pgd);
> +	secondary_data.swapper_pg_dir = get_arch_pgd(swapper_pg_dir);
>  	__cpuc_flush_dcache_area(&secondary_data, sizeof(secondary_data));
>  	outer_clean_range(__pa(&secondary_data), __pa(&secondary_data + 1));
>  
> diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
> index e6576f5..c02c1cc 100644
> --- a/arch/arm/mm/proc-v7-3level.S
> +++ b/arch/arm/mm/proc-v7-3level.S
> @@ -113,6 +113,7 @@ ENDPROC(cpu_v7_set_pte_ext)
>  	 */
>  	.macro	v7_ttb_setup, zero, ttbr0, ttbr1, tmp
>  	ldr	\tmp, =swapper_pg_dir		@ swapper_pg_dir virtual address
> +	mov	\tmp, \tmp, lsr #ARCH_PGD_SHIFT
>  	cmp	\ttbr1, \tmp			@ PHYS_OFFSET > PAGE_OFFSET?
>  	mrc	p15, 0, \tmp, c2, c0, 2		@ TTB control register
>  	orr	\tmp, \tmp, #TTB_EAE
> @@ -127,8 +128,15 @@ ENDPROC(cpu_v7_set_pte_ext)
>  	 */
>  	orrls	\tmp, \tmp, #TTBR1_SIZE				@ TTBCR.T1SZ
>  	mcr	p15, 0, \tmp, c2, c0, 2				@ TTBCR
> +	mov	\tmp, \ttbr1, lsr #(32 - ARCH_PGD_SHIFT)	@ upper bits
> +	mov	\ttbr1, \ttbr1, lsl #ARCH_PGD_SHIFT		@ lower bits
>  	addls	\ttbr1, \ttbr1, #TTBR1_OFFSET
>  	mcrr	p15, 1, \ttbr1, \zero, c2			@ load TTBR1
> +	mov	\tmp, \ttbr0, lsr #(32 - ARCH_PGD_SHIFT)	@ upper bits
> +	mov	\ttbr0, \ttbr0, lsl #ARCH_PGD_SHIFT		@ lower bits
> +	mcrr	p15, 0, \ttbr0, \zero, c2			@ load TTBR0
> +	mcrr	p15, 1, \ttbr1, \zero, c2			@ load TTBR1
> +	mcrr	p15, 0, \ttbr0, \zero, c2			@ load TTBR0
>  	.endm
>  
>  	__CPUINIT
> -- 
> 1.7.9.5
> 

Re: [PATCH v4 13/13] ARM: fix type of PHYS_PFN_OFFSET to unsigned long

[Nicolas Pitre]

On Thu, 31 Jan 2013, Cyril Chemparathy wrote:

> On LPAE machines, PHYS_OFFSET evaluates to a phys_addr_t and this type is
> inherited by the PHYS_PFN_OFFSET definition as well.  Consequently, the kernel
> build emits warnings of the form:
> 
> init/main.c: In function 'start_kernel':
> init/main.c:588:7: warning: format '%lx' expects argument of type 'long unsigned int', but argument 2 has type 'phys_addr_t' [-Wformat]
> 
> This patch fixes this warning by pinning down the PFN type to unsigned long.
> 
> Signed-off-by: Cyril Chemparathy <cyril@ti.com>

Acked-by: Nicolas Pitre <nico@linaro.org>

> ---
>  arch/arm/include/asm/memory.h |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
> index f3a7f76..32e9e5a 100644
> --- a/arch/arm/include/asm/memory.h
> +++ b/arch/arm/include/asm/memory.h
> @@ -223,7 +223,7 @@ static inline unsigned long __phys_to_virt(unsigned long x)
>   * direct-mapped view.  We assume this is the first page
>   * of RAM in the mem_map as well.
>   */
> -#define PHYS_PFN_OFFSET	(PHYS_OFFSET >> PAGE_SHIFT)
> +#define PHYS_PFN_OFFSET	((unsigned long)(PHYS_OFFSET >> PAGE_SHIFT))
>  
>  /*
>   * These are *only* valid on the kernel direct mapped RAM memory.
> -- 
> 1.7.9.5
> 

Re: [PATCH v4 00/13] ARM LPAE Fixes - Part 1

[Nicolas Pitre]

On Thu, 31 Jan 2013, Cyril Chemparathy wrote:

> This series is a repost of the LPAE related changes in preparation for the
> introduction of the Keystone sub-architecture.  The original series has now
> been split, and this particular series excludes the earlier changes to the
> runtime code patching implementation.  Earlier versions of this series can be
> found at [1], [2], [3] and [4].
> 
> These patches are also available in git:
> git://git.kernel.org/pub/scm/linux/kernel/git/cchemparathy/linux-keystone.git upstream/keystone-lpae-v4

This part 1 looks very nice.  It received many review cycles already as 
well.  It would be about time it goes upstream.

I think it is ready to be merged in Russell's tree.  Feel free to send 
him a pull request whenever you're ready.

Then we'll be free to look at the more controvertial p2v patching stuff.


Nicolas

Re: [PATCH v4 02/13] ARM: LPAE: use phys_addr_t in alloc_init_pud()

[Hui Wang]

Nicolas Pitre wrote:
> On Fri, 1 Feb 2013, Hui Wang wrote:
>
>   
>> Cyril Chemparathy wrote:
>>     
>>> From: Vitaly Andrianov <vitalya@ti.com>
>>>
>>> This patch fixes the alloc_init_pud() function to use phys_addr_t instead of
>>> unsigned long when passing in the phys argument.
>>>
>>> This is an extension to commit 97092e0c56830457af0639f6bd904537a150ea4a
>>> (ARM:
>>> pgtable: use phys_addr_t for physical addresses), which applied similar
>>> changes
>>> elsewhere in the ARM memory management code.
>>>
>>> Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
>>> Signed-off-by: Cyril Chemparathy <cyril@ti.com>
>>> Acked-by: Nicolas Pitre <nico@linaro.org>
>>> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
>>> ---
>>>  arch/arm/mm/mmu.c |    3 ++-
>>>  1 file changed, 2 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
>>> index 9f06102..ef43689 100644
>>> --- a/arch/arm/mm/mmu.c
>>> +++ b/arch/arm/mm/mmu.c
>>> @@ -612,7 +612,8 @@ static void __init alloc_init_section(pud_t *pud,
>>> unsigned long addr,
>>>  }
>>>   static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
>>> -	unsigned long end, unsigned long phys, const struct mem_type *type)
>>> +				  unsigned long end, phys_addr_t phys,
>>> +				  const struct mem_type *type)
>>>   
>>>       
>> The change is correct but seems useless so far. This function only be called
>> from map_lowmem and devicemaps_init, from i know neither lowmem nor device io
>> registers of existing platforms exceed 32bit address.
>>     
>
> It is not because you are not aware of any existing platforms with RAM 
> or device IO above the 4GB mark that they don't exist.
>
> For example, some LPAE systems have all their RAM located above the 4G 
> physical address mark. A simple (potentially non DMA capable) alias 
> exists in the low 32-bit address space to allow the system to boot and 
> switch to the real physical RAM addresses once the MMU is turned on.  
> Some of that RAM is still qualified as "low mem" i.e. the portion of RAM 
> that the kernel keeps permanently mapped in the 32-bit virtual space 
> even if all of it is above the 4G mark in physical space.
>
>
>   
Got it, thanks for sharing the knowledge.

Regards,
Hui.
> Nicolas
>
>   

Re: [PATCH v4 00/13] ARM LPAE Fixes - Part 1

[Cyril Chemparathy]

Hi Nico,

On 01/31/2013 11:00 PM, Nicolas Pitre wrote:
> On Thu, 31 Jan 2013, Cyril Chemparathy wrote:
>
>> This series is a repost of the LPAE related changes in preparation for the
>> introduction of the Keystone sub-architecture.  The original series has now
>> been split, and this particular series excludes the earlier changes to the
>> runtime code patching implementation.  Earlier versions of this series can be
>> found at [1], [2], [3] and [4].
>>
>> These patches are also available in git:
>> git://git.kernel.org/pub/scm/linux/kernel/git/cchemparathy/linux-keystone.git upstream/keystone-lpae-v4
>
> This part 1 looks very nice.  It received many review cycles already as
> well.  It would be about time it goes upstream.
>
> I think it is ready to be merged in Russell's tree.  Feel free to send
> him a pull request whenever you're ready.
>

Great.  I'll apply your acks and post a pull request.

> Then we'll be free to look at the more controvertial p2v patching stuff.
>

On the P2V patching stuff, I've implemented an alternative approach to 
get past this problem.  Essentially, the new implementation retains the 
kernel location detection part, but avoids the code patching by using 
simple inline P2V and V2P functions that use the offset detected early 
on in boot.

With this, I ran simple network and filesystem performance tests to 
compare the code-patching vs. non-code-patching variants.  These tests 
didn't yield any significant performance difference between the two on 
an ARMv7 (Cortex-A8) platform.

This series is basically operational at this point, but it needs a bit 
more test coverage before I post it out.

Thanks
-- Cyril.

Re: [PATCH v4 00/13] ARM LPAE Fixes - Part 1

[Russell King - ARM Linux]

On Fri, Feb 01, 2013 at 10:10:37AM -0500, Cyril Chemparathy wrote:
> With this, I ran simple network and filesystem performance tests to  
> compare the code-patching vs. non-code-patching variants.  These tests  
> didn't yield any significant performance difference between the two on  
> an ARMv7 (Cortex-A8) platform.

It's not network and fs activity that this kind of stuff is likely to
show up in, but more to do with walking pages tables and the like -
remember that page tables are stored using physical addresses, and any
walks of them have to convert those physical addresses to virtual
addresses and back again.

So, things like page scanning for eviction (eg, page aging, page
faults even those which just re-use a page from the page cache) have
to use the v:p / p:v translation macros.

Re: [PATCH v4 00/13] ARM LPAE Fixes - Part 1

[Cyril Chemparathy]

On 02/01/2013 10:14 AM, Russell King - ARM Linux wrote:
> On Fri, Feb 01, 2013 at 10:10:37AM -0500, Cyril Chemparathy wrote:
>> With this, I ran simple network and filesystem performance tests to
>> compare the code-patching vs. non-code-patching variants.  These tests
>> didn't yield any significant performance difference between the two on
>> an ARMv7 (Cortex-A8) platform.
>
> It's not network and fs activity that this kind of stuff is likely to
> show up in, but more to do with walking pages tables and the like -
> remember that page tables are stored using physical addresses, and any
> walks of them have to convert those physical addresses to virtual
> addresses and back again.
>
> So, things like page scanning for eviction (eg, page aging, page
> faults even those which just re-use a page from the page cache) have
> to use the v:p / p:v translation macros.
>

Thanks, Russell.  Any recommendations on how to best benchmark this?

Thanks
-- Cyril.

Re: [PATCH v4 02/13] ARM: LPAE: use phys_addr_t in alloc_init_pud()

[Subash Patel]

Hi Nicolas,

On Thursday 31 January 2013 07:35 PM, Nicolas Pitre wrote:
> On Fri, 1 Feb 2013, Hui Wang wrote:
>
>> Cyril Chemparathy wrote:
>>> From: Vitaly Andrianov <vitalya@ti.com>
>>>
>>> This patch fixes the alloc_init_pud() function to use phys_addr_t instead of
>>> unsigned long when passing in the phys argument.
>>>
>>> This is an extension to commit 97092e0c56830457af0639f6bd904537a150ea4a
>>> (ARM:
>>> pgtable: use phys_addr_t for physical addresses), which applied similar
>>> changes
>>> elsewhere in the ARM memory management code.
>>>
>>> Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
>>> Signed-off-by: Cyril Chemparathy <cyril@ti.com>
>>> Acked-by: Nicolas Pitre <nico@linaro.org>
>>> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
>>> ---
>>>   arch/arm/mm/mmu.c |    3 ++-
>>>   1 file changed, 2 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
>>> index 9f06102..ef43689 100644
>>> --- a/arch/arm/mm/mmu.c
>>> +++ b/arch/arm/mm/mmu.c
>>> @@ -612,7 +612,8 @@ static void __init alloc_init_section(pud_t *pud,
>>> unsigned long addr,
>>>   }
>>>    static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
>>> -	unsigned long end, unsigned long phys, const struct mem_type *type)
>>> +				  unsigned long end, phys_addr_t phys,
>>> +				  const struct mem_type *type)
>>>
>> The change is correct but seems useless so far. This function only be called
>> from map_lowmem and devicemaps_init, from i know neither lowmem nor device io
>> registers of existing platforms exceed 32bit address.
>
> It is not because you are not aware of any existing platforms with RAM
> or device IO above the 4GB mark that they don't exist.
>
> For example, some LPAE systems have all their RAM located above the 4G
> physical address mark. A simple (potentially non DMA capable) alias
> exists in the low 32-bit address space to allow the system to boot and
> switch to the real physical RAM addresses once the MMU is turned on.
> Some of that RAM is still qualified as "low mem" i.e. the portion of RAM
> that the kernel keeps permanently mapped in the 32-bit virtual space
> even if all of it is above the 4G mark in physical space.

I think he is right. You cannot have low_mem and devices in 36-bit 
areas. Atleast this is what I saw in one of the platforms on which I 
tested these patches. I am not sure what you mean by hardware address 
aliasing(as I have real RAM), but we need 32-bit areas to boot the CPU 
and I have mapped them for the LOW_MEM. But, I have used 36-bit areas 
for the HIGH_MEM. Since you said about aliasing DDR area in 32-bits, and 
then switching to 36-bit RAM, does the dma of the devices still use 
32-bit aliased addresses?

I haven't tested a configuration where LOW_MEM can have both 32-bit and 
36-bit DDR PA though. I think its not possible too.

Regards,
Subash


>
>
> Nicolas
> --
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>

Re: [PATCH v4 00/13] ARM LPAE Fixes - Part 1

[Nicolas Pitre]

On Fri, 1 Feb 2013, Cyril Chemparathy wrote:

> On 02/01/2013 10:14 AM, Russell King - ARM Linux wrote:
> > On Fri, Feb 01, 2013 at 10:10:37AM -0500, Cyril Chemparathy wrote:
> > > With this, I ran simple network and filesystem performance tests to
> > > compare the code-patching vs. non-code-patching variants.  These tests
> > > didn't yield any significant performance difference between the two on
> > > an ARMv7 (Cortex-A8) platform.
> > 
> > It's not network and fs activity that this kind of stuff is likely to
> > show up in, but more to do with walking pages tables and the like -
> > remember that page tables are stored using physical addresses, and any
> > walks of them have to convert those physical addresses to virtual
> > addresses and back again.
> > 
> > So, things like page scanning for eviction (eg, page aging, page
> > faults even those which just re-use a page from the page cache) have
> > to use the v:p / p:v translation macros.
> > 
> 
> Thanks, Russell.  Any recommendations on how to best benchmark this?

Well, the benchmark issue can be side-stepped altogether.  We know that 
the assembly patching is the best thing that can be done, and we do have 
most of it already.

As previously stated, the p2v patching may remain essentially identical 
to what we have right now.  Since the result is a 32-bit value, the 
current code should just work.

On the v2p side, it's just a matter of adding two instructions around 
the existing one (which should be turned into an adds).  The first is a 
mov to load the high bits of PHYS_OFFSET which are likely to be 
representable with a simple immediate operand, and the third one would 
be a simple adc with #0 which doesn't need any patching.


Nicolas

Re: [PATCH v4 02/13] ARM: LPAE: use phys_addr_t in alloc_init_pud()

[Cyril Chemparathy]

On 02/01/2013 12:33 PM, Subash Patel wrote:
> Hi Nicolas,
>
> On Thursday 31 January 2013 07:35 PM, Nicolas Pitre wrote:
>> On Fri, 1 Feb 2013, Hui Wang wrote:
>>
>>> Cyril Chemparathy wrote:
>>>> From: Vitaly Andrianov <vitalya@ti.com>
>>>>
>>>> This patch fixes the alloc_init_pud() function to use phys_addr_t
>>>> instead of
>>>> unsigned long when passing in the phys argument.
>>>>
>>>> This is an extension to commit 97092e0c56830457af0639f6bd904537a150ea4a
>>>> (ARM:
>>>> pgtable: use phys_addr_t for physical addresses), which applied similar
>>>> changes
>>>> elsewhere in the ARM memory management code.
>>>>
>>>> Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
>>>> Signed-off-by: Cyril Chemparathy <cyril@ti.com>
>>>> Acked-by: Nicolas Pitre <nico@linaro.org>
>>>> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
>>>> ---
>>>>   arch/arm/mm/mmu.c |    3 ++-
>>>>   1 file changed, 2 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
>>>> index 9f06102..ef43689 100644
>>>> --- a/arch/arm/mm/mmu.c
>>>> +++ b/arch/arm/mm/mmu.c
>>>> @@ -612,7 +612,8 @@ static void __init alloc_init_section(pud_t *pud,
>>>> unsigned long addr,
>>>>   }
>>>>    static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
>>>> -    unsigned long end, unsigned long phys, const struct mem_type
>>>> *type)
>>>> +                  unsigned long end, phys_addr_t phys,
>>>> +                  const struct mem_type *type)
>>>>
>>> The change is correct but seems useless so far. This function only be
>>> called
>>> from map_lowmem and devicemaps_init, from i know neither lowmem nor
>>> device io
>>> registers of existing platforms exceed 32bit address.
>>
>> It is not because you are not aware of any existing platforms with RAM
>> or device IO above the 4GB mark that they don't exist.
>>
>> For example, some LPAE systems have all their RAM located above the 4G
>> physical address mark. A simple (potentially non DMA capable) alias
>> exists in the low 32-bit address space to allow the system to boot and
>> switch to the real physical RAM addresses once the MMU is turned on.
>> Some of that RAM is still qualified as "low mem" i.e. the portion of RAM
>> that the kernel keeps permanently mapped in the 32-bit virtual space
>> even if all of it is above the 4G mark in physical space.
>
> I think he is right. You cannot have low_mem and devices in 36-bit
> areas. Atleast this is what I saw in one of the platforms on which I
> tested these patches. I am not sure what you mean by hardware address
> aliasing(as I have real RAM), but we need 32-bit areas to boot the CPU
> and I have mapped them for the LOW_MEM. But, I have used 36-bit areas
> for the HIGH_MEM. Since you said about aliasing DDR area in 32-bits, and
> then switching to 36-bit RAM, does the dma of the devices still use
> 32-bit aliased addresses?
>
> I haven't tested a configuration where LOW_MEM can have both 32-bit and
> 36-bit DDR PA though. I think its not possible too.
>

On the KeyStone platform, memory is located at 08:0000:0000, i.e., 
outside the 32-bit addressable range.  The hardware provides a limited 
aliased map of the very same memory at 8000:0000, but this alias is 
limited and intended only for boot time usage.

We boot the system while running out of this 32-bit physical address 
range.  We then switch over to the high physical address range fairly 
early in the kernel boot, by rewriting boot-time page tables and the 
TTBRs.  Once this switch over has happened, lowmem is indeed outside the 
32-bit physical address space.

Thanks
-- Cyril.

Re: [PATCH v4 02/13] ARM: LPAE: use phys_addr_t in alloc_init_pud()

[Nicolas Pitre]

On Fri, 1 Feb 2013, Subash Patel wrote:

> Hi Nicolas,
> 
> On Thursday 31 January 2013 07:35 PM, Nicolas Pitre wrote:
> > On Fri, 1 Feb 2013, Hui Wang wrote:
> > 
> > > Cyril Chemparathy wrote:
> > > > From: Vitaly Andrianov <vitalya@ti.com>
> > > > 
> > > > This patch fixes the alloc_init_pud() function to use phys_addr_t
> > > > instead of
> > > > unsigned long when passing in the phys argument.
> > > > 
> > > > This is an extension to commit 97092e0c56830457af0639f6bd904537a150ea4a
> > > > (ARM:
> > > > pgtable: use phys_addr_t for physical addresses), which applied similar
> > > > changes
> > > > elsewhere in the ARM memory management code.
> > > > 
> > > > Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
> > > > Signed-off-by: Cyril Chemparathy <cyril@ti.com>
> > > > Acked-by: Nicolas Pitre <nico@linaro.org>
> > > > Acked-by: Catalin Marinas <catalin.marinas@arm.com>
> > > > ---
> > > >   arch/arm/mm/mmu.c |    3 ++-
> > > >   1 file changed, 2 insertions(+), 1 deletion(-)
> > > > 
> > > > diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
> > > > index 9f06102..ef43689 100644
> > > > --- a/arch/arm/mm/mmu.c
> > > > +++ b/arch/arm/mm/mmu.c
> > > > @@ -612,7 +612,8 @@ static void __init alloc_init_section(pud_t *pud,
> > > > unsigned long addr,
> > > >   }
> > > >    static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
> > > > -	unsigned long end, unsigned long phys, const struct mem_type *type)
> > > > +				  unsigned long end, phys_addr_t phys,
> > > > +				  const struct mem_type *type)
> > > > 
> > > The change is correct but seems useless so far. This function only be
> > > called
> > > from map_lowmem and devicemaps_init, from i know neither lowmem nor device
> > > io
> > > registers of existing platforms exceed 32bit address.
> > 
> > It is not because you are not aware of any existing platforms with RAM
> > or device IO above the 4GB mark that they don't exist.
> > 
> > For example, some LPAE systems have all their RAM located above the 4G
> > physical address mark. A simple (potentially non DMA capable) alias
> > exists in the low 32-bit address space to allow the system to boot and
> > switch to the real physical RAM addresses once the MMU is turned on.
> > Some of that RAM is still qualified as "low mem" i.e. the portion of RAM
> > that the kernel keeps permanently mapped in the 32-bit virtual space
> > even if all of it is above the 4G mark in physical space.
> 
> I think he is right. You cannot have low_mem and devices in 36-bit areas.
> Atleast this is what I saw in one of the platforms on which I tested these
> patches. I am not sure what you mean by hardware address aliasing(as I have
> real RAM), but we need 32-bit areas to boot the CPU and I have mapped them for
> the LOW_MEM. But, I have used 36-bit areas for the HIGH_MEM. Since you said
> about aliasing DDR area in 32-bits, and then switching to 36-bit RAM, does the
> dma of the devices still use 32-bit aliased addresses?
> 
> I haven't tested a configuration where LOW_MEM can have both 32-bit and 36-bit
> DDR PA though. I think its not possible too.

Don't get confused by the 36-bit supersections introduced with ARMv6.  
This patch series is about LPAE capable systems using a completely 
different page table format providing physical addressing beyond 36 
bits.


Nicolas

Re: [PATCH v4 00/13] ARM LPAE Fixes - Part 1

[Subash Patel]

Hi Cyril,

Thanks for posting fixes patch set again. I have in fact used your 
previous patch series on a real LPAE system with split memory banks in 
both 32-bit and 36-bit physical addresses. I compared your below patches 
with previous version, and don't see significant changes. Hence you can use

Tested By: Subash Patel <subash.rp@samsung.com>

for this series as well. In the meantime, I have used the pa/va patching 
from v3, but haven't tested any performance numbers on it. But I will 
wait for your next reworked version.

Regards,
Subash

On Thursday 31 January 2013 01:58 PM, Cyril Chemparathy wrote:
> This series is a repost of the LPAE related changes in preparation for the
> introduction of the Keystone sub-architecture.  The original series has now
> been split, and this particular series excludes the earlier changes to the
> runtime code patching implementation.  Earlier versions of this series can be
> found at [1], [2], [3] and [4].
>
> These patches are also available in git:
> git://git.kernel.org/pub/scm/linux/kernel/git/cchemparathy/linux-keystone.git upstream/keystone-lpae-v4
>
> [1] http://comments.gmane.org/gmane.linux.kernel/1341497
> [2] http://comments.gmane.org/gmane.linux.kernel/1332069
> [3] http://comments.gmane.org/gmane.linux.kernel/1356716
> [4] http://comments.gmane.org/gmane.linux.kernel/1362529
>
> Series changelog:
>
> [01/13] ARM: LPAE: use signed arithmetic for mask
> [02/13] ARM: LPAE: use phys_addr_t in alloc_init_pud()
> [03/13] ARM: LPAE: use phys_addr_t in free_memmap()
>    (v4)	unchanged from v3
>    (v3)	unchanged from v2
>    (v2)	unchanged from v1
>
> [04/13] ARM: LPAE: use phys_addr_t for initrd location
>    (v4)	unchanged from v3
>    (v3)	unchanged from v2
>    (v2)	revert to unsigned long for initrd size
>
> [05/13] ARM: LPAE: use phys_addr_t in switch_mm()
>    (v4)  collapse shift and or into a single instruction
>    (v3)	remove unnecessary handling for !LPAE in proc-v7-3level
>    (v2)	use phys_addr_t instead of u64 in switch_mm()
>    (v2)	revert on changes to v6 and v7-2level
>    (v2)	fix register mapping for big-endian in v7-3level
>
> [06/13] ARM: LPAE: use 64-bit accessors for TTBR registers
>    (v4)  remove unnecessary condition code clobber
>    (v3)	remove unnecessary condition code clobber
>    (v2)	restore comment in cpu_set_reserved_ttbr0()
>
> [07/13] ARM: LPAE: define ARCH_LOW_ADDRESS_LIMIT for
>    (v4)	unchanged from v3
>    (v3)	unchanged from v2
>    (v2)	unchanged from v1
>
> [08/13] ARM: LPAE: factor out T1SZ and TTBR1 computations
>    (v4)  cleanup and move code comments
>    (v3)	unchanged from v2
>    (v2)	unchanged from v1
>
> [09/13] ARM: LPAE: accomodate >32-bit addresses for page
>    (v4)	unchanged from v3
>    (v3)	unchanged from v2
>    (v2)	apply arch_pgd_shift only on lpae
>    (v2)	move arch_pgd_shift definition to asm/memory.h
>    (v2)	revert on changes to non-lpae procs
>    (v2)	add check to ensure that the pgd physical address is aligned at an
> 	ARCH_PGD_SHIFT boundary
>
> [10/13] ARM: mm: use physical addresses in highmem sanity
> [11/13] ARM: mm: cleanup checks for membank overlap with
> [12/13] ARM: mm: clean up membank size limit checks
>    (v4)	unchanged from v3
>    (v3)	unchanged from v2
>    (v2)	unchanged from v1
>
> [13/13] ARM: fix type of PHYS_PFN_OFFSET to unsigned long
>    (v4)	introduced here
>
>
> Cyril Chemparathy (10):
>    ARM: LPAE: use signed arithmetic for mask definitions
>    ARM: LPAE: use phys_addr_t in switch_mm()
>    ARM: LPAE: use 64-bit accessors for TTBR registers
>    ARM: LPAE: define ARCH_LOW_ADDRESS_LIMIT for bootmem
>    ARM: LPAE: factor out T1SZ and TTBR1 computations
>    ARM: LPAE: accomodate >32-bit addresses for page table base
>    ARM: mm: use physical addresses in highmem sanity checks
>    ARM: mm: cleanup checks for membank overlap with vmalloc area
>    ARM: mm: clean up membank size limit checks
>    ARM: fix type of PHYS_PFN_OFFSET to unsigned long
>
> Vitaly Andrianov (3):
>    ARM: LPAE: use phys_addr_t in alloc_init_pud()
>    ARM: LPAE: use phys_addr_t in free_memmap()
>    ARM: LPAE: use phys_addr_t for initrd location
>
>   arch/arm/include/asm/memory.h               |   20 +++++++++-
>   arch/arm/include/asm/page.h                 |    2 +-
>   arch/arm/include/asm/pgtable-3level-hwdef.h |   20 ++++++++++
>   arch/arm/include/asm/pgtable-3level.h       |    6 +--
>   arch/arm/include/asm/proc-fns.h             |   26 +++++++++----
>   arch/arm/kernel/head.S                      |   10 ++---
>   arch/arm/kernel/smp.c                       |   11 +++++-
>   arch/arm/mm/context.c                       |    9 +----
>   arch/arm/mm/init.c                          |   19 +++++-----
>   arch/arm/mm/mmu.c                           |   49 +++++++++----------------
>   arch/arm/mm/proc-v7-3level.S                |   53 ++++++++++++++-------------
>   11 files changed, 132 insertions(+), 93 deletions(-)
>

Re: [PATCH v4 02/13] ARM: LPAE: use phys_addr_t in alloc_init_pud()

[Subash Patel]

On Friday 01 February 2013 10:14 AM, Nicolas Pitre wrote:
> On Fri, 1 Feb 2013, Subash Patel wrote:
>
>> Hi Nicolas,
>>
>> On Thursday 31 January 2013 07:35 PM, Nicolas Pitre wrote:
>>> On Fri, 1 Feb 2013, Hui Wang wrote:
>>>
>>>> Cyril Chemparathy wrote:
>>>>> From: Vitaly Andrianov <vitalya@ti.com>
>>>>>
>>>>> This patch fixes the alloc_init_pud() function to use phys_addr_t
>>>>> instead of
>>>>> unsigned long when passing in the phys argument.
>>>>>
>>>>> This is an extension to commit 97092e0c56830457af0639f6bd904537a150ea4a
>>>>> (ARM:
>>>>> pgtable: use phys_addr_t for physical addresses), which applied similar
>>>>> changes
>>>>> elsewhere in the ARM memory management code.
>>>>>
>>>>> Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
>>>>> Signed-off-by: Cyril Chemparathy <cyril@ti.com>
>>>>> Acked-by: Nicolas Pitre <nico@linaro.org>
>>>>> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
>>>>> ---
>>>>>    arch/arm/mm/mmu.c |    3 ++-
>>>>>    1 file changed, 2 insertions(+), 1 deletion(-)
>>>>>
>>>>> diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
>>>>> index 9f06102..ef43689 100644
>>>>> --- a/arch/arm/mm/mmu.c
>>>>> +++ b/arch/arm/mm/mmu.c
>>>>> @@ -612,7 +612,8 @@ static void __init alloc_init_section(pud_t *pud,
>>>>> unsigned long addr,
>>>>>    }
>>>>>     static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
>>>>> -	unsigned long end, unsigned long phys, const struct mem_type *type)
>>>>> +				  unsigned long end, phys_addr_t phys,
>>>>> +				  const struct mem_type *type)
>>>>>
>>>> The change is correct but seems useless so far. This function only be
>>>> called
>>>> from map_lowmem and devicemaps_init, from i know neither lowmem nor device
>>>> io
>>>> registers of existing platforms exceed 32bit address.
>>>
>>> It is not because you are not aware of any existing platforms with RAM
>>> or device IO above the 4GB mark that they don't exist.
>>>
>>> For example, some LPAE systems have all their RAM located above the 4G
>>> physical address mark. A simple (potentially non DMA capable) alias
>>> exists in the low 32-bit address space to allow the system to boot and
>>> switch to the real physical RAM addresses once the MMU is turned on.
>>> Some of that RAM is still qualified as "low mem" i.e. the portion of RAM
>>> that the kernel keeps permanently mapped in the 32-bit virtual space
>>> even if all of it is above the 4G mark in physical space.
>>
>> I think he is right. You cannot have low_mem and devices in 36-bit areas.
>> Atleast this is what I saw in one of the platforms on which I tested these
>> patches. I am not sure what you mean by hardware address aliasing(as I have
>> real RAM), but we need 32-bit areas to boot the CPU and I have mapped them for
>> the LOW_MEM. But, I have used 36-bit areas for the HIGH_MEM. Since you said
>> about aliasing DDR area in 32-bits, and then switching to 36-bit RAM, does the
>> dma of the devices still use 32-bit aliased addresses?
>>
>> I haven't tested a configuration where LOW_MEM can have both 32-bit and 36-bit
>> DDR PA though. I think its not possible too.
>
> Don't get confused by the 36-bit supersections introduced with ARMv6.
> This patch series is about LPAE capable systems using a completely
> different page table format providing physical addressing beyond 36
> bits.

Yes, I mean LPAE capable MMU's introduced with Cortex-A15. Infact I have 
programmed that MMU with 1G super-section for non-linux usage :) Cyril 
explained his platform and aliasing. My platform has a real memory in 
32-bit area, and we use it for 32-bit DMA's as well. So it looks we are 
speaking of various configurations of LPAE systems here.

Regards,
Subash

>
>
> Nicolas
>